1 | // SPDX-License-Identifier: GPL-2.0 |
2 | // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. |
3 | |
4 | /* Disable MMIO tracing to prevent excessive logging of unwanted MMIO traces */ |
5 | #define __DISABLE_TRACE_MMIO__ |
6 | |
7 | #include <linux/acpi.h> |
8 | #include <linux/clk.h> |
9 | #include <linux/slab.h> |
10 | #include <linux/dma-mapping.h> |
11 | #include <linux/io.h> |
12 | #include <linux/module.h> |
13 | #include <linux/of.h> |
14 | #include <linux/of_platform.h> |
15 | #include <linux/pinctrl/consumer.h> |
16 | #include <linux/platform_device.h> |
17 | #include <linux/soc/qcom/geni-se.h> |
18 | |
19 | /** |
20 | * DOC: Overview |
21 | * |
22 | * Generic Interface (GENI) Serial Engine (SE) Wrapper driver is introduced |
23 | * to manage GENI firmware based Qualcomm Universal Peripheral (QUP) Wrapper |
24 | * controller. QUP Wrapper is designed to support various serial bus protocols |
25 | * like UART, SPI, I2C, I3C, etc. |
26 | */ |
27 | |
28 | /** |
29 | * DOC: Hardware description |
30 | * |
31 | * GENI based QUP is a highly-flexible and programmable module for supporting |
32 | * a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. A single |
33 | * QUP module can provide upto 8 serial interfaces, using its internal |
34 | * serial engines. The actual configuration is determined by the target |
35 | * platform configuration. The protocol supported by each interface is |
36 | * determined by the firmware loaded to the serial engine. Each SE consists |
37 | * of a DMA Engine and GENI sub modules which enable serial engines to |
38 | * support FIFO and DMA modes of operation. |
39 | * |
40 | * |
41 | * +-----------------------------------------+ |
42 | * |QUP Wrapper | |
43 | * | +----------------------------+ | |
44 | * --QUP & SE Clocks--> | Serial Engine N | +-IO------> |
45 | * | | ... | | Interface |
46 | * <---Clock Perf.----+ +----+-----------------------+ | | |
47 | * State Interface | | Serial Engine 1 | | | |
48 | * | | | | | |
49 | * | | | | | |
50 | * <--------AHB-------> | | | | |
51 | * | | +----+ | |
52 | * | | | | |
53 | * | | | | |
54 | * <------SE IRQ------+ +----------------------------+ | |
55 | * | | |
56 | * +-----------------------------------------+ |
57 | * |
58 | * Figure 1: GENI based QUP Wrapper |
59 | * |
60 | * The GENI submodules include primary and secondary sequencers which are |
61 | * used to drive TX & RX operations. On serial interfaces that operate using |
62 | * master-slave model, primary sequencer drives both TX & RX operations. On |
63 | * serial interfaces that operate using peer-to-peer model, primary sequencer |
64 | * drives TX operation and secondary sequencer drives RX operation. |
65 | */ |
66 | |
67 | /** |
68 | * DOC: Software description |
69 | * |
70 | * GENI SE Wrapper driver is structured into 2 parts: |
71 | * |
72 | * geni_wrapper represents QUP Wrapper controller. This part of the driver |
73 | * manages QUP Wrapper information such as hardware version, clock |
74 | * performance table that is common to all the internal serial engines. |
75 | * |
76 | * geni_se represents serial engine. This part of the driver manages serial |
77 | * engine information such as clocks, containing QUP Wrapper, etc. This part |
78 | * of driver also supports operations (eg. initialize the concerned serial |
79 | * engine, select between FIFO and DMA mode of operation etc.) that are |
80 | * common to all the serial engines and are independent of serial interfaces. |
81 | */ |
82 | |
83 | #define MAX_CLK_PERF_LEVEL 32 |
84 | #define MAX_CLKS 2 |
85 | |
86 | /** |
87 | * struct geni_wrapper - Data structure to represent the QUP Wrapper Core |
88 | * @dev: Device pointer of the QUP wrapper core |
89 | * @base: Base address of this instance of QUP wrapper core |
90 | * @clks: Handle to the primary & optional secondary AHB clocks |
91 | * @num_clks: Count of clocks |
92 | * @to_core: Core ICC path |
93 | */ |
94 | struct geni_wrapper { |
95 | struct device *dev; |
96 | void __iomem *base; |
97 | struct clk_bulk_data clks[MAX_CLKS]; |
98 | unsigned int num_clks; |
99 | }; |
100 | |
101 | /** |
102 | * struct geni_se_desc - Data structure to represent the QUP Wrapper resources |
103 | * @clks: Name of the primary & optional secondary AHB clocks |
104 | * @num_clks: Count of clock names |
105 | */ |
106 | struct geni_se_desc { |
107 | unsigned int num_clks; |
108 | const char * const *clks; |
109 | }; |
110 | |
111 | static const char * const icc_path_names[] = {"qup-core" , "qup-config" , |
112 | "qup-memory" }; |
113 | |
114 | #define QUP_HW_VER_REG 0x4 |
115 | |
116 | /* Common SE registers */ |
117 | #define GENI_INIT_CFG_REVISION 0x0 |
118 | #define GENI_S_INIT_CFG_REVISION 0x4 |
119 | #define GENI_OUTPUT_CTRL 0x24 |
120 | #define GENI_CGC_CTRL 0x28 |
121 | #define GENI_CLK_CTRL_RO 0x60 |
122 | #define GENI_FW_S_REVISION_RO 0x6c |
123 | #define SE_GENI_BYTE_GRAN 0x254 |
124 | #define SE_GENI_TX_PACKING_CFG0 0x260 |
125 | #define SE_GENI_TX_PACKING_CFG1 0x264 |
126 | #define SE_GENI_RX_PACKING_CFG0 0x284 |
127 | #define SE_GENI_RX_PACKING_CFG1 0x288 |
128 | #define SE_GENI_M_GP_LENGTH 0x910 |
129 | #define SE_GENI_S_GP_LENGTH 0x914 |
130 | #define SE_DMA_TX_PTR_L 0xc30 |
131 | #define SE_DMA_TX_PTR_H 0xc34 |
132 | #define SE_DMA_TX_ATTR 0xc38 |
133 | #define SE_DMA_TX_LEN 0xc3c |
134 | #define SE_DMA_TX_IRQ_EN 0xc48 |
135 | #define SE_DMA_TX_IRQ_EN_SET 0xc4c |
136 | #define SE_DMA_TX_IRQ_EN_CLR 0xc50 |
137 | #define SE_DMA_TX_LEN_IN 0xc54 |
138 | #define SE_DMA_TX_MAX_BURST 0xc5c |
139 | #define SE_DMA_RX_PTR_L 0xd30 |
140 | #define SE_DMA_RX_PTR_H 0xd34 |
141 | #define SE_DMA_RX_ATTR 0xd38 |
142 | #define SE_DMA_RX_LEN 0xd3c |
143 | #define SE_DMA_RX_IRQ_EN 0xd48 |
144 | #define SE_DMA_RX_IRQ_EN_SET 0xd4c |
145 | #define SE_DMA_RX_IRQ_EN_CLR 0xd50 |
146 | #define SE_DMA_RX_LEN_IN 0xd54 |
147 | #define SE_DMA_RX_MAX_BURST 0xd5c |
148 | #define SE_DMA_RX_FLUSH 0xd60 |
149 | #define SE_GSI_EVENT_EN 0xe18 |
150 | #define SE_IRQ_EN 0xe1c |
151 | #define SE_DMA_GENERAL_CFG 0xe30 |
152 | |
153 | /* GENI_OUTPUT_CTRL fields */ |
154 | #define DEFAULT_IO_OUTPUT_CTRL_MSK GENMASK(6, 0) |
155 | |
156 | /* GENI_CGC_CTRL fields */ |
157 | #define CFG_AHB_CLK_CGC_ON BIT(0) |
158 | #define CFG_AHB_WR_ACLK_CGC_ON BIT(1) |
159 | #define DATA_AHB_CLK_CGC_ON BIT(2) |
160 | #define SCLK_CGC_ON BIT(3) |
161 | #define TX_CLK_CGC_ON BIT(4) |
162 | #define RX_CLK_CGC_ON BIT(5) |
163 | #define EXT_CLK_CGC_ON BIT(6) |
164 | #define PROG_RAM_HCLK_OFF BIT(8) |
165 | #define PROG_RAM_SCLK_OFF BIT(9) |
166 | #define DEFAULT_CGC_EN GENMASK(6, 0) |
167 | |
168 | /* SE_GSI_EVENT_EN fields */ |
169 | #define DMA_RX_EVENT_EN BIT(0) |
170 | #define DMA_TX_EVENT_EN BIT(1) |
171 | #define GENI_M_EVENT_EN BIT(2) |
172 | #define GENI_S_EVENT_EN BIT(3) |
173 | |
174 | /* SE_IRQ_EN fields */ |
175 | #define DMA_RX_IRQ_EN BIT(0) |
176 | #define DMA_TX_IRQ_EN BIT(1) |
177 | #define GENI_M_IRQ_EN BIT(2) |
178 | #define GENI_S_IRQ_EN BIT(3) |
179 | |
180 | /* SE_DMA_GENERAL_CFG */ |
181 | #define DMA_RX_CLK_CGC_ON BIT(0) |
182 | #define DMA_TX_CLK_CGC_ON BIT(1) |
183 | #define DMA_AHB_SLV_CFG_ON BIT(2) |
184 | #define AHB_SEC_SLV_CLK_CGC_ON BIT(3) |
185 | #define DUMMY_RX_NON_BUFFERABLE BIT(4) |
186 | #define RX_DMA_ZERO_PADDING_EN BIT(5) |
187 | #define RX_DMA_IRQ_DELAY_MSK GENMASK(8, 6) |
188 | #define RX_DMA_IRQ_DELAY_SHFT 6 |
189 | |
190 | /** |
191 | * geni_se_get_qup_hw_version() - Read the QUP wrapper Hardware version |
192 | * @se: Pointer to the corresponding serial engine. |
193 | * |
194 | * Return: Hardware Version of the wrapper. |
195 | */ |
196 | u32 geni_se_get_qup_hw_version(struct geni_se *se) |
197 | { |
198 | struct geni_wrapper *wrapper = se->wrapper; |
199 | |
200 | return readl_relaxed(wrapper->base + QUP_HW_VER_REG); |
201 | } |
202 | EXPORT_SYMBOL_GPL(geni_se_get_qup_hw_version); |
203 | |
204 | static void geni_se_io_set_mode(void __iomem *base) |
205 | { |
206 | u32 val; |
207 | |
208 | val = readl_relaxed(base + SE_IRQ_EN); |
209 | val |= GENI_M_IRQ_EN | GENI_S_IRQ_EN; |
210 | val |= DMA_TX_IRQ_EN | DMA_RX_IRQ_EN; |
211 | writel_relaxed(val, base + SE_IRQ_EN); |
212 | |
213 | val = readl_relaxed(base + SE_GENI_DMA_MODE_EN); |
214 | val &= ~GENI_DMA_MODE_EN; |
215 | writel_relaxed(val, base + SE_GENI_DMA_MODE_EN); |
216 | |
217 | writel_relaxed(0, base + SE_GSI_EVENT_EN); |
218 | } |
219 | |
220 | static void geni_se_io_init(void __iomem *base) |
221 | { |
222 | u32 val; |
223 | |
224 | val = readl_relaxed(base + GENI_CGC_CTRL); |
225 | val |= DEFAULT_CGC_EN; |
226 | writel_relaxed(val, base + GENI_CGC_CTRL); |
227 | |
228 | val = readl_relaxed(base + SE_DMA_GENERAL_CFG); |
229 | val |= AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CFG_ON; |
230 | val |= DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON; |
231 | writel_relaxed(val, base + SE_DMA_GENERAL_CFG); |
232 | |
233 | writel_relaxed(DEFAULT_IO_OUTPUT_CTRL_MSK, base + GENI_OUTPUT_CTRL); |
234 | writel_relaxed(FORCE_DEFAULT, base + GENI_FORCE_DEFAULT_REG); |
235 | } |
236 | |
237 | static void geni_se_irq_clear(struct geni_se *se) |
238 | { |
239 | writel_relaxed(0, se->base + SE_GSI_EVENT_EN); |
240 | writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR); |
241 | writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR); |
242 | writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR); |
243 | writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR); |
244 | writel_relaxed(0xffffffff, se->base + SE_IRQ_EN); |
245 | } |
246 | |
247 | /** |
248 | * geni_se_init() - Initialize the GENI serial engine |
249 | * @se: Pointer to the concerned serial engine. |
250 | * @rx_wm: Receive watermark, in units of FIFO words. |
251 | * @rx_rfr: Ready-for-receive watermark, in units of FIFO words. |
252 | * |
253 | * This function is used to initialize the GENI serial engine, configure |
254 | * receive watermark and ready-for-receive watermarks. |
255 | */ |
256 | void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr) |
257 | { |
258 | u32 val; |
259 | |
260 | geni_se_irq_clear(se); |
261 | geni_se_io_init(base: se->base); |
262 | geni_se_io_set_mode(base: se->base); |
263 | |
264 | writel_relaxed(rx_wm, se->base + SE_GENI_RX_WATERMARK_REG); |
265 | writel_relaxed(rx_rfr, se->base + SE_GENI_RX_RFR_WATERMARK_REG); |
266 | |
267 | val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); |
268 | val |= M_COMMON_GENI_M_IRQ_EN; |
269 | writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); |
270 | |
271 | val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); |
272 | val |= S_COMMON_GENI_S_IRQ_EN; |
273 | writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); |
274 | } |
275 | EXPORT_SYMBOL_GPL(geni_se_init); |
276 | |
277 | static void geni_se_select_fifo_mode(struct geni_se *se) |
278 | { |
279 | u32 proto = geni_se_read_proto(se); |
280 | u32 val, val_old; |
281 | |
282 | geni_se_irq_clear(se); |
283 | |
284 | /* UART driver manages enabling / disabling interrupts internally */ |
285 | if (proto != GENI_SE_UART) { |
286 | /* Non-UART use only primary sequencer so dont bother about S_IRQ */ |
287 | val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); |
288 | val |= M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN; |
289 | val |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; |
290 | if (val != val_old) |
291 | writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); |
292 | } |
293 | |
294 | val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); |
295 | val &= ~GENI_DMA_MODE_EN; |
296 | if (val != val_old) |
297 | writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); |
298 | } |
299 | |
300 | static void geni_se_select_dma_mode(struct geni_se *se) |
301 | { |
302 | u32 proto = geni_se_read_proto(se); |
303 | u32 val, val_old; |
304 | |
305 | geni_se_irq_clear(se); |
306 | |
307 | /* UART driver manages enabling / disabling interrupts internally */ |
308 | if (proto != GENI_SE_UART) { |
309 | /* Non-UART use only primary sequencer so dont bother about S_IRQ */ |
310 | val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); |
311 | val &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN); |
312 | val &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); |
313 | if (val != val_old) |
314 | writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); |
315 | } |
316 | |
317 | val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); |
318 | val |= GENI_DMA_MODE_EN; |
319 | if (val != val_old) |
320 | writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); |
321 | } |
322 | |
323 | static void geni_se_select_gpi_mode(struct geni_se *se) |
324 | { |
325 | u32 val; |
326 | |
327 | geni_se_irq_clear(se); |
328 | |
329 | writel(val: 0, addr: se->base + SE_IRQ_EN); |
330 | |
331 | val = readl(addr: se->base + SE_GENI_M_IRQ_EN); |
332 | val &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN | |
333 | M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); |
334 | writel(val, addr: se->base + SE_GENI_M_IRQ_EN); |
335 | |
336 | writel(GENI_DMA_MODE_EN, addr: se->base + SE_GENI_DMA_MODE_EN); |
337 | |
338 | val = readl(addr: se->base + SE_GSI_EVENT_EN); |
339 | val |= (DMA_RX_EVENT_EN | DMA_TX_EVENT_EN | GENI_M_EVENT_EN | GENI_S_EVENT_EN); |
340 | writel(val, addr: se->base + SE_GSI_EVENT_EN); |
341 | } |
342 | |
343 | /** |
344 | * geni_se_select_mode() - Select the serial engine transfer mode |
345 | * @se: Pointer to the concerned serial engine. |
346 | * @mode: Transfer mode to be selected. |
347 | */ |
348 | void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode) |
349 | { |
350 | WARN_ON(mode != GENI_SE_FIFO && mode != GENI_SE_DMA && mode != GENI_GPI_DMA); |
351 | |
352 | switch (mode) { |
353 | case GENI_SE_FIFO: |
354 | geni_se_select_fifo_mode(se); |
355 | break; |
356 | case GENI_SE_DMA: |
357 | geni_se_select_dma_mode(se); |
358 | break; |
359 | case GENI_GPI_DMA: |
360 | geni_se_select_gpi_mode(se); |
361 | break; |
362 | case GENI_SE_INVALID: |
363 | default: |
364 | break; |
365 | } |
366 | } |
367 | EXPORT_SYMBOL_GPL(geni_se_select_mode); |
368 | |
369 | /** |
370 | * DOC: Overview |
371 | * |
372 | * GENI FIFO packing is highly configurable. TX/RX packing/unpacking consist |
373 | * of up to 4 operations, each operation represented by 4 configuration vectors |
374 | * of 10 bits programmed in GENI_TX_PACKING_CFG0 and GENI_TX_PACKING_CFG1 for |
375 | * TX FIFO and in GENI_RX_PACKING_CFG0 and GENI_RX_PACKING_CFG1 for RX FIFO. |
376 | * Refer to below examples for detailed bit-field description. |
377 | * |
378 | * Example 1: word_size = 7, packing_mode = 4 x 8, msb_to_lsb = 1 |
379 | * |
380 | * +-----------+-------+-------+-------+-------+ |
381 | * | | vec_0 | vec_1 | vec_2 | vec_3 | |
382 | * +-----------+-------+-------+-------+-------+ |
383 | * | start | 0x6 | 0xe | 0x16 | 0x1e | |
384 | * | direction | 1 | 1 | 1 | 1 | |
385 | * | length | 6 | 6 | 6 | 6 | |
386 | * | stop | 0 | 0 | 0 | 1 | |
387 | * +-----------+-------+-------+-------+-------+ |
388 | * |
389 | * Example 2: word_size = 15, packing_mode = 2 x 16, msb_to_lsb = 0 |
390 | * |
391 | * +-----------+-------+-------+-------+-------+ |
392 | * | | vec_0 | vec_1 | vec_2 | vec_3 | |
393 | * +-----------+-------+-------+-------+-------+ |
394 | * | start | 0x0 | 0x8 | 0x10 | 0x18 | |
395 | * | direction | 0 | 0 | 0 | 0 | |
396 | * | length | 7 | 6 | 7 | 6 | |
397 | * | stop | 0 | 0 | 0 | 1 | |
398 | * +-----------+-------+-------+-------+-------+ |
399 | * |
400 | * Example 3: word_size = 23, packing_mode = 1 x 32, msb_to_lsb = 1 |
401 | * |
402 | * +-----------+-------+-------+-------+-------+ |
403 | * | | vec_0 | vec_1 | vec_2 | vec_3 | |
404 | * +-----------+-------+-------+-------+-------+ |
405 | * | start | 0x16 | 0xe | 0x6 | 0x0 | |
406 | * | direction | 1 | 1 | 1 | 1 | |
407 | * | length | 7 | 7 | 6 | 0 | |
408 | * | stop | 0 | 0 | 1 | 0 | |
409 | * +-----------+-------+-------+-------+-------+ |
410 | * |
411 | */ |
412 | |
413 | #define NUM_PACKING_VECTORS 4 |
414 | #define PACKING_START_SHIFT 5 |
415 | #define PACKING_DIR_SHIFT 4 |
416 | #define PACKING_LEN_SHIFT 1 |
417 | #define PACKING_STOP_BIT BIT(0) |
418 | #define PACKING_VECTOR_SHIFT 10 |
419 | /** |
420 | * geni_se_config_packing() - Packing configuration of the serial engine |
421 | * @se: Pointer to the concerned serial engine |
422 | * @bpw: Bits of data per transfer word. |
423 | * @pack_words: Number of words per fifo element. |
424 | * @msb_to_lsb: Transfer from MSB to LSB or vice-versa. |
425 | * @tx_cfg: Flag to configure the TX Packing. |
426 | * @rx_cfg: Flag to configure the RX Packing. |
427 | * |
428 | * This function is used to configure the packing rules for the current |
429 | * transfer. |
430 | */ |
431 | void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words, |
432 | bool msb_to_lsb, bool tx_cfg, bool rx_cfg) |
433 | { |
434 | u32 cfg0, cfg1, cfg[NUM_PACKING_VECTORS] = {0}; |
435 | int len; |
436 | int temp_bpw = bpw; |
437 | int idx_start = msb_to_lsb ? bpw - 1 : 0; |
438 | int idx = idx_start; |
439 | int idx_delta = msb_to_lsb ? -BITS_PER_BYTE : BITS_PER_BYTE; |
440 | int ceil_bpw = ALIGN(bpw, BITS_PER_BYTE); |
441 | int iter = (ceil_bpw * pack_words) / BITS_PER_BYTE; |
442 | int i; |
443 | |
444 | if (iter <= 0 || iter > NUM_PACKING_VECTORS) |
445 | return; |
446 | |
447 | for (i = 0; i < iter; i++) { |
448 | len = min_t(int, temp_bpw, BITS_PER_BYTE) - 1; |
449 | cfg[i] = idx << PACKING_START_SHIFT; |
450 | cfg[i] |= msb_to_lsb << PACKING_DIR_SHIFT; |
451 | cfg[i] |= len << PACKING_LEN_SHIFT; |
452 | |
453 | if (temp_bpw <= BITS_PER_BYTE) { |
454 | idx = ((i + 1) * BITS_PER_BYTE) + idx_start; |
455 | temp_bpw = bpw; |
456 | } else { |
457 | idx = idx + idx_delta; |
458 | temp_bpw = temp_bpw - BITS_PER_BYTE; |
459 | } |
460 | } |
461 | cfg[iter - 1] |= PACKING_STOP_BIT; |
462 | cfg0 = cfg[0] | (cfg[1] << PACKING_VECTOR_SHIFT); |
463 | cfg1 = cfg[2] | (cfg[3] << PACKING_VECTOR_SHIFT); |
464 | |
465 | if (tx_cfg) { |
466 | writel_relaxed(cfg0, se->base + SE_GENI_TX_PACKING_CFG0); |
467 | writel_relaxed(cfg1, se->base + SE_GENI_TX_PACKING_CFG1); |
468 | } |
469 | if (rx_cfg) { |
470 | writel_relaxed(cfg0, se->base + SE_GENI_RX_PACKING_CFG0); |
471 | writel_relaxed(cfg1, se->base + SE_GENI_RX_PACKING_CFG1); |
472 | } |
473 | |
474 | /* |
475 | * Number of protocol words in each FIFO entry |
476 | * 0 - 4x8, four words in each entry, max word size of 8 bits |
477 | * 1 - 2x16, two words in each entry, max word size of 16 bits |
478 | * 2 - 1x32, one word in each entry, max word size of 32 bits |
479 | * 3 - undefined |
480 | */ |
481 | if (pack_words || bpw == 32) |
482 | writel_relaxed(bpw / 16, se->base + SE_GENI_BYTE_GRAN); |
483 | } |
484 | EXPORT_SYMBOL_GPL(geni_se_config_packing); |
485 | |
486 | static void geni_se_clks_off(struct geni_se *se) |
487 | { |
488 | struct geni_wrapper *wrapper = se->wrapper; |
489 | |
490 | clk_disable_unprepare(clk: se->clk); |
491 | clk_bulk_disable_unprepare(num_clks: wrapper->num_clks, clks: wrapper->clks); |
492 | } |
493 | |
494 | /** |
495 | * geni_se_resources_off() - Turn off resources associated with the serial |
496 | * engine |
497 | * @se: Pointer to the concerned serial engine. |
498 | * |
499 | * Return: 0 on success, standard Linux error codes on failure/error. |
500 | */ |
501 | int geni_se_resources_off(struct geni_se *se) |
502 | { |
503 | int ret; |
504 | |
505 | if (has_acpi_companion(dev: se->dev)) |
506 | return 0; |
507 | |
508 | ret = pinctrl_pm_select_sleep_state(dev: se->dev); |
509 | if (ret) |
510 | return ret; |
511 | |
512 | geni_se_clks_off(se); |
513 | return 0; |
514 | } |
515 | EXPORT_SYMBOL_GPL(geni_se_resources_off); |
516 | |
517 | static int geni_se_clks_on(struct geni_se *se) |
518 | { |
519 | int ret; |
520 | struct geni_wrapper *wrapper = se->wrapper; |
521 | |
522 | ret = clk_bulk_prepare_enable(num_clks: wrapper->num_clks, clks: wrapper->clks); |
523 | if (ret) |
524 | return ret; |
525 | |
526 | ret = clk_prepare_enable(clk: se->clk); |
527 | if (ret) |
528 | clk_bulk_disable_unprepare(num_clks: wrapper->num_clks, clks: wrapper->clks); |
529 | return ret; |
530 | } |
531 | |
532 | /** |
533 | * geni_se_resources_on() - Turn on resources associated with the serial |
534 | * engine |
535 | * @se: Pointer to the concerned serial engine. |
536 | * |
537 | * Return: 0 on success, standard Linux error codes on failure/error. |
538 | */ |
539 | int geni_se_resources_on(struct geni_se *se) |
540 | { |
541 | int ret; |
542 | |
543 | if (has_acpi_companion(dev: se->dev)) |
544 | return 0; |
545 | |
546 | ret = geni_se_clks_on(se); |
547 | if (ret) |
548 | return ret; |
549 | |
550 | ret = pinctrl_pm_select_default_state(dev: se->dev); |
551 | if (ret) |
552 | geni_se_clks_off(se); |
553 | |
554 | return ret; |
555 | } |
556 | EXPORT_SYMBOL_GPL(geni_se_resources_on); |
557 | |
558 | /** |
559 | * geni_se_clk_tbl_get() - Get the clock table to program DFS |
560 | * @se: Pointer to the concerned serial engine. |
561 | * @tbl: Table in which the output is returned. |
562 | * |
563 | * This function is called by the protocol drivers to determine the different |
564 | * clock frequencies supported by serial engine core clock. The protocol |
565 | * drivers use the output to determine the clock frequency index to be |
566 | * programmed into DFS. |
567 | * |
568 | * Return: number of valid performance levels in the table on success, |
569 | * standard Linux error codes on failure. |
570 | */ |
571 | int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl) |
572 | { |
573 | long freq = 0; |
574 | int i; |
575 | |
576 | if (se->clk_perf_tbl) { |
577 | *tbl = se->clk_perf_tbl; |
578 | return se->num_clk_levels; |
579 | } |
580 | |
581 | se->clk_perf_tbl = devm_kcalloc(dev: se->dev, MAX_CLK_PERF_LEVEL, |
582 | size: sizeof(*se->clk_perf_tbl), |
583 | GFP_KERNEL); |
584 | if (!se->clk_perf_tbl) |
585 | return -ENOMEM; |
586 | |
587 | for (i = 0; i < MAX_CLK_PERF_LEVEL; i++) { |
588 | freq = clk_round_rate(clk: se->clk, rate: freq + 1); |
589 | if (freq <= 0 || freq == se->clk_perf_tbl[i - 1]) |
590 | break; |
591 | se->clk_perf_tbl[i] = freq; |
592 | } |
593 | se->num_clk_levels = i; |
594 | *tbl = se->clk_perf_tbl; |
595 | return se->num_clk_levels; |
596 | } |
597 | EXPORT_SYMBOL_GPL(geni_se_clk_tbl_get); |
598 | |
599 | /** |
600 | * geni_se_clk_freq_match() - Get the matching or closest SE clock frequency |
601 | * @se: Pointer to the concerned serial engine. |
602 | * @req_freq: Requested clock frequency. |
603 | * @index: Index of the resultant frequency in the table. |
604 | * @res_freq: Resultant frequency of the source clock. |
605 | * @exact: Flag to indicate exact multiple requirement of the requested |
606 | * frequency. |
607 | * |
608 | * This function is called by the protocol drivers to determine the best match |
609 | * of the requested frequency as provided by the serial engine clock in order |
610 | * to meet the performance requirements. |
611 | * |
612 | * If we return success: |
613 | * - if @exact is true then @res_freq / <an_integer> == @req_freq |
614 | * - if @exact is false then @res_freq / <an_integer> <= @req_freq |
615 | * |
616 | * Return: 0 on success, standard Linux error codes on failure. |
617 | */ |
618 | int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq, |
619 | unsigned int *index, unsigned long *res_freq, |
620 | bool exact) |
621 | { |
622 | unsigned long *tbl; |
623 | int num_clk_levels; |
624 | int i; |
625 | unsigned long best_delta; |
626 | unsigned long new_delta; |
627 | unsigned int divider; |
628 | |
629 | num_clk_levels = geni_se_clk_tbl_get(se, &tbl); |
630 | if (num_clk_levels < 0) |
631 | return num_clk_levels; |
632 | |
633 | if (num_clk_levels == 0) |
634 | return -EINVAL; |
635 | |
636 | best_delta = ULONG_MAX; |
637 | for (i = 0; i < num_clk_levels; i++) { |
638 | divider = DIV_ROUND_UP(tbl[i], req_freq); |
639 | new_delta = req_freq - tbl[i] / divider; |
640 | if (new_delta < best_delta) { |
641 | /* We have a new best! */ |
642 | *index = i; |
643 | *res_freq = tbl[i]; |
644 | |
645 | /* If the new best is exact then we're done */ |
646 | if (new_delta == 0) |
647 | return 0; |
648 | |
649 | /* Record how close we got */ |
650 | best_delta = new_delta; |
651 | } |
652 | } |
653 | |
654 | if (exact) |
655 | return -EINVAL; |
656 | |
657 | return 0; |
658 | } |
659 | EXPORT_SYMBOL_GPL(geni_se_clk_freq_match); |
660 | |
661 | #define GENI_SE_DMA_DONE_EN BIT(0) |
662 | #define GENI_SE_DMA_EOT_EN BIT(1) |
663 | #define GENI_SE_DMA_AHB_ERR_EN BIT(2) |
664 | #define GENI_SE_DMA_EOT_BUF BIT(0) |
665 | |
666 | /** |
667 | * geni_se_tx_init_dma() - Initiate TX DMA transfer on the serial engine |
668 | * @se: Pointer to the concerned serial engine. |
669 | * @iova: Mapped DMA address. |
670 | * @len: Length of the TX buffer. |
671 | * |
672 | * This function is used to initiate DMA TX transfer. |
673 | */ |
674 | void geni_se_tx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len) |
675 | { |
676 | u32 val; |
677 | |
678 | val = GENI_SE_DMA_DONE_EN; |
679 | val |= GENI_SE_DMA_EOT_EN; |
680 | val |= GENI_SE_DMA_AHB_ERR_EN; |
681 | writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET); |
682 | writel_relaxed(lower_32_bits(iova), se->base + SE_DMA_TX_PTR_L); |
683 | writel_relaxed(upper_32_bits(iova), se->base + SE_DMA_TX_PTR_H); |
684 | writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR); |
685 | writel(val: len, addr: se->base + SE_DMA_TX_LEN); |
686 | } |
687 | EXPORT_SYMBOL_GPL(geni_se_tx_init_dma); |
688 | |
689 | /** |
690 | * geni_se_tx_dma_prep() - Prepare the serial engine for TX DMA transfer |
691 | * @se: Pointer to the concerned serial engine. |
692 | * @buf: Pointer to the TX buffer. |
693 | * @len: Length of the TX buffer. |
694 | * @iova: Pointer to store the mapped DMA address. |
695 | * |
696 | * This function is used to prepare the buffers for DMA TX. |
697 | * |
698 | * Return: 0 on success, standard Linux error codes on failure. |
699 | */ |
700 | int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len, |
701 | dma_addr_t *iova) |
702 | { |
703 | struct geni_wrapper *wrapper = se->wrapper; |
704 | |
705 | if (!wrapper) |
706 | return -EINVAL; |
707 | |
708 | *iova = dma_map_single(wrapper->dev, buf, len, DMA_TO_DEVICE); |
709 | if (dma_mapping_error(dev: wrapper->dev, dma_addr: *iova)) |
710 | return -EIO; |
711 | |
712 | geni_se_tx_init_dma(se, *iova, len); |
713 | return 0; |
714 | } |
715 | EXPORT_SYMBOL_GPL(geni_se_tx_dma_prep); |
716 | |
717 | /** |
718 | * geni_se_rx_init_dma() - Initiate RX DMA transfer on the serial engine |
719 | * @se: Pointer to the concerned serial engine. |
720 | * @iova: Mapped DMA address. |
721 | * @len: Length of the RX buffer. |
722 | * |
723 | * This function is used to initiate DMA RX transfer. |
724 | */ |
725 | void geni_se_rx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len) |
726 | { |
727 | u32 val; |
728 | |
729 | val = GENI_SE_DMA_DONE_EN; |
730 | val |= GENI_SE_DMA_EOT_EN; |
731 | val |= GENI_SE_DMA_AHB_ERR_EN; |
732 | writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET); |
733 | writel_relaxed(lower_32_bits(iova), se->base + SE_DMA_RX_PTR_L); |
734 | writel_relaxed(upper_32_bits(iova), se->base + SE_DMA_RX_PTR_H); |
735 | /* RX does not have EOT buffer type bit. So just reset RX_ATTR */ |
736 | writel_relaxed(0, se->base + SE_DMA_RX_ATTR); |
737 | writel(val: len, addr: se->base + SE_DMA_RX_LEN); |
738 | } |
739 | EXPORT_SYMBOL_GPL(geni_se_rx_init_dma); |
740 | |
741 | /** |
742 | * geni_se_rx_dma_prep() - Prepare the serial engine for RX DMA transfer |
743 | * @se: Pointer to the concerned serial engine. |
744 | * @buf: Pointer to the RX buffer. |
745 | * @len: Length of the RX buffer. |
746 | * @iova: Pointer to store the mapped DMA address. |
747 | * |
748 | * This function is used to prepare the buffers for DMA RX. |
749 | * |
750 | * Return: 0 on success, standard Linux error codes on failure. |
751 | */ |
752 | int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len, |
753 | dma_addr_t *iova) |
754 | { |
755 | struct geni_wrapper *wrapper = se->wrapper; |
756 | |
757 | if (!wrapper) |
758 | return -EINVAL; |
759 | |
760 | *iova = dma_map_single(wrapper->dev, buf, len, DMA_FROM_DEVICE); |
761 | if (dma_mapping_error(dev: wrapper->dev, dma_addr: *iova)) |
762 | return -EIO; |
763 | |
764 | geni_se_rx_init_dma(se, *iova, len); |
765 | return 0; |
766 | } |
767 | EXPORT_SYMBOL_GPL(geni_se_rx_dma_prep); |
768 | |
769 | /** |
770 | * geni_se_tx_dma_unprep() - Unprepare the serial engine after TX DMA transfer |
771 | * @se: Pointer to the concerned serial engine. |
772 | * @iova: DMA address of the TX buffer. |
773 | * @len: Length of the TX buffer. |
774 | * |
775 | * This function is used to unprepare the DMA buffers after DMA TX. |
776 | */ |
777 | void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len) |
778 | { |
779 | struct geni_wrapper *wrapper = se->wrapper; |
780 | |
781 | if (!dma_mapping_error(dev: wrapper->dev, dma_addr: iova)) |
782 | dma_unmap_single(wrapper->dev, iova, len, DMA_TO_DEVICE); |
783 | } |
784 | EXPORT_SYMBOL_GPL(geni_se_tx_dma_unprep); |
785 | |
786 | /** |
787 | * geni_se_rx_dma_unprep() - Unprepare the serial engine after RX DMA transfer |
788 | * @se: Pointer to the concerned serial engine. |
789 | * @iova: DMA address of the RX buffer. |
790 | * @len: Length of the RX buffer. |
791 | * |
792 | * This function is used to unprepare the DMA buffers after DMA RX. |
793 | */ |
794 | void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len) |
795 | { |
796 | struct geni_wrapper *wrapper = se->wrapper; |
797 | |
798 | if (!dma_mapping_error(dev: wrapper->dev, dma_addr: iova)) |
799 | dma_unmap_single(wrapper->dev, iova, len, DMA_FROM_DEVICE); |
800 | } |
801 | EXPORT_SYMBOL_GPL(geni_se_rx_dma_unprep); |
802 | |
803 | int geni_icc_get(struct geni_se *se, const char *icc_ddr) |
804 | { |
805 | int i, err; |
806 | const char *icc_names[] = {"qup-core" , "qup-config" , icc_ddr}; |
807 | |
808 | if (has_acpi_companion(dev: se->dev)) |
809 | return 0; |
810 | |
811 | for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { |
812 | if (!icc_names[i]) |
813 | continue; |
814 | |
815 | se->icc_paths[i].path = devm_of_icc_get(dev: se->dev, name: icc_names[i]); |
816 | if (IS_ERR(ptr: se->icc_paths[i].path)) |
817 | goto err; |
818 | } |
819 | |
820 | return 0; |
821 | |
822 | err: |
823 | err = PTR_ERR(ptr: se->icc_paths[i].path); |
824 | if (err != -EPROBE_DEFER) |
825 | dev_err_ratelimited(se->dev, "Failed to get ICC path '%s': %d\n" , |
826 | icc_names[i], err); |
827 | return err; |
828 | |
829 | } |
830 | EXPORT_SYMBOL_GPL(geni_icc_get); |
831 | |
832 | int geni_icc_set_bw(struct geni_se *se) |
833 | { |
834 | int i, ret; |
835 | |
836 | for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { |
837 | ret = icc_set_bw(path: se->icc_paths[i].path, |
838 | avg_bw: se->icc_paths[i].avg_bw, peak_bw: se->icc_paths[i].avg_bw); |
839 | if (ret) { |
840 | dev_err_ratelimited(se->dev, "ICC BW voting failed on path '%s': %d\n" , |
841 | icc_path_names[i], ret); |
842 | return ret; |
843 | } |
844 | } |
845 | |
846 | return 0; |
847 | } |
848 | EXPORT_SYMBOL_GPL(geni_icc_set_bw); |
849 | |
850 | void geni_icc_set_tag(struct geni_se *se, u32 tag) |
851 | { |
852 | int i; |
853 | |
854 | for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) |
855 | icc_set_tag(path: se->icc_paths[i].path, tag); |
856 | } |
857 | EXPORT_SYMBOL_GPL(geni_icc_set_tag); |
858 | |
859 | /* To do: Replace this by icc_bulk_enable once it's implemented in ICC core */ |
860 | int geni_icc_enable(struct geni_se *se) |
861 | { |
862 | int i, ret; |
863 | |
864 | for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { |
865 | ret = icc_enable(path: se->icc_paths[i].path); |
866 | if (ret) { |
867 | dev_err_ratelimited(se->dev, "ICC enable failed on path '%s': %d\n" , |
868 | icc_path_names[i], ret); |
869 | return ret; |
870 | } |
871 | } |
872 | |
873 | return 0; |
874 | } |
875 | EXPORT_SYMBOL_GPL(geni_icc_enable); |
876 | |
877 | int geni_icc_disable(struct geni_se *se) |
878 | { |
879 | int i, ret; |
880 | |
881 | for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { |
882 | ret = icc_disable(path: se->icc_paths[i].path); |
883 | if (ret) { |
884 | dev_err_ratelimited(se->dev, "ICC disable failed on path '%s': %d\n" , |
885 | icc_path_names[i], ret); |
886 | return ret; |
887 | } |
888 | } |
889 | |
890 | return 0; |
891 | } |
892 | EXPORT_SYMBOL_GPL(geni_icc_disable); |
893 | |
894 | static int geni_se_probe(struct platform_device *pdev) |
895 | { |
896 | struct device *dev = &pdev->dev; |
897 | struct geni_wrapper *wrapper; |
898 | int ret; |
899 | |
900 | wrapper = devm_kzalloc(dev, size: sizeof(*wrapper), GFP_KERNEL); |
901 | if (!wrapper) |
902 | return -ENOMEM; |
903 | |
904 | wrapper->dev = dev; |
905 | wrapper->base = devm_platform_ioremap_resource(pdev, index: 0); |
906 | if (IS_ERR(ptr: wrapper->base)) |
907 | return PTR_ERR(ptr: wrapper->base); |
908 | |
909 | if (!has_acpi_companion(dev: &pdev->dev)) { |
910 | const struct geni_se_desc *desc; |
911 | int i; |
912 | |
913 | desc = device_get_match_data(dev: &pdev->dev); |
914 | if (!desc) |
915 | return -EINVAL; |
916 | |
917 | wrapper->num_clks = min_t(unsigned int, desc->num_clks, MAX_CLKS); |
918 | |
919 | for (i = 0; i < wrapper->num_clks; ++i) |
920 | wrapper->clks[i].id = desc->clks[i]; |
921 | |
922 | ret = of_count_phandle_with_args(np: dev->of_node, list_name: "clocks" , cells_name: "#clock-cells" ); |
923 | if (ret < 0) { |
924 | dev_err(dev, "invalid clocks property at %pOF\n" , dev->of_node); |
925 | return ret; |
926 | } |
927 | |
928 | if (ret < wrapper->num_clks) { |
929 | dev_err(dev, "invalid clocks count at %pOF, expected %d entries\n" , |
930 | dev->of_node, wrapper->num_clks); |
931 | return -EINVAL; |
932 | } |
933 | |
934 | ret = devm_clk_bulk_get(dev, num_clks: wrapper->num_clks, clks: wrapper->clks); |
935 | if (ret) { |
936 | dev_err(dev, "Err getting clks %d\n" , ret); |
937 | return ret; |
938 | } |
939 | } |
940 | |
941 | dev_set_drvdata(dev, data: wrapper); |
942 | dev_dbg(dev, "GENI SE Driver probed\n" ); |
943 | return devm_of_platform_populate(dev); |
944 | } |
945 | |
946 | static const char * const qup_clks[] = { |
947 | "m-ahb" , |
948 | "s-ahb" , |
949 | }; |
950 | |
951 | static const struct geni_se_desc qup_desc = { |
952 | .clks = qup_clks, |
953 | .num_clks = ARRAY_SIZE(qup_clks), |
954 | }; |
955 | |
956 | static const char * const i2c_master_hub_clks[] = { |
957 | "s-ahb" , |
958 | }; |
959 | |
960 | static const struct geni_se_desc i2c_master_hub_desc = { |
961 | .clks = i2c_master_hub_clks, |
962 | .num_clks = ARRAY_SIZE(i2c_master_hub_clks), |
963 | }; |
964 | |
965 | static const struct of_device_id geni_se_dt_match[] = { |
966 | { .compatible = "qcom,geni-se-qup" , .data = &qup_desc }, |
967 | { .compatible = "qcom,geni-se-i2c-master-hub" , .data = &i2c_master_hub_desc }, |
968 | {} |
969 | }; |
970 | MODULE_DEVICE_TABLE(of, geni_se_dt_match); |
971 | |
972 | static struct platform_driver geni_se_driver = { |
973 | .driver = { |
974 | .name = "geni_se_qup" , |
975 | .of_match_table = geni_se_dt_match, |
976 | }, |
977 | .probe = geni_se_probe, |
978 | }; |
979 | module_platform_driver(geni_se_driver); |
980 | |
981 | MODULE_DESCRIPTION("GENI Serial Engine Driver" ); |
982 | MODULE_LICENSE("GPL v2" ); |
983 | |