1 | // SPDX-License-Identifier: GPL-2.0 |
2 | // |
3 | // Copyright (c) 2011-2015 Samsung Electronics Co., Ltd. |
4 | // http://www.samsung.com/ |
5 | // |
6 | // Exynos3250 - CPU PMU (Power Management Unit) support |
7 | |
8 | #include <linux/soc/samsung/exynos-regs-pmu.h> |
9 | #include <linux/soc/samsung/exynos-pmu.h> |
10 | |
11 | #include "exynos-pmu.h" |
12 | |
13 | static const struct exynos_pmu_conf exynos3250_pmu_config[] = { |
14 | /* { .offset = offset, .val = { AFTR, W-AFTR, SLEEP } */ |
15 | { EXYNOS3_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, |
16 | { EXYNOS3_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, |
17 | { EXYNOS3_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, |
18 | { EXYNOS3_ARM_CORE1_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, |
19 | { EXYNOS3_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, |
20 | { EXYNOS3_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, |
21 | { EXYNOS3_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, |
22 | { EXYNOS3_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, |
23 | { EXYNOS3_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, |
24 | { EXYNOS3_ARM_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, |
25 | { EXYNOS3_ARM_L2_SYS_PWR_REG, { 0x0, 0x0, 0x3} }, |
26 | { EXYNOS3_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, |
27 | { EXYNOS3_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, |
28 | { EXYNOS3_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, |
29 | { EXYNOS3_DRAM_FREQ_DOWN_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, |
30 | { EXYNOS3_DDRPHY_DLLOFF_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, |
31 | { EXYNOS3_LPDDR_PHY_DLL_LOCK_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, |
32 | { EXYNOS3_CMU_ACLKSTOP_COREBLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, |
33 | { EXYNOS3_CMU_SCLKSTOP_COREBLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, |
34 | { EXYNOS3_CMU_RESET_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, |
35 | { EXYNOS3_APLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, |
36 | { EXYNOS3_MPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, |
37 | { EXYNOS3_BPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, |
38 | { EXYNOS3_VPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, |
39 | { EXYNOS3_EPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, |
40 | { EXYNOS3_UPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, |
41 | { EXYNOS3_EPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, |
42 | { EXYNOS3_MPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, |
43 | { EXYNOS3_BPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, |
44 | { EXYNOS3_CMU_CLKSTOP_CAM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, |
45 | { EXYNOS3_CMU_CLKSTOP_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, |
46 | { EXYNOS3_CMU_CLKSTOP_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, |
47 | { EXYNOS3_CMU_CLKSTOP_LCD0_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, |
48 | { EXYNOS3_CMU_CLKSTOP_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, |
49 | { EXYNOS3_CMU_CLKSTOP_MAUDIO_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, |
50 | { EXYNOS3_CMU_RESET_CAM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, |
51 | { EXYNOS3_CMU_RESET_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, |
52 | { EXYNOS3_CMU_RESET_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, |
53 | { EXYNOS3_CMU_RESET_LCD0_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, |
54 | { EXYNOS3_CMU_RESET_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, |
55 | { EXYNOS3_CMU_RESET_MAUDIO_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, |
56 | { EXYNOS3_TOP_BUS_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, |
57 | { EXYNOS3_TOP_RETENTION_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, |
58 | { EXYNOS3_TOP_PWR_SYS_PWR_REG, { 0x3, 0x3, 0x3} }, |
59 | { EXYNOS3_TOP_BUS_COREBLK_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, |
60 | { EXYNOS3_TOP_RETENTION_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, |
61 | { EXYNOS3_TOP_PWR_COREBLK_SYS_PWR_REG, { 0x3, 0x3, 0x3} }, |
62 | { EXYNOS3_LOGIC_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, |
63 | { EXYNOS3_OSCCLK_GATE_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, |
64 | { EXYNOS3_LOGIC_RESET_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, |
65 | { EXYNOS3_OSCCLK_GATE_COREBLK_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, |
66 | { EXYNOS3_PAD_RETENTION_DRAM_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, |
67 | { EXYNOS3_PAD_RETENTION_MAUDIO_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, |
68 | { EXYNOS3_PAD_RETENTION_GPIO_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, |
69 | { EXYNOS3_PAD_RETENTION_UART_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, |
70 | { EXYNOS3_PAD_RETENTION_MMC0_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, |
71 | { EXYNOS3_PAD_RETENTION_MMC1_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, |
72 | { EXYNOS3_PAD_RETENTION_MMC2_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, |
73 | { EXYNOS3_PAD_RETENTION_SPI_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, |
74 | { EXYNOS3_PAD_RETENTION_EBIA_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, |
75 | { EXYNOS3_PAD_RETENTION_EBIB_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, |
76 | { EXYNOS3_PAD_RETENTION_JTAG_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, |
77 | { EXYNOS3_PAD_ISOLATION_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, |
78 | { EXYNOS3_PAD_ALV_SEL_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, |
79 | { EXYNOS3_XUSBXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, |
80 | { EXYNOS3_XXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, |
81 | { EXYNOS3_EXT_REGULATOR_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, |
82 | { EXYNOS3_EXT_REGULATOR_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, |
83 | { EXYNOS3_GPIO_MODE_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, |
84 | { EXYNOS3_GPIO_MODE_MAUDIO_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, |
85 | { EXYNOS3_TOP_ASB_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, |
86 | { EXYNOS3_TOP_ASB_ISOLATION_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, |
87 | { EXYNOS3_TOP_ASB_RESET_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, |
88 | { EXYNOS3_TOP_ASB_ISOLATION_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, |
89 | { EXYNOS3_CAM_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, |
90 | { EXYNOS3_MFC_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, |
91 | { EXYNOS3_G3D_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, |
92 | { EXYNOS3_LCD0_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, |
93 | { EXYNOS3_ISP_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, |
94 | { EXYNOS3_MAUDIO_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, |
95 | { EXYNOS3_CMU_SYSCLK_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, |
96 | { PMU_TABLE_END,}, |
97 | }; |
98 | |
99 | static unsigned int const exynos3250_list_feed[] = { |
100 | EXYNOS3_ARM_CORE_OPTION(0), |
101 | EXYNOS3_ARM_CORE_OPTION(1), |
102 | EXYNOS3_ARM_CORE_OPTION(2), |
103 | EXYNOS3_ARM_CORE_OPTION(3), |
104 | EXYNOS3_ARM_COMMON_OPTION, |
105 | EXYNOS3_TOP_PWR_OPTION, |
106 | EXYNOS3_CORE_TOP_PWR_OPTION, |
107 | S5P_CAM_OPTION, |
108 | S5P_MFC_OPTION, |
109 | S5P_G3D_OPTION, |
110 | S5P_LCD0_OPTION, |
111 | S5P_ISP_OPTION, |
112 | }; |
113 | |
114 | static void (enum sys_powerdown mode) |
115 | { |
116 | unsigned int i; |
117 | unsigned int tmp; |
118 | |
119 | /* Enable only SC_FEEDBACK */ |
120 | for (i = 0; i < ARRAY_SIZE(exynos3250_list_feed); i++) { |
121 | tmp = pmu_raw_readl(offset: exynos3250_list_feed[i]); |
122 | tmp &= ~(EXYNOS3_OPTION_USE_SC_COUNTER); |
123 | tmp |= EXYNOS3_OPTION_USE_SC_FEEDBACK; |
124 | pmu_raw_writel(val: tmp, offset: exynos3250_list_feed[i]); |
125 | } |
126 | |
127 | if (mode != SYS_SLEEP) |
128 | return; |
129 | |
130 | pmu_raw_writel(XUSBXTI_DURATION, EXYNOS3_XUSBXTI_DURATION); |
131 | pmu_raw_writel(XXTI_DURATION, EXYNOS3_XXTI_DURATION); |
132 | pmu_raw_writel(EXT_REGULATOR_DURATION, EXYNOS3_EXT_REGULATOR_DURATION); |
133 | pmu_raw_writel(EXT_REGULATOR_COREBLK_DURATION, |
134 | EXYNOS3_EXT_REGULATOR_COREBLK_DURATION); |
135 | } |
136 | |
137 | static void exynos3250_pmu_init(void) |
138 | { |
139 | unsigned int value; |
140 | |
141 | /* |
142 | * To prevent from issuing new bus request form L2 memory system |
143 | * If core status is power down, should be set '1' to L2 power down |
144 | */ |
145 | value = pmu_raw_readl(EXYNOS3_ARM_COMMON_OPTION); |
146 | value |= EXYNOS3_OPTION_SKIP_DEACTIVATE_ACEACP_IN_PWDN; |
147 | pmu_raw_writel(val: value, EXYNOS3_ARM_COMMON_OPTION); |
148 | |
149 | /* Enable USE_STANDBY_WFI for all CORE */ |
150 | pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION); |
151 | |
152 | /* |
153 | * Set PSHOLD port for output high |
154 | */ |
155 | value = pmu_raw_readl(S5P_PS_HOLD_CONTROL); |
156 | value |= S5P_PS_HOLD_OUTPUT_HIGH; |
157 | pmu_raw_writel(val: value, S5P_PS_HOLD_CONTROL); |
158 | |
159 | /* |
160 | * Enable signal for PSHOLD port |
161 | */ |
162 | value = pmu_raw_readl(S5P_PS_HOLD_CONTROL); |
163 | value |= S5P_PS_HOLD_EN; |
164 | pmu_raw_writel(val: value, S5P_PS_HOLD_CONTROL); |
165 | } |
166 | |
167 | const struct exynos_pmu_data exynos3250_pmu_data = { |
168 | .pmu_config = exynos3250_pmu_config, |
169 | .pmu_init = exynos3250_pmu_init, |
170 | .powerdown_conf_extra = exynos3250_powerdown_conf_extra, |
171 | }; |
172 | |