| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * dz.h: Serial port driver for DECstations equipped |
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| 4 | * with the DZ chipset. |
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| 5 | * |
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| 6 | * Copyright (C) 1998 Olivier A. D. Lebaillif |
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| 7 | * |
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| 8 | * Email: olivier.lebaillif@ifrsys.com |
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| 9 | * |
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| 10 | * Copyright (C) 2004, 2006 Maciej W. Rozycki |
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| 11 | */ |
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| 12 | #ifndef DZ_SERIAL_H |
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| 13 | #define DZ_SERIAL_H |
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| 14 | |
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| 15 | /* |
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| 16 | * Definitions for the Control and Status Register. |
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| 17 | */ |
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| 18 | #define DZ_TRDY 0x8000 /* Transmitter empty */ |
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| 19 | #define DZ_TIE 0x4000 /* Transmitter Interrupt Enbl */ |
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| 20 | #define DZ_TLINE 0x0300 /* Transmitter Line Number */ |
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| 21 | #define DZ_RDONE 0x0080 /* Receiver data ready */ |
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| 22 | #define DZ_RIE 0x0040 /* Receive Interrupt Enable */ |
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| 23 | #define DZ_MSE 0x0020 /* Master Scan Enable */ |
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| 24 | #define DZ_CLR 0x0010 /* Master reset */ |
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| 25 | #define DZ_MAINT 0x0008 /* Loop Back Mode */ |
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| 26 | |
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| 27 | /* |
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| 28 | * Definitions for the Receiver Buffer Register. |
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| 29 | */ |
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| 30 | #define DZ_RBUF_MASK 0x00FF /* Data Mask */ |
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| 31 | #define DZ_LINE_MASK 0x0300 /* Line Mask */ |
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| 32 | #define DZ_DVAL 0x8000 /* Valid Data indicator */ |
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| 33 | #define DZ_OERR 0x4000 /* Overrun error indicator */ |
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| 34 | #define DZ_FERR 0x2000 /* Frame error indicator */ |
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| 35 | #define DZ_PERR 0x1000 /* Parity error indicator */ |
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| 36 | |
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| 37 | #define DZ_BREAK 0x0800 /* BREAK event software flag */ |
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| 38 | |
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| 39 | #define LINE(x) ((x & DZ_LINE_MASK) >> 8) /* Get the line number |
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| 40 | from the input buffer */ |
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| 41 | #define UCHAR(x) ((unsigned char)(x & DZ_RBUF_MASK)) |
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| 42 | |
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| 43 | /* |
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| 44 | * Definitions for the Transmit Control Register. |
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| 45 | */ |
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| 46 | #define DZ_LINE_KEYBOARD 0x0001 |
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| 47 | #define DZ_LINE_MOUSE 0x0002 |
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| 48 | #define DZ_LINE_MODEM 0x0004 |
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| 49 | #define DZ_LINE_PRINTER 0x0008 |
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| 50 | |
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| 51 | #define DZ_MODEM_RTS 0x0800 /* RTS for the modem line (2) */ |
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| 52 | #define DZ_MODEM_DTR 0x0400 /* DTR for the modem line (2) */ |
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| 53 | #define DZ_PRINT_RTS 0x0200 /* RTS for the prntr line (3) */ |
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| 54 | #define DZ_PRINT_DTR 0x0100 /* DTR for the prntr line (3) */ |
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| 55 | #define DZ_LNENB 0x000f /* Transmitter Line Enable */ |
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| 56 | |
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| 57 | /* |
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| 58 | * Definitions for the Modem Status Register. |
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| 59 | */ |
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| 60 | #define DZ_MODEM_RI 0x0800 /* RI for the modem line (2) */ |
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| 61 | #define DZ_MODEM_CD 0x0400 /* CD for the modem line (2) */ |
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| 62 | #define DZ_MODEM_DSR 0x0200 /* DSR for the modem line (2) */ |
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| 63 | #define DZ_MODEM_CTS 0x0100 /* CTS for the modem line (2) */ |
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| 64 | #define DZ_PRINT_RI 0x0008 /* RI for the printer line (3) */ |
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| 65 | #define DZ_PRINT_CD 0x0004 /* CD for the printer line (3) */ |
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| 66 | #define DZ_PRINT_DSR 0x0002 /* DSR for the prntr line (3) */ |
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| 67 | #define DZ_PRINT_CTS 0x0001 /* CTS for the prntr line (3) */ |
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| 68 | |
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| 69 | /* |
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| 70 | * Definitions for the Transmit Data Register. |
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| 71 | */ |
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| 72 | #define DZ_BRK0 0x0100 /* Break assertion for line 0 */ |
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| 73 | #define DZ_BRK1 0x0200 /* Break assertion for line 1 */ |
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| 74 | #define DZ_BRK2 0x0400 /* Break assertion for line 2 */ |
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| 75 | #define DZ_BRK3 0x0800 /* Break assertion for line 3 */ |
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| 76 | |
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| 77 | /* |
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| 78 | * Definitions for the Line Parameter Register. |
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| 79 | */ |
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| 80 | #define DZ_KEYBOARD 0x0000 /* line 0 = keyboard */ |
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| 81 | #define DZ_MOUSE 0x0001 /* line 1 = mouse */ |
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| 82 | #define DZ_MODEM 0x0002 /* line 2 = modem */ |
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| 83 | #define DZ_PRINTER 0x0003 /* line 3 = printer */ |
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| 84 | |
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| 85 | #define DZ_CSIZE 0x0018 /* Number of bits per byte (mask) */ |
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| 86 | #define DZ_CS5 0x0000 /* 5 bits per byte */ |
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| 87 | #define DZ_CS6 0x0008 /* 6 bits per byte */ |
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| 88 | #define DZ_CS7 0x0010 /* 7 bits per byte */ |
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| 89 | #define DZ_CS8 0x0018 /* 8 bits per byte */ |
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| 90 | |
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| 91 | #define DZ_CSTOPB 0x0020 /* 2 stop bits instead of one */ |
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| 92 | |
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| 93 | #define DZ_PARENB 0x0040 /* Parity enable */ |
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| 94 | #define DZ_PARODD 0x0080 /* Odd parity instead of even */ |
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| 95 | |
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| 96 | #define DZ_CBAUD 0x0E00 /* Baud Rate (mask) */ |
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| 97 | #define DZ_B50 0x0000 |
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| 98 | #define DZ_B75 0x0100 |
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| 99 | #define DZ_B110 0x0200 |
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| 100 | #define DZ_B134 0x0300 |
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| 101 | #define DZ_B150 0x0400 |
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| 102 | #define DZ_B300 0x0500 |
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| 103 | #define DZ_B600 0x0600 |
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| 104 | #define DZ_B1200 0x0700 |
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| 105 | #define DZ_B1800 0x0800 |
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| 106 | #define DZ_B2000 0x0900 |
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| 107 | #define DZ_B2400 0x0A00 |
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| 108 | #define DZ_B3600 0x0B00 |
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| 109 | #define DZ_B4800 0x0C00 |
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| 110 | #define DZ_B7200 0x0D00 |
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| 111 | #define DZ_B9600 0x0E00 |
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| 112 | |
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| 113 | #define DZ_RXENAB 0x1000 /* Receiver Enable */ |
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| 114 | |
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| 115 | /* |
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| 116 | * Addresses for the DZ registers |
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| 117 | */ |
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| 118 | #define DZ_CSR 0x00 /* Control and Status Register */ |
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| 119 | #define DZ_RBUF 0x08 /* Receive Buffer */ |
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| 120 | #define DZ_LPR 0x08 /* Line Parameters Register */ |
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| 121 | #define DZ_TCR 0x10 /* Transmitter Control Register */ |
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| 122 | #define DZ_MSR 0x18 /* Modem Status Register */ |
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| 123 | #define DZ_TDR 0x18 /* Transmit Data Register */ |
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| 124 | |
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| 125 | #define DZ_NB_PORT 4 |
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| 126 | |
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| 127 | #define DZ_XMIT_SIZE 4096 /* buffer size */ |
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| 128 | #define DZ_WAKEUP_CHARS DZ_XMIT_SIZE/4 |
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| 129 | |
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| 130 | #endif /* DZ_SERIAL_H */ |
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| 131 | |
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