1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* |
3 | * Driver for Motorola/Freescale IMX serial ports |
4 | * |
5 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. |
6 | * |
7 | * Author: Sascha Hauer <sascha@saschahauer.de> |
8 | * Copyright (C) 2004 Pengutronix |
9 | */ |
10 | |
11 | #include <linux/module.h> |
12 | #include <linux/ioport.h> |
13 | #include <linux/init.h> |
14 | #include <linux/console.h> |
15 | #include <linux/sysrq.h> |
16 | #include <linux/platform_device.h> |
17 | #include <linux/tty.h> |
18 | #include <linux/tty_flip.h> |
19 | #include <linux/serial_core.h> |
20 | #include <linux/serial.h> |
21 | #include <linux/clk.h> |
22 | #include <linux/delay.h> |
23 | #include <linux/ktime.h> |
24 | #include <linux/pinctrl/consumer.h> |
25 | #include <linux/rational.h> |
26 | #include <linux/slab.h> |
27 | #include <linux/of.h> |
28 | #include <linux/io.h> |
29 | #include <linux/dma-mapping.h> |
30 | |
31 | #include <asm/irq.h> |
32 | #include <linux/dma/imx-dma.h> |
33 | |
34 | #include "serial_mctrl_gpio.h" |
35 | |
36 | /* Register definitions */ |
37 | #define URXD0 0x0 /* Receiver Register */ |
38 | #define URTX0 0x40 /* Transmitter Register */ |
39 | #define UCR1 0x80 /* Control Register 1 */ |
40 | #define UCR2 0x84 /* Control Register 2 */ |
41 | #define UCR3 0x88 /* Control Register 3 */ |
42 | #define UCR4 0x8c /* Control Register 4 */ |
43 | #define UFCR 0x90 /* FIFO Control Register */ |
44 | #define USR1 0x94 /* Status Register 1 */ |
45 | #define USR2 0x98 /* Status Register 2 */ |
46 | #define UESC 0x9c /* Escape Character Register */ |
47 | #define UTIM 0xa0 /* Escape Timer Register */ |
48 | #define UBIR 0xa4 /* BRM Incremental Register */ |
49 | #define UBMR 0xa8 /* BRM Modulator Register */ |
50 | #define UBRC 0xac /* Baud Rate Count Register */ |
51 | #define IMX21_ONEMS 0xb0 /* One Millisecond register */ |
52 | #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ |
53 | #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ |
54 | |
55 | /* UART Control Register Bit Fields.*/ |
56 | #define URXD_DUMMY_READ (1<<16) |
57 | #define URXD_CHARRDY (1<<15) |
58 | #define URXD_ERR (1<<14) |
59 | #define URXD_OVRRUN (1<<13) |
60 | #define URXD_FRMERR (1<<12) |
61 | #define URXD_BRK (1<<11) |
62 | #define URXD_PRERR (1<<10) |
63 | #define URXD_RX_DATA (0xFF<<0) |
64 | #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ |
65 | #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ |
66 | #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ |
67 | #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ |
68 | #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ |
69 | #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ |
70 | #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */ |
71 | #define UCR1_IREN (1<<7) /* Infrared interface enable */ |
72 | #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ |
73 | #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ |
74 | #define UCR1_SNDBRK (1<<4) /* Send break */ |
75 | #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */ |
76 | #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ |
77 | #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ |
78 | #define UCR1_DOZE (1<<1) /* Doze */ |
79 | #define UCR1_UARTEN (1<<0) /* UART enabled */ |
80 | #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ |
81 | #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ |
82 | #define UCR2_CTSC (1<<13) /* CTS pin control */ |
83 | #define UCR2_CTS (1<<12) /* Clear to send */ |
84 | #define UCR2_ESCEN (1<<11) /* Escape enable */ |
85 | #define UCR2_PREN (1<<8) /* Parity enable */ |
86 | #define UCR2_PROE (1<<7) /* Parity odd/even */ |
87 | #define UCR2_STPB (1<<6) /* Stop */ |
88 | #define UCR2_WS (1<<5) /* Word size */ |
89 | #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ |
90 | #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ |
91 | #define UCR2_TXEN (1<<2) /* Transmitter enabled */ |
92 | #define UCR2_RXEN (1<<1) /* Receiver enabled */ |
93 | #define UCR2_SRST (1<<0) /* SW reset */ |
94 | #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ |
95 | #define UCR3_PARERREN (1<<12) /* Parity enable */ |
96 | #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ |
97 | #define UCR3_DSR (1<<10) /* Data set ready */ |
98 | #define UCR3_DCD (1<<9) /* Data carrier detect */ |
99 | #define UCR3_RI (1<<8) /* Ring indicator */ |
100 | #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ |
101 | #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ |
102 | #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ |
103 | #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ |
104 | #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */ |
105 | #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ |
106 | #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ |
107 | #define UCR3_BPEN (1<<0) /* Preset registers enable */ |
108 | #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ |
109 | #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ |
110 | #define UCR4_INVR (1<<9) /* Inverted infrared reception */ |
111 | #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ |
112 | #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ |
113 | #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ |
114 | #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ |
115 | #define UCR4_IRSC (1<<5) /* IR special case */ |
116 | #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ |
117 | #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ |
118 | #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ |
119 | #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ |
120 | #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ |
121 | #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ |
122 | #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ |
123 | #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) |
124 | #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ |
125 | #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ |
126 | #define USR1_RTSS (1<<14) /* RTS pin status */ |
127 | #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ |
128 | #define USR1_RTSD (1<<12) /* RTS delta */ |
129 | #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ |
130 | #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ |
131 | #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ |
132 | #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */ |
133 | #define USR1_DTRD (1<<7) /* DTR Delta */ |
134 | #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ |
135 | #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ |
136 | #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ |
137 | #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ |
138 | #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ |
139 | #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ |
140 | #define USR2_IDLE (1<<12) /* Idle condition */ |
141 | #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */ |
142 | #define USR2_RIIN (1<<9) /* Ring Indicator Input */ |
143 | #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ |
144 | #define USR2_WAKE (1<<7) /* Wake */ |
145 | #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */ |
146 | #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ |
147 | #define USR2_TXDC (1<<3) /* Transmitter complete */ |
148 | #define USR2_BRCD (1<<2) /* Break condition */ |
149 | #define USR2_ORE (1<<1) /* Overrun error */ |
150 | #define USR2_RDR (1<<0) /* Recv data ready */ |
151 | #define UTS_FRCPERR (1<<13) /* Force parity error */ |
152 | #define UTS_LOOP (1<<12) /* Loop tx and rx */ |
153 | #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ |
154 | #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ |
155 | #define UTS_TXFULL (1<<4) /* TxFIFO full */ |
156 | #define UTS_RXFULL (1<<3) /* RxFIFO full */ |
157 | #define UTS_SOFTRST (1<<0) /* Software reset */ |
158 | |
159 | /* We've been assigned a range on the "Low-density serial ports" major */ |
160 | #define SERIAL_IMX_MAJOR 207 |
161 | #define MINOR_START 16 |
162 | #define DEV_NAME "ttymxc" |
163 | |
164 | /* |
165 | * This determines how often we check the modem status signals |
166 | * for any change. They generally aren't connected to an IRQ |
167 | * so we have to poll them. We also check immediately before |
168 | * filling the TX fifo incase CTS has been dropped. |
169 | */ |
170 | #define MCTRL_TIMEOUT (250*HZ/1000) |
171 | |
172 | #define DRIVER_NAME "IMX-uart" |
173 | |
174 | #define UART_NR 8 |
175 | |
176 | /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */ |
177 | enum imx_uart_type { |
178 | IMX1_UART, |
179 | IMX21_UART, |
180 | }; |
181 | |
182 | /* device type dependent stuff */ |
183 | struct imx_uart_data { |
184 | unsigned uts_reg; |
185 | enum imx_uart_type devtype; |
186 | }; |
187 | |
188 | enum imx_tx_state { |
189 | OFF, |
190 | WAIT_AFTER_RTS, |
191 | SEND, |
192 | WAIT_AFTER_SEND, |
193 | }; |
194 | |
195 | struct imx_port { |
196 | struct uart_port port; |
197 | struct timer_list timer; |
198 | unsigned int old_status; |
199 | unsigned int have_rtscts:1; |
200 | unsigned int have_rtsgpio:1; |
201 | unsigned int dte_mode:1; |
202 | unsigned int inverted_tx:1; |
203 | unsigned int inverted_rx:1; |
204 | struct clk *clk_ipg; |
205 | struct clk *clk_per; |
206 | const struct imx_uart_data *devdata; |
207 | |
208 | struct mctrl_gpios *gpios; |
209 | |
210 | /* counter to stop 0xff flood */ |
211 | int idle_counter; |
212 | |
213 | /* DMA fields */ |
214 | unsigned int dma_is_enabled:1; |
215 | unsigned int dma_is_rxing:1; |
216 | unsigned int dma_is_txing:1; |
217 | struct dma_chan *dma_chan_rx, *dma_chan_tx; |
218 | struct scatterlist rx_sgl, tx_sgl[2]; |
219 | void *rx_buf; |
220 | struct circ_buf rx_ring; |
221 | unsigned int rx_buf_size; |
222 | unsigned int rx_period_length; |
223 | unsigned int rx_periods; |
224 | dma_cookie_t rx_cookie; |
225 | unsigned int tx_bytes; |
226 | unsigned int dma_tx_nents; |
227 | unsigned int saved_reg[10]; |
228 | bool context_saved; |
229 | |
230 | enum imx_tx_state tx_state; |
231 | struct hrtimer trigger_start_tx; |
232 | struct hrtimer trigger_stop_tx; |
233 | }; |
234 | |
235 | struct imx_port_ucrs { |
236 | unsigned int ucr1; |
237 | unsigned int ucr2; |
238 | unsigned int ucr3; |
239 | }; |
240 | |
241 | static const struct imx_uart_data imx_uart_imx1_devdata = { |
242 | .uts_reg = IMX1_UTS, |
243 | .devtype = IMX1_UART, |
244 | }; |
245 | |
246 | static const struct imx_uart_data imx_uart_imx21_devdata = { |
247 | .uts_reg = IMX21_UTS, |
248 | .devtype = IMX21_UART, |
249 | }; |
250 | |
251 | static const struct of_device_id imx_uart_dt_ids[] = { |
252 | /* |
253 | * For reasons unknown to me, some UART devices (e.g. imx6ul's) are |
254 | * compatible to fsl,imx6q-uart, but not fsl,imx21-uart, while the |
255 | * original imx6q's UART is compatible to fsl,imx21-uart. This driver |
256 | * doesn't make any distinction between these two variants. |
257 | */ |
258 | { .compatible = "fsl,imx6q-uart" , .data = &imx_uart_imx21_devdata, }, |
259 | { .compatible = "fsl,imx1-uart" , .data = &imx_uart_imx1_devdata, }, |
260 | { .compatible = "fsl,imx21-uart" , .data = &imx_uart_imx21_devdata, }, |
261 | { /* sentinel */ } |
262 | }; |
263 | MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); |
264 | |
265 | static inline void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset) |
266 | { |
267 | writel(val, addr: sport->port.membase + offset); |
268 | } |
269 | |
270 | static inline u32 imx_uart_readl(struct imx_port *sport, u32 offset) |
271 | { |
272 | return readl(addr: sport->port.membase + offset); |
273 | } |
274 | |
275 | static inline unsigned imx_uart_uts_reg(struct imx_port *sport) |
276 | { |
277 | return sport->devdata->uts_reg; |
278 | } |
279 | |
280 | static inline int imx_uart_is_imx1(struct imx_port *sport) |
281 | { |
282 | return sport->devdata->devtype == IMX1_UART; |
283 | } |
284 | |
285 | /* |
286 | * Save and restore functions for UCR1, UCR2 and UCR3 registers |
287 | */ |
288 | #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE) |
289 | static void imx_uart_ucrs_save(struct imx_port *sport, |
290 | struct imx_port_ucrs *ucr) |
291 | { |
292 | /* save control registers */ |
293 | ucr->ucr1 = imx_uart_readl(sport, UCR1); |
294 | ucr->ucr2 = imx_uart_readl(sport, UCR2); |
295 | ucr->ucr3 = imx_uart_readl(sport, UCR3); |
296 | } |
297 | |
298 | static void imx_uart_ucrs_restore(struct imx_port *sport, |
299 | struct imx_port_ucrs *ucr) |
300 | { |
301 | /* restore control registers */ |
302 | imx_uart_writel(sport, val: ucr->ucr1, UCR1); |
303 | imx_uart_writel(sport, val: ucr->ucr2, UCR2); |
304 | imx_uart_writel(sport, val: ucr->ucr3, UCR3); |
305 | } |
306 | #endif |
307 | |
308 | /* called with port.lock taken and irqs caller dependent */ |
309 | static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2) |
310 | { |
311 | *ucr2 &= ~(UCR2_CTSC | UCR2_CTS); |
312 | |
313 | mctrl_gpio_set(gpios: sport->gpios, mctrl: sport->port.mctrl | TIOCM_RTS); |
314 | } |
315 | |
316 | /* called with port.lock taken and irqs caller dependent */ |
317 | static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2) |
318 | { |
319 | *ucr2 &= ~UCR2_CTSC; |
320 | *ucr2 |= UCR2_CTS; |
321 | |
322 | mctrl_gpio_set(gpios: sport->gpios, mctrl: sport->port.mctrl & ~TIOCM_RTS); |
323 | } |
324 | |
325 | static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec) |
326 | { |
327 | hrtimer_start(timer: hrt, tim: ms_to_ktime(ms: msec), mode: HRTIMER_MODE_REL); |
328 | } |
329 | |
330 | /* called with port.lock taken and irqs off */ |
331 | static void imx_uart_soft_reset(struct imx_port *sport) |
332 | { |
333 | int i = 10; |
334 | u32 ucr2, ubir, ubmr, uts; |
335 | |
336 | /* |
337 | * According to the Reference Manual description of the UART SRST bit: |
338 | * |
339 | * "Reset the transmit and receive state machines, |
340 | * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD |
341 | * and UTS[6-3]". |
342 | * |
343 | * We don't need to restore the old values from USR1, USR2, URXD and |
344 | * UTXD. UBRC is read only, so only save/restore the other three |
345 | * registers. |
346 | */ |
347 | ubir = imx_uart_readl(sport, UBIR); |
348 | ubmr = imx_uart_readl(sport, UBMR); |
349 | uts = imx_uart_readl(sport, IMX21_UTS); |
350 | |
351 | ucr2 = imx_uart_readl(sport, UCR2); |
352 | imx_uart_writel(sport, val: ucr2 & ~UCR2_SRST, UCR2); |
353 | |
354 | while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) |
355 | udelay(1); |
356 | |
357 | /* Restore the registers */ |
358 | imx_uart_writel(sport, val: ubir, UBIR); |
359 | imx_uart_writel(sport, val: ubmr, UBMR); |
360 | imx_uart_writel(sport, val: uts, IMX21_UTS); |
361 | |
362 | sport->idle_counter = 0; |
363 | } |
364 | |
365 | static void imx_uart_disable_loopback_rs485(struct imx_port *sport) |
366 | { |
367 | unsigned int uts; |
368 | |
369 | /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */ |
370 | uts = imx_uart_readl(sport, offset: imx_uart_uts_reg(sport)); |
371 | uts &= ~UTS_LOOP; |
372 | imx_uart_writel(sport, val: uts, offset: imx_uart_uts_reg(sport)); |
373 | } |
374 | |
375 | /* called with port.lock taken and irqs off */ |
376 | static void imx_uart_start_rx(struct uart_port *port) |
377 | { |
378 | struct imx_port *sport = (struct imx_port *)port; |
379 | unsigned int ucr1, ucr2; |
380 | |
381 | ucr1 = imx_uart_readl(sport, UCR1); |
382 | ucr2 = imx_uart_readl(sport, UCR2); |
383 | |
384 | ucr2 |= UCR2_RXEN; |
385 | |
386 | if (sport->dma_is_enabled) { |
387 | ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN; |
388 | } else { |
389 | ucr1 |= UCR1_RRDYEN; |
390 | ucr2 |= UCR2_ATEN; |
391 | } |
392 | |
393 | /* Write UCR2 first as it includes RXEN */ |
394 | imx_uart_writel(sport, val: ucr2, UCR2); |
395 | imx_uart_writel(sport, val: ucr1, UCR1); |
396 | imx_uart_disable_loopback_rs485(sport); |
397 | } |
398 | |
399 | /* called with port.lock taken and irqs off */ |
400 | static void imx_uart_stop_tx(struct uart_port *port) |
401 | { |
402 | struct imx_port *sport = (struct imx_port *)port; |
403 | u32 ucr1, ucr4, usr2; |
404 | |
405 | if (sport->tx_state == OFF) |
406 | return; |
407 | |
408 | /* |
409 | * We are maybe in the SMP context, so if the DMA TX thread is running |
410 | * on other cpu, we have to wait for it to finish. |
411 | */ |
412 | if (sport->dma_is_txing) |
413 | return; |
414 | |
415 | ucr1 = imx_uart_readl(sport, UCR1); |
416 | imx_uart_writel(sport, val: ucr1 & ~UCR1_TRDYEN, UCR1); |
417 | |
418 | usr2 = imx_uart_readl(sport, USR2); |
419 | if (!(usr2 & USR2_TXDC)) { |
420 | /* The shifter is still busy, so retry once TC triggers */ |
421 | return; |
422 | } |
423 | |
424 | ucr4 = imx_uart_readl(sport, UCR4); |
425 | ucr4 &= ~UCR4_TCEN; |
426 | imx_uart_writel(sport, val: ucr4, UCR4); |
427 | |
428 | /* in rs485 mode disable transmitter */ |
429 | if (port->rs485.flags & SER_RS485_ENABLED) { |
430 | if (sport->tx_state == SEND) { |
431 | sport->tx_state = WAIT_AFTER_SEND; |
432 | |
433 | if (port->rs485.delay_rts_after_send > 0) { |
434 | start_hrtimer_ms(hrt: &sport->trigger_stop_tx, |
435 | msec: port->rs485.delay_rts_after_send); |
436 | return; |
437 | } |
438 | |
439 | /* continue without any delay */ |
440 | } |
441 | |
442 | if (sport->tx_state == WAIT_AFTER_RTS || |
443 | sport->tx_state == WAIT_AFTER_SEND) { |
444 | u32 ucr2; |
445 | |
446 | hrtimer_try_to_cancel(timer: &sport->trigger_start_tx); |
447 | |
448 | ucr2 = imx_uart_readl(sport, UCR2); |
449 | if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) |
450 | imx_uart_rts_active(sport, ucr2: &ucr2); |
451 | else |
452 | imx_uart_rts_inactive(sport, ucr2: &ucr2); |
453 | imx_uart_writel(sport, val: ucr2, UCR2); |
454 | |
455 | if (!port->rs485_rx_during_tx_gpio) |
456 | imx_uart_start_rx(port); |
457 | |
458 | sport->tx_state = OFF; |
459 | } |
460 | } else { |
461 | sport->tx_state = OFF; |
462 | } |
463 | } |
464 | |
465 | /* called with port.lock taken and irqs off */ |
466 | static void imx_uart_stop_rx(struct uart_port *port) |
467 | { |
468 | struct imx_port *sport = (struct imx_port *)port; |
469 | u32 ucr1, ucr2, ucr4, uts; |
470 | |
471 | ucr1 = imx_uart_readl(sport, UCR1); |
472 | ucr2 = imx_uart_readl(sport, UCR2); |
473 | ucr4 = imx_uart_readl(sport, UCR4); |
474 | |
475 | if (sport->dma_is_enabled) { |
476 | ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN); |
477 | } else { |
478 | ucr1 &= ~UCR1_RRDYEN; |
479 | ucr2 &= ~UCR2_ATEN; |
480 | ucr4 &= ~UCR4_OREN; |
481 | } |
482 | imx_uart_writel(sport, val: ucr1, UCR1); |
483 | imx_uart_writel(sport, val: ucr4, UCR4); |
484 | |
485 | /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */ |
486 | if (port->rs485.flags & SER_RS485_ENABLED && |
487 | port->rs485.flags & SER_RS485_RTS_ON_SEND && |
488 | sport->have_rtscts && !sport->have_rtsgpio) { |
489 | uts = imx_uart_readl(sport, offset: imx_uart_uts_reg(sport)); |
490 | uts |= UTS_LOOP; |
491 | imx_uart_writel(sport, val: uts, offset: imx_uart_uts_reg(sport)); |
492 | ucr2 |= UCR2_RXEN; |
493 | } else { |
494 | ucr2 &= ~UCR2_RXEN; |
495 | } |
496 | |
497 | imx_uart_writel(sport, val: ucr2, UCR2); |
498 | } |
499 | |
500 | /* called with port.lock taken and irqs off */ |
501 | static void imx_uart_enable_ms(struct uart_port *port) |
502 | { |
503 | struct imx_port *sport = (struct imx_port *)port; |
504 | |
505 | mod_timer(timer: &sport->timer, expires: jiffies); |
506 | |
507 | mctrl_gpio_enable_ms(gpios: sport->gpios); |
508 | } |
509 | |
510 | static void imx_uart_dma_tx(struct imx_port *sport); |
511 | |
512 | /* called with port.lock taken and irqs off */ |
513 | static inline void imx_uart_transmit_buffer(struct imx_port *sport) |
514 | { |
515 | struct circ_buf *xmit = &sport->port.state->xmit; |
516 | |
517 | if (sport->port.x_char) { |
518 | /* Send next char */ |
519 | imx_uart_writel(sport, val: sport->port.x_char, URTX0); |
520 | sport->port.icount.tx++; |
521 | sport->port.x_char = 0; |
522 | return; |
523 | } |
524 | |
525 | if (uart_circ_empty(xmit) || uart_tx_stopped(port: &sport->port)) { |
526 | imx_uart_stop_tx(port: &sport->port); |
527 | return; |
528 | } |
529 | |
530 | if (sport->dma_is_enabled) { |
531 | u32 ucr1; |
532 | /* |
533 | * We've just sent a X-char Ensure the TX DMA is enabled |
534 | * and the TX IRQ is disabled. |
535 | **/ |
536 | ucr1 = imx_uart_readl(sport, UCR1); |
537 | ucr1 &= ~UCR1_TRDYEN; |
538 | if (sport->dma_is_txing) { |
539 | ucr1 |= UCR1_TXDMAEN; |
540 | imx_uart_writel(sport, val: ucr1, UCR1); |
541 | } else { |
542 | imx_uart_writel(sport, val: ucr1, UCR1); |
543 | imx_uart_dma_tx(sport); |
544 | } |
545 | |
546 | return; |
547 | } |
548 | |
549 | while (!uart_circ_empty(xmit) && |
550 | !(imx_uart_readl(sport, offset: imx_uart_uts_reg(sport)) & UTS_TXFULL)) { |
551 | /* send xmit->buf[xmit->tail] |
552 | * out the port here */ |
553 | imx_uart_writel(sport, val: xmit->buf[xmit->tail], URTX0); |
554 | uart_xmit_advance(up: &sport->port, chars: 1); |
555 | } |
556 | |
557 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
558 | uart_write_wakeup(port: &sport->port); |
559 | |
560 | if (uart_circ_empty(xmit)) |
561 | imx_uart_stop_tx(port: &sport->port); |
562 | } |
563 | |
564 | static void imx_uart_dma_tx_callback(void *data) |
565 | { |
566 | struct imx_port *sport = data; |
567 | struct scatterlist *sgl = &sport->tx_sgl[0]; |
568 | struct circ_buf *xmit = &sport->port.state->xmit; |
569 | unsigned long flags; |
570 | u32 ucr1; |
571 | |
572 | uart_port_lock_irqsave(up: &sport->port, flags: &flags); |
573 | |
574 | dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); |
575 | |
576 | ucr1 = imx_uart_readl(sport, UCR1); |
577 | ucr1 &= ~UCR1_TXDMAEN; |
578 | imx_uart_writel(sport, val: ucr1, UCR1); |
579 | |
580 | uart_xmit_advance(up: &sport->port, chars: sport->tx_bytes); |
581 | |
582 | dev_dbg(sport->port.dev, "we finish the TX DMA.\n" ); |
583 | |
584 | sport->dma_is_txing = 0; |
585 | |
586 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
587 | uart_write_wakeup(port: &sport->port); |
588 | |
589 | if (!uart_circ_empty(xmit) && !uart_tx_stopped(port: &sport->port)) |
590 | imx_uart_dma_tx(sport); |
591 | else if (sport->port.rs485.flags & SER_RS485_ENABLED) { |
592 | u32 ucr4 = imx_uart_readl(sport, UCR4); |
593 | ucr4 |= UCR4_TCEN; |
594 | imx_uart_writel(sport, val: ucr4, UCR4); |
595 | } |
596 | |
597 | uart_port_unlock_irqrestore(up: &sport->port, flags); |
598 | } |
599 | |
600 | /* called with port.lock taken and irqs off */ |
601 | static void imx_uart_dma_tx(struct imx_port *sport) |
602 | { |
603 | struct circ_buf *xmit = &sport->port.state->xmit; |
604 | struct scatterlist *sgl = sport->tx_sgl; |
605 | struct dma_async_tx_descriptor *desc; |
606 | struct dma_chan *chan = sport->dma_chan_tx; |
607 | struct device *dev = sport->port.dev; |
608 | u32 ucr1, ucr4; |
609 | int ret; |
610 | |
611 | if (sport->dma_is_txing) |
612 | return; |
613 | |
614 | ucr4 = imx_uart_readl(sport, UCR4); |
615 | ucr4 &= ~UCR4_TCEN; |
616 | imx_uart_writel(sport, val: ucr4, UCR4); |
617 | |
618 | sport->tx_bytes = uart_circ_chars_pending(xmit); |
619 | |
620 | if (xmit->tail < xmit->head || xmit->head == 0) { |
621 | sport->dma_tx_nents = 1; |
622 | sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); |
623 | } else { |
624 | sport->dma_tx_nents = 2; |
625 | sg_init_table(sgl, 2); |
626 | sg_set_buf(sg: sgl, buf: xmit->buf + xmit->tail, |
627 | UART_XMIT_SIZE - xmit->tail); |
628 | sg_set_buf(sg: sgl + 1, buf: xmit->buf, buflen: xmit->head); |
629 | } |
630 | |
631 | ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); |
632 | if (ret == 0) { |
633 | dev_err(dev, "DMA mapping error for TX.\n" ); |
634 | return; |
635 | } |
636 | desc = dmaengine_prep_slave_sg(chan, sgl, sg_len: ret, |
637 | dir: DMA_MEM_TO_DEV, flags: DMA_PREP_INTERRUPT); |
638 | if (!desc) { |
639 | dma_unmap_sg(dev, sgl, sport->dma_tx_nents, |
640 | DMA_TO_DEVICE); |
641 | dev_err(dev, "We cannot prepare for the TX slave dma!\n" ); |
642 | return; |
643 | } |
644 | desc->callback = imx_uart_dma_tx_callback; |
645 | desc->callback_param = sport; |
646 | |
647 | dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n" , |
648 | uart_circ_chars_pending(xmit)); |
649 | |
650 | ucr1 = imx_uart_readl(sport, UCR1); |
651 | ucr1 |= UCR1_TXDMAEN; |
652 | imx_uart_writel(sport, val: ucr1, UCR1); |
653 | |
654 | /* fire it */ |
655 | sport->dma_is_txing = 1; |
656 | dmaengine_submit(desc); |
657 | dma_async_issue_pending(chan); |
658 | return; |
659 | } |
660 | |
661 | /* called with port.lock taken and irqs off */ |
662 | static void imx_uart_start_tx(struct uart_port *port) |
663 | { |
664 | struct imx_port *sport = (struct imx_port *)port; |
665 | u32 ucr1; |
666 | |
667 | if (!sport->port.x_char && uart_circ_empty(&port->state->xmit)) |
668 | return; |
669 | |
670 | /* |
671 | * We cannot simply do nothing here if sport->tx_state == SEND already |
672 | * because UCR1_TXMPTYEN might already have been cleared in |
673 | * imx_uart_stop_tx(), but tx_state is still SEND. |
674 | */ |
675 | |
676 | if (port->rs485.flags & SER_RS485_ENABLED) { |
677 | if (sport->tx_state == OFF) { |
678 | u32 ucr2 = imx_uart_readl(sport, UCR2); |
679 | if (port->rs485.flags & SER_RS485_RTS_ON_SEND) |
680 | imx_uart_rts_active(sport, ucr2: &ucr2); |
681 | else |
682 | imx_uart_rts_inactive(sport, ucr2: &ucr2); |
683 | imx_uart_writel(sport, val: ucr2, UCR2); |
684 | |
685 | if (!(port->rs485.flags & SER_RS485_RX_DURING_TX) && |
686 | !port->rs485_rx_during_tx_gpio) |
687 | imx_uart_stop_rx(port); |
688 | |
689 | sport->tx_state = WAIT_AFTER_RTS; |
690 | |
691 | if (port->rs485.delay_rts_before_send > 0) { |
692 | start_hrtimer_ms(hrt: &sport->trigger_start_tx, |
693 | msec: port->rs485.delay_rts_before_send); |
694 | return; |
695 | } |
696 | |
697 | /* continue without any delay */ |
698 | } |
699 | |
700 | if (sport->tx_state == WAIT_AFTER_SEND |
701 | || sport->tx_state == WAIT_AFTER_RTS) { |
702 | |
703 | hrtimer_try_to_cancel(timer: &sport->trigger_stop_tx); |
704 | |
705 | /* |
706 | * Enable transmitter and shifter empty irq only if DMA |
707 | * is off. In the DMA case this is done in the |
708 | * tx-callback. |
709 | */ |
710 | if (!sport->dma_is_enabled) { |
711 | u32 ucr4 = imx_uart_readl(sport, UCR4); |
712 | ucr4 |= UCR4_TCEN; |
713 | imx_uart_writel(sport, val: ucr4, UCR4); |
714 | } |
715 | |
716 | sport->tx_state = SEND; |
717 | } |
718 | } else { |
719 | sport->tx_state = SEND; |
720 | } |
721 | |
722 | if (!sport->dma_is_enabled) { |
723 | ucr1 = imx_uart_readl(sport, UCR1); |
724 | imx_uart_writel(sport, val: ucr1 | UCR1_TRDYEN, UCR1); |
725 | } |
726 | |
727 | if (sport->dma_is_enabled) { |
728 | if (sport->port.x_char) { |
729 | /* We have X-char to send, so enable TX IRQ and |
730 | * disable TX DMA to let TX interrupt to send X-char */ |
731 | ucr1 = imx_uart_readl(sport, UCR1); |
732 | ucr1 &= ~UCR1_TXDMAEN; |
733 | ucr1 |= UCR1_TRDYEN; |
734 | imx_uart_writel(sport, val: ucr1, UCR1); |
735 | return; |
736 | } |
737 | |
738 | if (!uart_circ_empty(&port->state->xmit) && |
739 | !uart_tx_stopped(port)) |
740 | imx_uart_dma_tx(sport); |
741 | return; |
742 | } |
743 | } |
744 | |
745 | static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id) |
746 | { |
747 | struct imx_port *sport = dev_id; |
748 | u32 usr1; |
749 | |
750 | imx_uart_writel(sport, USR1_RTSD, USR1); |
751 | usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS; |
752 | uart_handle_cts_change(uport: &sport->port, active: usr1); |
753 | wake_up_interruptible(&sport->port.state->port.delta_msr_wait); |
754 | |
755 | return IRQ_HANDLED; |
756 | } |
757 | |
758 | static irqreturn_t imx_uart_rtsint(int irq, void *dev_id) |
759 | { |
760 | struct imx_port *sport = dev_id; |
761 | irqreturn_t ret; |
762 | |
763 | uart_port_lock(up: &sport->port); |
764 | |
765 | ret = __imx_uart_rtsint(irq, dev_id); |
766 | |
767 | uart_port_unlock(up: &sport->port); |
768 | |
769 | return ret; |
770 | } |
771 | |
772 | static irqreturn_t imx_uart_txint(int irq, void *dev_id) |
773 | { |
774 | struct imx_port *sport = dev_id; |
775 | |
776 | uart_port_lock(up: &sport->port); |
777 | imx_uart_transmit_buffer(sport); |
778 | uart_port_unlock(up: &sport->port); |
779 | return IRQ_HANDLED; |
780 | } |
781 | |
782 | /* Check if hardware Rx flood is in progress, and issue soft reset to stop it. |
783 | * This is to be called from Rx ISRs only when some bytes were actually |
784 | * received. |
785 | * |
786 | * A way to reproduce the flood (checked on iMX6SX) is: open iMX UART at 9600 |
787 | * 8N1, and from external source send 0xf0 char at 115200 8N1. In about 90% of |
788 | * cases this starts a flood of "receiving" of 0xff characters by the iMX6 UART |
789 | * that is terminated by any activity on RxD line, or could be stopped by |
790 | * issuing soft reset to the UART (just stop/start of RX does not help). Note |
791 | * that what we do here is sending isolated start bit about 2.4 times shorter |
792 | * than it is to be on UART configured baud rate. |
793 | */ |
794 | static void imx_uart_check_flood(struct imx_port *sport, u32 usr2) |
795 | { |
796 | /* To detect hardware 0xff flood we monitor RxD line between RX |
797 | * interrupts to isolate "receiving" of char(s) with no activity |
798 | * on RxD line, that'd never happen on actual data transfers. |
799 | * |
800 | * We use USR2_WAKE bit to check for activity on RxD line, but we have a |
801 | * race here if we clear USR2_WAKE when receiving of a char is in |
802 | * progress, so we might get RX interrupt later with USR2_WAKE bit |
803 | * cleared. Note though that as we don't try to clear USR2_WAKE when we |
804 | * detected no activity, this race may hide actual activity only once. |
805 | * |
806 | * Yet another case where receive interrupt may occur without RxD |
807 | * activity is expiration of aging timer, so we consider this as well. |
808 | * |
809 | * We use 'idle_counter' to ensure that we got at least so many RX |
810 | * interrupts without any detected activity on RxD line. 2 cases |
811 | * described plus 1 to be on the safe side gives us a margin of 3, |
812 | * below. In practice I was not able to produce a false positive to |
813 | * induce soft reset at regular data transfers even using 1 as the |
814 | * margin, so 3 is actually very strong. |
815 | * |
816 | * We count interrupts, not chars in 'idle-counter' for simplicity. |
817 | */ |
818 | |
819 | if (usr2 & USR2_WAKE) { |
820 | imx_uart_writel(sport, USR2_WAKE, USR2); |
821 | sport->idle_counter = 0; |
822 | } else if (++sport->idle_counter > 3) { |
823 | dev_warn(sport->port.dev, "RX flood detected: soft reset." ); |
824 | imx_uart_soft_reset(sport); /* also clears 'sport->idle_counter' */ |
825 | } |
826 | } |
827 | |
828 | static irqreturn_t __imx_uart_rxint(int irq, void *dev_id) |
829 | { |
830 | struct imx_port *sport = dev_id; |
831 | struct tty_port *port = &sport->port.state->port; |
832 | u32 usr2, rx; |
833 | |
834 | /* If we received something, check for 0xff flood */ |
835 | usr2 = imx_uart_readl(sport, USR2); |
836 | if (usr2 & USR2_RDR) |
837 | imx_uart_check_flood(sport, usr2); |
838 | |
839 | while ((rx = imx_uart_readl(sport, URXD0)) & URXD_CHARRDY) { |
840 | unsigned int flg = TTY_NORMAL; |
841 | sport->port.icount.rx++; |
842 | |
843 | if (unlikely(rx & URXD_ERR)) { |
844 | if (rx & URXD_BRK) { |
845 | sport->port.icount.brk++; |
846 | if (uart_handle_break(port: &sport->port)) |
847 | continue; |
848 | } |
849 | else if (rx & URXD_PRERR) |
850 | sport->port.icount.parity++; |
851 | else if (rx & URXD_FRMERR) |
852 | sport->port.icount.frame++; |
853 | if (rx & URXD_OVRRUN) |
854 | sport->port.icount.overrun++; |
855 | |
856 | if (rx & sport->port.ignore_status_mask) |
857 | continue; |
858 | |
859 | rx &= (sport->port.read_status_mask | 0xFF); |
860 | |
861 | if (rx & URXD_BRK) |
862 | flg = TTY_BREAK; |
863 | else if (rx & URXD_PRERR) |
864 | flg = TTY_PARITY; |
865 | else if (rx & URXD_FRMERR) |
866 | flg = TTY_FRAME; |
867 | if (rx & URXD_OVRRUN) |
868 | flg = TTY_OVERRUN; |
869 | |
870 | sport->port.sysrq = 0; |
871 | } else if (uart_handle_sysrq_char(port: &sport->port, ch: (unsigned char)rx)) { |
872 | continue; |
873 | } |
874 | |
875 | if (sport->port.ignore_status_mask & URXD_DUMMY_READ) |
876 | continue; |
877 | |
878 | if (tty_insert_flip_char(port, ch: rx, flag: flg) == 0) |
879 | sport->port.icount.buf_overrun++; |
880 | } |
881 | |
882 | tty_flip_buffer_push(port); |
883 | |
884 | return IRQ_HANDLED; |
885 | } |
886 | |
887 | static irqreturn_t imx_uart_rxint(int irq, void *dev_id) |
888 | { |
889 | struct imx_port *sport = dev_id; |
890 | irqreturn_t ret; |
891 | |
892 | uart_port_lock(up: &sport->port); |
893 | |
894 | ret = __imx_uart_rxint(irq, dev_id); |
895 | |
896 | uart_port_unlock(up: &sport->port); |
897 | |
898 | return ret; |
899 | } |
900 | |
901 | static void imx_uart_clear_rx_errors(struct imx_port *sport); |
902 | |
903 | /* |
904 | * We have a modem side uart, so the meanings of RTS and CTS are inverted. |
905 | */ |
906 | static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport) |
907 | { |
908 | unsigned int tmp = TIOCM_DSR; |
909 | unsigned usr1 = imx_uart_readl(sport, USR1); |
910 | unsigned usr2 = imx_uart_readl(sport, USR2); |
911 | |
912 | if (usr1 & USR1_RTSS) |
913 | tmp |= TIOCM_CTS; |
914 | |
915 | /* in DCE mode DCDIN is always 0 */ |
916 | if (!(usr2 & USR2_DCDIN)) |
917 | tmp |= TIOCM_CAR; |
918 | |
919 | if (sport->dte_mode) |
920 | if (!(imx_uart_readl(sport, USR2) & USR2_RIIN)) |
921 | tmp |= TIOCM_RI; |
922 | |
923 | return tmp; |
924 | } |
925 | |
926 | /* |
927 | * Handle any change of modem status signal since we were last called. |
928 | */ |
929 | static void imx_uart_mctrl_check(struct imx_port *sport) |
930 | { |
931 | unsigned int status, changed; |
932 | |
933 | status = imx_uart_get_hwmctrl(sport); |
934 | changed = status ^ sport->old_status; |
935 | |
936 | if (changed == 0) |
937 | return; |
938 | |
939 | sport->old_status = status; |
940 | |
941 | if (changed & TIOCM_RI && status & TIOCM_RI) |
942 | sport->port.icount.rng++; |
943 | if (changed & TIOCM_DSR) |
944 | sport->port.icount.dsr++; |
945 | if (changed & TIOCM_CAR) |
946 | uart_handle_dcd_change(uport: &sport->port, active: status & TIOCM_CAR); |
947 | if (changed & TIOCM_CTS) |
948 | uart_handle_cts_change(uport: &sport->port, active: status & TIOCM_CTS); |
949 | |
950 | wake_up_interruptible(&sport->port.state->port.delta_msr_wait); |
951 | } |
952 | |
953 | static irqreturn_t imx_uart_int(int irq, void *dev_id) |
954 | { |
955 | struct imx_port *sport = dev_id; |
956 | unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4; |
957 | irqreturn_t ret = IRQ_NONE; |
958 | |
959 | uart_port_lock(up: &sport->port); |
960 | |
961 | usr1 = imx_uart_readl(sport, USR1); |
962 | usr2 = imx_uart_readl(sport, USR2); |
963 | ucr1 = imx_uart_readl(sport, UCR1); |
964 | ucr2 = imx_uart_readl(sport, UCR2); |
965 | ucr3 = imx_uart_readl(sport, UCR3); |
966 | ucr4 = imx_uart_readl(sport, UCR4); |
967 | |
968 | /* |
969 | * Even if a condition is true that can trigger an irq only handle it if |
970 | * the respective irq source is enabled. This prevents some undesired |
971 | * actions, for example if a character that sits in the RX FIFO and that |
972 | * should be fetched via DMA is tried to be fetched using PIO. Or the |
973 | * receiver is currently off and so reading from URXD0 results in an |
974 | * exception. So just mask the (raw) status bits for disabled irqs. |
975 | */ |
976 | if ((ucr1 & UCR1_RRDYEN) == 0) |
977 | usr1 &= ~USR1_RRDY; |
978 | if ((ucr2 & UCR2_ATEN) == 0) |
979 | usr1 &= ~USR1_AGTIM; |
980 | if ((ucr1 & UCR1_TRDYEN) == 0) |
981 | usr1 &= ~USR1_TRDY; |
982 | if ((ucr4 & UCR4_TCEN) == 0) |
983 | usr2 &= ~USR2_TXDC; |
984 | if ((ucr3 & UCR3_DTRDEN) == 0) |
985 | usr1 &= ~USR1_DTRD; |
986 | if ((ucr1 & UCR1_RTSDEN) == 0) |
987 | usr1 &= ~USR1_RTSD; |
988 | if ((ucr3 & UCR3_AWAKEN) == 0) |
989 | usr1 &= ~USR1_AWAKE; |
990 | if ((ucr4 & UCR4_OREN) == 0) |
991 | usr2 &= ~USR2_ORE; |
992 | |
993 | if (usr1 & (USR1_RRDY | USR1_AGTIM)) { |
994 | imx_uart_writel(sport, USR1_AGTIM, USR1); |
995 | |
996 | __imx_uart_rxint(irq, dev_id); |
997 | ret = IRQ_HANDLED; |
998 | } |
999 | |
1000 | if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) { |
1001 | imx_uart_transmit_buffer(sport); |
1002 | ret = IRQ_HANDLED; |
1003 | } |
1004 | |
1005 | if (usr1 & USR1_DTRD) { |
1006 | imx_uart_writel(sport, USR1_DTRD, USR1); |
1007 | |
1008 | imx_uart_mctrl_check(sport); |
1009 | |
1010 | ret = IRQ_HANDLED; |
1011 | } |
1012 | |
1013 | if (usr1 & USR1_RTSD) { |
1014 | __imx_uart_rtsint(irq, dev_id); |
1015 | ret = IRQ_HANDLED; |
1016 | } |
1017 | |
1018 | if (usr1 & USR1_AWAKE) { |
1019 | imx_uart_writel(sport, USR1_AWAKE, USR1); |
1020 | ret = IRQ_HANDLED; |
1021 | } |
1022 | |
1023 | if (usr2 & USR2_ORE) { |
1024 | sport->port.icount.overrun++; |
1025 | imx_uart_writel(sport, USR2_ORE, USR2); |
1026 | ret = IRQ_HANDLED; |
1027 | } |
1028 | |
1029 | uart_port_unlock(up: &sport->port); |
1030 | |
1031 | return ret; |
1032 | } |
1033 | |
1034 | /* |
1035 | * Return TIOCSER_TEMT when transmitter is not busy. |
1036 | */ |
1037 | static unsigned int imx_uart_tx_empty(struct uart_port *port) |
1038 | { |
1039 | struct imx_port *sport = (struct imx_port *)port; |
1040 | unsigned int ret; |
1041 | |
1042 | ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; |
1043 | |
1044 | /* If the TX DMA is working, return 0. */ |
1045 | if (sport->dma_is_txing) |
1046 | ret = 0; |
1047 | |
1048 | return ret; |
1049 | } |
1050 | |
1051 | /* called with port.lock taken and irqs off */ |
1052 | static unsigned int imx_uart_get_mctrl(struct uart_port *port) |
1053 | { |
1054 | struct imx_port *sport = (struct imx_port *)port; |
1055 | unsigned int ret = imx_uart_get_hwmctrl(sport); |
1056 | |
1057 | mctrl_gpio_get(gpios: sport->gpios, mctrl: &ret); |
1058 | |
1059 | return ret; |
1060 | } |
1061 | |
1062 | /* called with port.lock taken and irqs off */ |
1063 | static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) |
1064 | { |
1065 | struct imx_port *sport = (struct imx_port *)port; |
1066 | u32 ucr3, uts; |
1067 | |
1068 | if (!(port->rs485.flags & SER_RS485_ENABLED)) { |
1069 | u32 ucr2; |
1070 | |
1071 | /* |
1072 | * Turn off autoRTS if RTS is lowered and restore autoRTS |
1073 | * setting if RTS is raised. |
1074 | */ |
1075 | ucr2 = imx_uart_readl(sport, UCR2); |
1076 | ucr2 &= ~(UCR2_CTS | UCR2_CTSC); |
1077 | if (mctrl & TIOCM_RTS) { |
1078 | ucr2 |= UCR2_CTS; |
1079 | /* |
1080 | * UCR2_IRTS is unset if and only if the port is |
1081 | * configured for CRTSCTS, so we use inverted UCR2_IRTS |
1082 | * to get the state to restore to. |
1083 | */ |
1084 | if (!(ucr2 & UCR2_IRTS)) |
1085 | ucr2 |= UCR2_CTSC; |
1086 | } |
1087 | imx_uart_writel(sport, val: ucr2, UCR2); |
1088 | } |
1089 | |
1090 | ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR; |
1091 | if (!(mctrl & TIOCM_DTR)) |
1092 | ucr3 |= UCR3_DSR; |
1093 | imx_uart_writel(sport, val: ucr3, UCR3); |
1094 | |
1095 | uts = imx_uart_readl(sport, offset: imx_uart_uts_reg(sport)) & ~UTS_LOOP; |
1096 | if (mctrl & TIOCM_LOOP) |
1097 | uts |= UTS_LOOP; |
1098 | imx_uart_writel(sport, val: uts, offset: imx_uart_uts_reg(sport)); |
1099 | |
1100 | mctrl_gpio_set(gpios: sport->gpios, mctrl); |
1101 | } |
1102 | |
1103 | /* |
1104 | * Interrupts always disabled. |
1105 | */ |
1106 | static void imx_uart_break_ctl(struct uart_port *port, int break_state) |
1107 | { |
1108 | struct imx_port *sport = (struct imx_port *)port; |
1109 | unsigned long flags; |
1110 | u32 ucr1; |
1111 | |
1112 | uart_port_lock_irqsave(up: &sport->port, flags: &flags); |
1113 | |
1114 | ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK; |
1115 | |
1116 | if (break_state != 0) |
1117 | ucr1 |= UCR1_SNDBRK; |
1118 | |
1119 | imx_uart_writel(sport, val: ucr1, UCR1); |
1120 | |
1121 | uart_port_unlock_irqrestore(up: &sport->port, flags); |
1122 | } |
1123 | |
1124 | /* |
1125 | * This is our per-port timeout handler, for checking the |
1126 | * modem status signals. |
1127 | */ |
1128 | static void imx_uart_timeout(struct timer_list *t) |
1129 | { |
1130 | struct imx_port *sport = from_timer(sport, t, timer); |
1131 | unsigned long flags; |
1132 | |
1133 | if (sport->port.state) { |
1134 | uart_port_lock_irqsave(up: &sport->port, flags: &flags); |
1135 | imx_uart_mctrl_check(sport); |
1136 | uart_port_unlock_irqrestore(up: &sport->port, flags); |
1137 | |
1138 | mod_timer(timer: &sport->timer, expires: jiffies + MCTRL_TIMEOUT); |
1139 | } |
1140 | } |
1141 | |
1142 | /* |
1143 | * There are two kinds of RX DMA interrupts(such as in the MX6Q): |
1144 | * [1] the RX DMA buffer is full. |
1145 | * [2] the aging timer expires |
1146 | * |
1147 | * Condition [2] is triggered when a character has been sitting in the FIFO |
1148 | * for at least 8 byte durations. |
1149 | */ |
1150 | static void imx_uart_dma_rx_callback(void *data) |
1151 | { |
1152 | struct imx_port *sport = data; |
1153 | struct dma_chan *chan = sport->dma_chan_rx; |
1154 | struct scatterlist *sgl = &sport->rx_sgl; |
1155 | struct tty_port *port = &sport->port.state->port; |
1156 | struct dma_tx_state state; |
1157 | struct circ_buf *rx_ring = &sport->rx_ring; |
1158 | enum dma_status status; |
1159 | unsigned int w_bytes = 0; |
1160 | unsigned int r_bytes; |
1161 | unsigned int bd_size; |
1162 | |
1163 | status = dmaengine_tx_status(chan, cookie: sport->rx_cookie, state: &state); |
1164 | |
1165 | if (status == DMA_ERROR) { |
1166 | uart_port_lock(up: &sport->port); |
1167 | imx_uart_clear_rx_errors(sport); |
1168 | uart_port_unlock(up: &sport->port); |
1169 | return; |
1170 | } |
1171 | |
1172 | /* |
1173 | * The state-residue variable represents the empty space |
1174 | * relative to the entire buffer. Taking this in consideration |
1175 | * the head is always calculated base on the buffer total |
1176 | * length - DMA transaction residue. The UART script from the |
1177 | * SDMA firmware will jump to the next buffer descriptor, |
1178 | * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). |
1179 | * Taking this in consideration the tail is always at the |
1180 | * beginning of the buffer descriptor that contains the head. |
1181 | */ |
1182 | |
1183 | /* Calculate the head */ |
1184 | rx_ring->head = sg_dma_len(sgl) - state.residue; |
1185 | |
1186 | /* Calculate the tail. */ |
1187 | bd_size = sg_dma_len(sgl) / sport->rx_periods; |
1188 | rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; |
1189 | |
1190 | if (rx_ring->head <= sg_dma_len(sgl) && |
1191 | rx_ring->head > rx_ring->tail) { |
1192 | |
1193 | /* Move data from tail to head */ |
1194 | r_bytes = rx_ring->head - rx_ring->tail; |
1195 | |
1196 | /* If we received something, check for 0xff flood */ |
1197 | uart_port_lock(up: &sport->port); |
1198 | imx_uart_check_flood(sport, usr2: imx_uart_readl(sport, USR2)); |
1199 | uart_port_unlock(up: &sport->port); |
1200 | |
1201 | if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { |
1202 | |
1203 | /* CPU claims ownership of RX DMA buffer */ |
1204 | dma_sync_sg_for_cpu(dev: sport->port.dev, sg: sgl, nelems: 1, |
1205 | dir: DMA_FROM_DEVICE); |
1206 | |
1207 | w_bytes = tty_insert_flip_string(port, |
1208 | chars: sport->rx_buf + rx_ring->tail, size: r_bytes); |
1209 | |
1210 | /* UART retrieves ownership of RX DMA buffer */ |
1211 | dma_sync_sg_for_device(dev: sport->port.dev, sg: sgl, nelems: 1, |
1212 | dir: DMA_FROM_DEVICE); |
1213 | |
1214 | if (w_bytes != r_bytes) |
1215 | sport->port.icount.buf_overrun++; |
1216 | |
1217 | sport->port.icount.rx += w_bytes; |
1218 | } |
1219 | } else { |
1220 | WARN_ON(rx_ring->head > sg_dma_len(sgl)); |
1221 | WARN_ON(rx_ring->head <= rx_ring->tail); |
1222 | } |
1223 | |
1224 | if (w_bytes) { |
1225 | tty_flip_buffer_push(port); |
1226 | dev_dbg(sport->port.dev, "We get %d bytes.\n" , w_bytes); |
1227 | } |
1228 | } |
1229 | |
1230 | static int imx_uart_start_rx_dma(struct imx_port *sport) |
1231 | { |
1232 | struct scatterlist *sgl = &sport->rx_sgl; |
1233 | struct dma_chan *chan = sport->dma_chan_rx; |
1234 | struct device *dev = sport->port.dev; |
1235 | struct dma_async_tx_descriptor *desc; |
1236 | int ret; |
1237 | |
1238 | sport->rx_ring.head = 0; |
1239 | sport->rx_ring.tail = 0; |
1240 | |
1241 | sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size); |
1242 | ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); |
1243 | if (ret == 0) { |
1244 | dev_err(dev, "DMA mapping error for RX.\n" ); |
1245 | return -EINVAL; |
1246 | } |
1247 | |
1248 | desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl), |
1249 | sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, |
1250 | dir: DMA_DEV_TO_MEM, flags: DMA_PREP_INTERRUPT); |
1251 | |
1252 | if (!desc) { |
1253 | dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE); |
1254 | dev_err(dev, "We cannot prepare for the RX slave dma!\n" ); |
1255 | return -EINVAL; |
1256 | } |
1257 | desc->callback = imx_uart_dma_rx_callback; |
1258 | desc->callback_param = sport; |
1259 | |
1260 | dev_dbg(dev, "RX: prepare for the DMA.\n" ); |
1261 | sport->dma_is_rxing = 1; |
1262 | sport->rx_cookie = dmaengine_submit(desc); |
1263 | dma_async_issue_pending(chan); |
1264 | return 0; |
1265 | } |
1266 | |
1267 | static void imx_uart_clear_rx_errors(struct imx_port *sport) |
1268 | { |
1269 | struct tty_port *port = &sport->port.state->port; |
1270 | u32 usr1, usr2; |
1271 | |
1272 | usr1 = imx_uart_readl(sport, USR1); |
1273 | usr2 = imx_uart_readl(sport, USR2); |
1274 | |
1275 | if (usr2 & USR2_BRCD) { |
1276 | sport->port.icount.brk++; |
1277 | imx_uart_writel(sport, USR2_BRCD, USR2); |
1278 | uart_handle_break(port: &sport->port); |
1279 | if (tty_insert_flip_char(port, ch: 0, TTY_BREAK) == 0) |
1280 | sport->port.icount.buf_overrun++; |
1281 | tty_flip_buffer_push(port); |
1282 | } else { |
1283 | if (usr1 & USR1_FRAMERR) { |
1284 | sport->port.icount.frame++; |
1285 | imx_uart_writel(sport, USR1_FRAMERR, USR1); |
1286 | } else if (usr1 & USR1_PARITYERR) { |
1287 | sport->port.icount.parity++; |
1288 | imx_uart_writel(sport, USR1_PARITYERR, USR1); |
1289 | } |
1290 | } |
1291 | |
1292 | if (usr2 & USR2_ORE) { |
1293 | sport->port.icount.overrun++; |
1294 | imx_uart_writel(sport, USR2_ORE, USR2); |
1295 | } |
1296 | |
1297 | sport->idle_counter = 0; |
1298 | |
1299 | } |
1300 | |
1301 | #define TXTL_DEFAULT 2 /* reset default */ |
1302 | #define RXTL_DEFAULT 8 /* 8 characters or aging timer */ |
1303 | #define TXTL_DMA 8 /* DMA burst setting */ |
1304 | #define RXTL_DMA 9 /* DMA burst setting */ |
1305 | |
1306 | static void imx_uart_setup_ufcr(struct imx_port *sport, |
1307 | unsigned char txwl, unsigned char rxwl) |
1308 | { |
1309 | unsigned int val; |
1310 | |
1311 | /* set receiver / transmitter trigger level */ |
1312 | val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); |
1313 | val |= txwl << UFCR_TXTL_SHF | rxwl; |
1314 | imx_uart_writel(sport, val, UFCR); |
1315 | } |
1316 | |
1317 | static void imx_uart_dma_exit(struct imx_port *sport) |
1318 | { |
1319 | if (sport->dma_chan_rx) { |
1320 | dmaengine_terminate_sync(chan: sport->dma_chan_rx); |
1321 | dma_release_channel(chan: sport->dma_chan_rx); |
1322 | sport->dma_chan_rx = NULL; |
1323 | sport->rx_cookie = -EINVAL; |
1324 | kfree(objp: sport->rx_buf); |
1325 | sport->rx_buf = NULL; |
1326 | } |
1327 | |
1328 | if (sport->dma_chan_tx) { |
1329 | dmaengine_terminate_sync(chan: sport->dma_chan_tx); |
1330 | dma_release_channel(chan: sport->dma_chan_tx); |
1331 | sport->dma_chan_tx = NULL; |
1332 | } |
1333 | } |
1334 | |
1335 | static int imx_uart_dma_init(struct imx_port *sport) |
1336 | { |
1337 | struct dma_slave_config slave_config = {}; |
1338 | struct device *dev = sport->port.dev; |
1339 | int ret; |
1340 | |
1341 | /* Prepare for RX : */ |
1342 | sport->dma_chan_rx = dma_request_slave_channel(dev, name: "rx" ); |
1343 | if (!sport->dma_chan_rx) { |
1344 | dev_dbg(dev, "cannot get the DMA channel.\n" ); |
1345 | ret = -EINVAL; |
1346 | goto err; |
1347 | } |
1348 | |
1349 | slave_config.direction = DMA_DEV_TO_MEM; |
1350 | slave_config.src_addr = sport->port.mapbase + URXD0; |
1351 | slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; |
1352 | /* one byte less than the watermark level to enable the aging timer */ |
1353 | slave_config.src_maxburst = RXTL_DMA - 1; |
1354 | ret = dmaengine_slave_config(chan: sport->dma_chan_rx, config: &slave_config); |
1355 | if (ret) { |
1356 | dev_err(dev, "error in RX dma configuration.\n" ); |
1357 | goto err; |
1358 | } |
1359 | |
1360 | sport->rx_buf_size = sport->rx_period_length * sport->rx_periods; |
1361 | sport->rx_buf = kzalloc(size: sport->rx_buf_size, GFP_KERNEL); |
1362 | if (!sport->rx_buf) { |
1363 | ret = -ENOMEM; |
1364 | goto err; |
1365 | } |
1366 | sport->rx_ring.buf = sport->rx_buf; |
1367 | |
1368 | /* Prepare for TX : */ |
1369 | sport->dma_chan_tx = dma_request_slave_channel(dev, name: "tx" ); |
1370 | if (!sport->dma_chan_tx) { |
1371 | dev_err(dev, "cannot get the TX DMA channel!\n" ); |
1372 | ret = -EINVAL; |
1373 | goto err; |
1374 | } |
1375 | |
1376 | slave_config.direction = DMA_MEM_TO_DEV; |
1377 | slave_config.dst_addr = sport->port.mapbase + URTX0; |
1378 | slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; |
1379 | slave_config.dst_maxburst = TXTL_DMA; |
1380 | ret = dmaengine_slave_config(chan: sport->dma_chan_tx, config: &slave_config); |
1381 | if (ret) { |
1382 | dev_err(dev, "error in TX dma configuration." ); |
1383 | goto err; |
1384 | } |
1385 | |
1386 | return 0; |
1387 | err: |
1388 | imx_uart_dma_exit(sport); |
1389 | return ret; |
1390 | } |
1391 | |
1392 | static void imx_uart_enable_dma(struct imx_port *sport) |
1393 | { |
1394 | u32 ucr1; |
1395 | |
1396 | imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA); |
1397 | |
1398 | /* set UCR1 */ |
1399 | ucr1 = imx_uart_readl(sport, UCR1); |
1400 | ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN; |
1401 | imx_uart_writel(sport, val: ucr1, UCR1); |
1402 | |
1403 | sport->dma_is_enabled = 1; |
1404 | } |
1405 | |
1406 | static void imx_uart_disable_dma(struct imx_port *sport) |
1407 | { |
1408 | u32 ucr1; |
1409 | |
1410 | /* clear UCR1 */ |
1411 | ucr1 = imx_uart_readl(sport, UCR1); |
1412 | ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN); |
1413 | imx_uart_writel(sport, val: ucr1, UCR1); |
1414 | |
1415 | imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); |
1416 | |
1417 | sport->dma_is_enabled = 0; |
1418 | } |
1419 | |
1420 | /* half the RX buffer size */ |
1421 | #define CTSTL 16 |
1422 | |
1423 | static int imx_uart_startup(struct uart_port *port) |
1424 | { |
1425 | struct imx_port *sport = (struct imx_port *)port; |
1426 | int retval; |
1427 | unsigned long flags; |
1428 | int dma_is_inited = 0; |
1429 | u32 ucr1, ucr2, ucr3, ucr4; |
1430 | |
1431 | retval = clk_prepare_enable(clk: sport->clk_per); |
1432 | if (retval) |
1433 | return retval; |
1434 | retval = clk_prepare_enable(clk: sport->clk_ipg); |
1435 | if (retval) { |
1436 | clk_disable_unprepare(clk: sport->clk_per); |
1437 | return retval; |
1438 | } |
1439 | |
1440 | imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); |
1441 | |
1442 | /* disable the DREN bit (Data Ready interrupt enable) before |
1443 | * requesting IRQs |
1444 | */ |
1445 | ucr4 = imx_uart_readl(sport, UCR4); |
1446 | |
1447 | /* set the trigger level for CTS */ |
1448 | ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); |
1449 | ucr4 |= CTSTL << UCR4_CTSTL_SHF; |
1450 | |
1451 | imx_uart_writel(sport, val: ucr4 & ~UCR4_DREN, UCR4); |
1452 | |
1453 | /* Can we enable the DMA support? */ |
1454 | if (!uart_console(port) && imx_uart_dma_init(sport) == 0) { |
1455 | lockdep_set_subclass(&port->lock, 1); |
1456 | dma_is_inited = 1; |
1457 | } |
1458 | |
1459 | uart_port_lock_irqsave(up: &sport->port, flags: &flags); |
1460 | |
1461 | /* Reset fifo's and state machines */ |
1462 | imx_uart_soft_reset(sport); |
1463 | |
1464 | /* |
1465 | * Finally, clear and enable interrupts |
1466 | */ |
1467 | imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1); |
1468 | imx_uart_writel(sport, USR2_ORE, USR2); |
1469 | |
1470 | ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN; |
1471 | ucr1 |= UCR1_UARTEN; |
1472 | if (sport->have_rtscts) |
1473 | ucr1 |= UCR1_RTSDEN; |
1474 | |
1475 | imx_uart_writel(sport, val: ucr1, UCR1); |
1476 | |
1477 | ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR); |
1478 | if (!dma_is_inited) |
1479 | ucr4 |= UCR4_OREN; |
1480 | if (sport->inverted_rx) |
1481 | ucr4 |= UCR4_INVR; |
1482 | imx_uart_writel(sport, val: ucr4, UCR4); |
1483 | |
1484 | ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT; |
1485 | /* |
1486 | * configure tx polarity before enabling tx |
1487 | */ |
1488 | if (sport->inverted_tx) |
1489 | ucr3 |= UCR3_INVT; |
1490 | |
1491 | if (!imx_uart_is_imx1(sport)) { |
1492 | ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD; |
1493 | |
1494 | if (sport->dte_mode) |
1495 | /* disable broken interrupts */ |
1496 | ucr3 &= ~(UCR3_RI | UCR3_DCD); |
1497 | } |
1498 | imx_uart_writel(sport, val: ucr3, UCR3); |
1499 | |
1500 | ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN; |
1501 | ucr2 |= (UCR2_RXEN | UCR2_TXEN); |
1502 | if (!sport->have_rtscts) |
1503 | ucr2 |= UCR2_IRTS; |
1504 | /* |
1505 | * make sure the edge sensitive RTS-irq is disabled, |
1506 | * we're using RTSD instead. |
1507 | */ |
1508 | if (!imx_uart_is_imx1(sport)) |
1509 | ucr2 &= ~UCR2_RTSEN; |
1510 | imx_uart_writel(sport, val: ucr2, UCR2); |
1511 | |
1512 | /* |
1513 | * Enable modem status interrupts |
1514 | */ |
1515 | imx_uart_enable_ms(port: &sport->port); |
1516 | |
1517 | if (dma_is_inited) { |
1518 | imx_uart_enable_dma(sport); |
1519 | imx_uart_start_rx_dma(sport); |
1520 | } else { |
1521 | ucr1 = imx_uart_readl(sport, UCR1); |
1522 | ucr1 |= UCR1_RRDYEN; |
1523 | imx_uart_writel(sport, val: ucr1, UCR1); |
1524 | |
1525 | ucr2 = imx_uart_readl(sport, UCR2); |
1526 | ucr2 |= UCR2_ATEN; |
1527 | imx_uart_writel(sport, val: ucr2, UCR2); |
1528 | } |
1529 | |
1530 | imx_uart_disable_loopback_rs485(sport); |
1531 | |
1532 | uart_port_unlock_irqrestore(up: &sport->port, flags); |
1533 | |
1534 | return 0; |
1535 | } |
1536 | |
1537 | static void imx_uart_shutdown(struct uart_port *port) |
1538 | { |
1539 | struct imx_port *sport = (struct imx_port *)port; |
1540 | unsigned long flags; |
1541 | u32 ucr1, ucr2, ucr4, uts; |
1542 | |
1543 | if (sport->dma_is_enabled) { |
1544 | dmaengine_terminate_sync(chan: sport->dma_chan_tx); |
1545 | if (sport->dma_is_txing) { |
1546 | dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], |
1547 | sport->dma_tx_nents, DMA_TO_DEVICE); |
1548 | sport->dma_is_txing = 0; |
1549 | } |
1550 | dmaengine_terminate_sync(chan: sport->dma_chan_rx); |
1551 | if (sport->dma_is_rxing) { |
1552 | dma_unmap_sg(sport->port.dev, &sport->rx_sgl, |
1553 | 1, DMA_FROM_DEVICE); |
1554 | sport->dma_is_rxing = 0; |
1555 | } |
1556 | |
1557 | uart_port_lock_irqsave(up: &sport->port, flags: &flags); |
1558 | imx_uart_stop_tx(port); |
1559 | imx_uart_stop_rx(port); |
1560 | imx_uart_disable_dma(sport); |
1561 | uart_port_unlock_irqrestore(up: &sport->port, flags); |
1562 | imx_uart_dma_exit(sport); |
1563 | } |
1564 | |
1565 | mctrl_gpio_disable_ms(gpios: sport->gpios); |
1566 | |
1567 | uart_port_lock_irqsave(up: &sport->port, flags: &flags); |
1568 | ucr2 = imx_uart_readl(sport, UCR2); |
1569 | ucr2 &= ~(UCR2_TXEN | UCR2_ATEN); |
1570 | imx_uart_writel(sport, val: ucr2, UCR2); |
1571 | uart_port_unlock_irqrestore(up: &sport->port, flags); |
1572 | |
1573 | /* |
1574 | * Stop our timer. |
1575 | */ |
1576 | del_timer_sync(timer: &sport->timer); |
1577 | |
1578 | /* |
1579 | * Disable all interrupts, port and break condition. |
1580 | */ |
1581 | |
1582 | uart_port_lock_irqsave(up: &sport->port, flags: &flags); |
1583 | |
1584 | ucr1 = imx_uart_readl(sport, UCR1); |
1585 | ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_RXDMAEN | |
1586 | UCR1_ATDMAEN | UCR1_SNDBRK); |
1587 | /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */ |
1588 | if (port->rs485.flags & SER_RS485_ENABLED && |
1589 | port->rs485.flags & SER_RS485_RTS_ON_SEND && |
1590 | sport->have_rtscts && !sport->have_rtsgpio) { |
1591 | uts = imx_uart_readl(sport, offset: imx_uart_uts_reg(sport)); |
1592 | uts |= UTS_LOOP; |
1593 | imx_uart_writel(sport, val: uts, offset: imx_uart_uts_reg(sport)); |
1594 | ucr1 |= UCR1_UARTEN; |
1595 | } else { |
1596 | ucr1 &= ~UCR1_UARTEN; |
1597 | } |
1598 | imx_uart_writel(sport, val: ucr1, UCR1); |
1599 | |
1600 | ucr4 = imx_uart_readl(sport, UCR4); |
1601 | ucr4 &= ~UCR4_TCEN; |
1602 | imx_uart_writel(sport, val: ucr4, UCR4); |
1603 | |
1604 | uart_port_unlock_irqrestore(up: &sport->port, flags); |
1605 | |
1606 | clk_disable_unprepare(clk: sport->clk_per); |
1607 | clk_disable_unprepare(clk: sport->clk_ipg); |
1608 | } |
1609 | |
1610 | /* called with port.lock taken and irqs off */ |
1611 | static void imx_uart_flush_buffer(struct uart_port *port) |
1612 | { |
1613 | struct imx_port *sport = (struct imx_port *)port; |
1614 | struct scatterlist *sgl = &sport->tx_sgl[0]; |
1615 | |
1616 | if (!sport->dma_chan_tx) |
1617 | return; |
1618 | |
1619 | sport->tx_bytes = 0; |
1620 | dmaengine_terminate_all(chan: sport->dma_chan_tx); |
1621 | if (sport->dma_is_txing) { |
1622 | u32 ucr1; |
1623 | |
1624 | dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, |
1625 | DMA_TO_DEVICE); |
1626 | ucr1 = imx_uart_readl(sport, UCR1); |
1627 | ucr1 &= ~UCR1_TXDMAEN; |
1628 | imx_uart_writel(sport, val: ucr1, UCR1); |
1629 | sport->dma_is_txing = 0; |
1630 | } |
1631 | |
1632 | imx_uart_soft_reset(sport); |
1633 | |
1634 | } |
1635 | |
1636 | static void |
1637 | imx_uart_set_termios(struct uart_port *port, struct ktermios *termios, |
1638 | const struct ktermios *old) |
1639 | { |
1640 | struct imx_port *sport = (struct imx_port *)port; |
1641 | unsigned long flags; |
1642 | u32 ucr2, old_ucr2, ufcr; |
1643 | unsigned int baud, quot; |
1644 | unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; |
1645 | unsigned long div; |
1646 | unsigned long num, denom, old_ubir, old_ubmr; |
1647 | uint64_t tdiv64; |
1648 | |
1649 | /* |
1650 | * We only support CS7 and CS8. |
1651 | */ |
1652 | while ((termios->c_cflag & CSIZE) != CS7 && |
1653 | (termios->c_cflag & CSIZE) != CS8) { |
1654 | termios->c_cflag &= ~CSIZE; |
1655 | termios->c_cflag |= old_csize; |
1656 | old_csize = CS8; |
1657 | } |
1658 | |
1659 | del_timer_sync(timer: &sport->timer); |
1660 | |
1661 | /* |
1662 | * Ask the core to calculate the divisor for us. |
1663 | */ |
1664 | baud = uart_get_baud_rate(port, termios, old, min: 50, max: port->uartclk / 16); |
1665 | quot = uart_get_divisor(port, baud); |
1666 | |
1667 | uart_port_lock_irqsave(up: &sport->port, flags: &flags); |
1668 | |
1669 | /* |
1670 | * Read current UCR2 and save it for future use, then clear all the bits |
1671 | * except those we will or may need to preserve. |
1672 | */ |
1673 | old_ucr2 = imx_uart_readl(sport, UCR2); |
1674 | ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS); |
1675 | |
1676 | ucr2 |= UCR2_SRST | UCR2_IRTS; |
1677 | if ((termios->c_cflag & CSIZE) == CS8) |
1678 | ucr2 |= UCR2_WS; |
1679 | |
1680 | if (!sport->have_rtscts) |
1681 | termios->c_cflag &= ~CRTSCTS; |
1682 | |
1683 | if (port->rs485.flags & SER_RS485_ENABLED) { |
1684 | /* |
1685 | * RTS is mandatory for rs485 operation, so keep |
1686 | * it under manual control and keep transmitter |
1687 | * disabled. |
1688 | */ |
1689 | if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) |
1690 | imx_uart_rts_active(sport, ucr2: &ucr2); |
1691 | else |
1692 | imx_uart_rts_inactive(sport, ucr2: &ucr2); |
1693 | |
1694 | } else if (termios->c_cflag & CRTSCTS) { |
1695 | /* |
1696 | * Only let receiver control RTS output if we were not requested |
1697 | * to have RTS inactive (which then should take precedence). |
1698 | */ |
1699 | if (ucr2 & UCR2_CTS) |
1700 | ucr2 |= UCR2_CTSC; |
1701 | } |
1702 | |
1703 | if (termios->c_cflag & CRTSCTS) |
1704 | ucr2 &= ~UCR2_IRTS; |
1705 | if (termios->c_cflag & CSTOPB) |
1706 | ucr2 |= UCR2_STPB; |
1707 | if (termios->c_cflag & PARENB) { |
1708 | ucr2 |= UCR2_PREN; |
1709 | if (termios->c_cflag & PARODD) |
1710 | ucr2 |= UCR2_PROE; |
1711 | } |
1712 | |
1713 | sport->port.read_status_mask = 0; |
1714 | if (termios->c_iflag & INPCK) |
1715 | sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); |
1716 | if (termios->c_iflag & (BRKINT | PARMRK)) |
1717 | sport->port.read_status_mask |= URXD_BRK; |
1718 | |
1719 | /* |
1720 | * Characters to ignore |
1721 | */ |
1722 | sport->port.ignore_status_mask = 0; |
1723 | if (termios->c_iflag & IGNPAR) |
1724 | sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; |
1725 | if (termios->c_iflag & IGNBRK) { |
1726 | sport->port.ignore_status_mask |= URXD_BRK; |
1727 | /* |
1728 | * If we're ignoring parity and break indicators, |
1729 | * ignore overruns too (for real raw support). |
1730 | */ |
1731 | if (termios->c_iflag & IGNPAR) |
1732 | sport->port.ignore_status_mask |= URXD_OVRRUN; |
1733 | } |
1734 | |
1735 | if ((termios->c_cflag & CREAD) == 0) |
1736 | sport->port.ignore_status_mask |= URXD_DUMMY_READ; |
1737 | |
1738 | /* |
1739 | * Update the per-port timeout. |
1740 | */ |
1741 | uart_update_timeout(port, cflag: termios->c_cflag, baud); |
1742 | |
1743 | /* custom-baudrate handling */ |
1744 | div = sport->port.uartclk / (baud * 16); |
1745 | if (baud == 38400 && quot != div) |
1746 | baud = sport->port.uartclk / (quot * 16); |
1747 | |
1748 | div = sport->port.uartclk / (baud * 16); |
1749 | if (div > 7) |
1750 | div = 7; |
1751 | if (!div) |
1752 | div = 1; |
1753 | |
1754 | rational_best_approximation(given_numerator: 16 * div * baud, given_denominator: sport->port.uartclk, |
1755 | max_numerator: 1 << 16, max_denominator: 1 << 16, best_numerator: &num, best_denominator: &denom); |
1756 | |
1757 | tdiv64 = sport->port.uartclk; |
1758 | tdiv64 *= num; |
1759 | do_div(tdiv64, denom * 16 * div); |
1760 | tty_termios_encode_baud_rate(termios, |
1761 | ibaud: (speed_t)tdiv64, obaud: (speed_t)tdiv64); |
1762 | |
1763 | num -= 1; |
1764 | denom -= 1; |
1765 | |
1766 | ufcr = imx_uart_readl(sport, UFCR); |
1767 | ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); |
1768 | imx_uart_writel(sport, val: ufcr, UFCR); |
1769 | |
1770 | /* |
1771 | * Two registers below should always be written both and in this |
1772 | * particular order. One consequence is that we need to check if any of |
1773 | * them changes and then update both. We do need the check for change |
1774 | * as even writing the same values seem to "restart" |
1775 | * transmission/receiving logic in the hardware, that leads to data |
1776 | * breakage even when rate doesn't in fact change. E.g., user switches |
1777 | * RTS/CTS handshake and suddenly gets broken bytes. |
1778 | */ |
1779 | old_ubir = imx_uart_readl(sport, UBIR); |
1780 | old_ubmr = imx_uart_readl(sport, UBMR); |
1781 | if (old_ubir != num || old_ubmr != denom) { |
1782 | imx_uart_writel(sport, val: num, UBIR); |
1783 | imx_uart_writel(sport, val: denom, UBMR); |
1784 | } |
1785 | |
1786 | if (!imx_uart_is_imx1(sport)) |
1787 | imx_uart_writel(sport, val: sport->port.uartclk / div / 1000, |
1788 | IMX21_ONEMS); |
1789 | |
1790 | imx_uart_writel(sport, val: ucr2, UCR2); |
1791 | |
1792 | if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) |
1793 | imx_uart_enable_ms(port: &sport->port); |
1794 | |
1795 | uart_port_unlock_irqrestore(up: &sport->port, flags); |
1796 | } |
1797 | |
1798 | static const char *imx_uart_type(struct uart_port *port) |
1799 | { |
1800 | return port->type == PORT_IMX ? "IMX" : NULL; |
1801 | } |
1802 | |
1803 | /* |
1804 | * Configure/autoconfigure the port. |
1805 | */ |
1806 | static void imx_uart_config_port(struct uart_port *port, int flags) |
1807 | { |
1808 | if (flags & UART_CONFIG_TYPE) |
1809 | port->type = PORT_IMX; |
1810 | } |
1811 | |
1812 | /* |
1813 | * Verify the new serial_struct (for TIOCSSERIAL). |
1814 | * The only change we allow are to the flags and type, and |
1815 | * even then only between PORT_IMX and PORT_UNKNOWN |
1816 | */ |
1817 | static int |
1818 | imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser) |
1819 | { |
1820 | int ret = 0; |
1821 | |
1822 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) |
1823 | ret = -EINVAL; |
1824 | if (port->irq != ser->irq) |
1825 | ret = -EINVAL; |
1826 | if (ser->io_type != UPIO_MEM) |
1827 | ret = -EINVAL; |
1828 | if (port->uartclk / 16 != ser->baud_base) |
1829 | ret = -EINVAL; |
1830 | if (port->mapbase != (unsigned long)ser->iomem_base) |
1831 | ret = -EINVAL; |
1832 | if (port->iobase != ser->port) |
1833 | ret = -EINVAL; |
1834 | if (ser->hub6 != 0) |
1835 | ret = -EINVAL; |
1836 | return ret; |
1837 | } |
1838 | |
1839 | #if defined(CONFIG_CONSOLE_POLL) |
1840 | |
1841 | static int imx_uart_poll_init(struct uart_port *port) |
1842 | { |
1843 | struct imx_port *sport = (struct imx_port *)port; |
1844 | unsigned long flags; |
1845 | u32 ucr1, ucr2; |
1846 | int retval; |
1847 | |
1848 | retval = clk_prepare_enable(clk: sport->clk_ipg); |
1849 | if (retval) |
1850 | return retval; |
1851 | retval = clk_prepare_enable(clk: sport->clk_per); |
1852 | if (retval) |
1853 | clk_disable_unprepare(clk: sport->clk_ipg); |
1854 | |
1855 | imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); |
1856 | |
1857 | uart_port_lock_irqsave(up: &sport->port, flags: &flags); |
1858 | |
1859 | /* |
1860 | * Be careful about the order of enabling bits here. First enable the |
1861 | * receiver (UARTEN + RXEN) and only then the corresponding irqs. |
1862 | * This prevents that a character that already sits in the RX fifo is |
1863 | * triggering an irq but the try to fetch it from there results in an |
1864 | * exception because UARTEN or RXEN is still off. |
1865 | */ |
1866 | ucr1 = imx_uart_readl(sport, UCR1); |
1867 | ucr2 = imx_uart_readl(sport, UCR2); |
1868 | |
1869 | if (imx_uart_is_imx1(sport)) |
1870 | ucr1 |= IMX1_UCR1_UARTCLKEN; |
1871 | |
1872 | ucr1 |= UCR1_UARTEN; |
1873 | ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN); |
1874 | |
1875 | ucr2 |= UCR2_RXEN | UCR2_TXEN; |
1876 | ucr2 &= ~UCR2_ATEN; |
1877 | |
1878 | imx_uart_writel(sport, val: ucr1, UCR1); |
1879 | imx_uart_writel(sport, val: ucr2, UCR2); |
1880 | |
1881 | /* now enable irqs */ |
1882 | imx_uart_writel(sport, val: ucr1 | UCR1_RRDYEN, UCR1); |
1883 | imx_uart_writel(sport, val: ucr2 | UCR2_ATEN, UCR2); |
1884 | |
1885 | uart_port_unlock_irqrestore(up: &sport->port, flags); |
1886 | |
1887 | return 0; |
1888 | } |
1889 | |
1890 | static int imx_uart_poll_get_char(struct uart_port *port) |
1891 | { |
1892 | struct imx_port *sport = (struct imx_port *)port; |
1893 | if (!(imx_uart_readl(sport, USR2) & USR2_RDR)) |
1894 | return NO_POLL_CHAR; |
1895 | |
1896 | return imx_uart_readl(sport, URXD0) & URXD_RX_DATA; |
1897 | } |
1898 | |
1899 | static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c) |
1900 | { |
1901 | struct imx_port *sport = (struct imx_port *)port; |
1902 | unsigned int status; |
1903 | |
1904 | /* drain */ |
1905 | do { |
1906 | status = imx_uart_readl(sport, USR1); |
1907 | } while (~status & USR1_TRDY); |
1908 | |
1909 | /* write */ |
1910 | imx_uart_writel(sport, val: c, URTX0); |
1911 | |
1912 | /* flush */ |
1913 | do { |
1914 | status = imx_uart_readl(sport, USR2); |
1915 | } while (~status & USR2_TXDC); |
1916 | } |
1917 | #endif |
1918 | |
1919 | /* called with port.lock taken and irqs off or from .probe without locking */ |
1920 | static int imx_uart_rs485_config(struct uart_port *port, struct ktermios *termios, |
1921 | struct serial_rs485 *rs485conf) |
1922 | { |
1923 | struct imx_port *sport = (struct imx_port *)port; |
1924 | u32 ucr2; |
1925 | |
1926 | if (rs485conf->flags & SER_RS485_ENABLED) { |
1927 | /* Enable receiver if low-active RTS signal is requested */ |
1928 | if (sport->have_rtscts && !sport->have_rtsgpio && |
1929 | !(rs485conf->flags & SER_RS485_RTS_ON_SEND)) |
1930 | rs485conf->flags |= SER_RS485_RX_DURING_TX; |
1931 | |
1932 | /* disable transmitter */ |
1933 | ucr2 = imx_uart_readl(sport, UCR2); |
1934 | if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) |
1935 | imx_uart_rts_active(sport, ucr2: &ucr2); |
1936 | else |
1937 | imx_uart_rts_inactive(sport, ucr2: &ucr2); |
1938 | imx_uart_writel(sport, val: ucr2, UCR2); |
1939 | } |
1940 | |
1941 | /* Make sure Rx is enabled in case Tx is active with Rx disabled */ |
1942 | if (!(rs485conf->flags & SER_RS485_ENABLED) || |
1943 | rs485conf->flags & SER_RS485_RX_DURING_TX) |
1944 | imx_uart_start_rx(port); |
1945 | |
1946 | if (port->rs485_rx_during_tx_gpio) |
1947 | gpiod_set_value_cansleep(desc: port->rs485_rx_during_tx_gpio, |
1948 | value: !!(rs485conf->flags & SER_RS485_RX_DURING_TX)); |
1949 | |
1950 | return 0; |
1951 | } |
1952 | |
1953 | static const struct uart_ops imx_uart_pops = { |
1954 | .tx_empty = imx_uart_tx_empty, |
1955 | .set_mctrl = imx_uart_set_mctrl, |
1956 | .get_mctrl = imx_uart_get_mctrl, |
1957 | .stop_tx = imx_uart_stop_tx, |
1958 | .start_tx = imx_uart_start_tx, |
1959 | .stop_rx = imx_uart_stop_rx, |
1960 | .enable_ms = imx_uart_enable_ms, |
1961 | .break_ctl = imx_uart_break_ctl, |
1962 | .startup = imx_uart_startup, |
1963 | .shutdown = imx_uart_shutdown, |
1964 | .flush_buffer = imx_uart_flush_buffer, |
1965 | .set_termios = imx_uart_set_termios, |
1966 | .type = imx_uart_type, |
1967 | .config_port = imx_uart_config_port, |
1968 | .verify_port = imx_uart_verify_port, |
1969 | #if defined(CONFIG_CONSOLE_POLL) |
1970 | .poll_init = imx_uart_poll_init, |
1971 | .poll_get_char = imx_uart_poll_get_char, |
1972 | .poll_put_char = imx_uart_poll_put_char, |
1973 | #endif |
1974 | }; |
1975 | |
1976 | static struct imx_port *imx_uart_ports[UART_NR]; |
1977 | |
1978 | #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE) |
1979 | static void imx_uart_console_putchar(struct uart_port *port, unsigned char ch) |
1980 | { |
1981 | struct imx_port *sport = (struct imx_port *)port; |
1982 | |
1983 | while (imx_uart_readl(sport, offset: imx_uart_uts_reg(sport)) & UTS_TXFULL) |
1984 | barrier(); |
1985 | |
1986 | imx_uart_writel(sport, val: ch, URTX0); |
1987 | } |
1988 | |
1989 | /* |
1990 | * Interrupts are disabled on entering |
1991 | */ |
1992 | static void |
1993 | imx_uart_console_write(struct console *co, const char *s, unsigned int count) |
1994 | { |
1995 | struct imx_port *sport = imx_uart_ports[co->index]; |
1996 | struct imx_port_ucrs old_ucr; |
1997 | unsigned long flags; |
1998 | unsigned int ucr1; |
1999 | int locked = 1; |
2000 | |
2001 | if (sport->port.sysrq) |
2002 | locked = 0; |
2003 | else if (oops_in_progress) |
2004 | locked = uart_port_trylock_irqsave(up: &sport->port, flags: &flags); |
2005 | else |
2006 | uart_port_lock_irqsave(up: &sport->port, flags: &flags); |
2007 | |
2008 | /* |
2009 | * First, save UCR1/2/3 and then disable interrupts |
2010 | */ |
2011 | imx_uart_ucrs_save(sport, ucr: &old_ucr); |
2012 | ucr1 = old_ucr.ucr1; |
2013 | |
2014 | if (imx_uart_is_imx1(sport)) |
2015 | ucr1 |= IMX1_UCR1_UARTCLKEN; |
2016 | ucr1 |= UCR1_UARTEN; |
2017 | ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN); |
2018 | |
2019 | imx_uart_writel(sport, val: ucr1, UCR1); |
2020 | |
2021 | imx_uart_writel(sport, val: old_ucr.ucr2 | UCR2_TXEN, UCR2); |
2022 | |
2023 | uart_console_write(port: &sport->port, s, count, putchar: imx_uart_console_putchar); |
2024 | |
2025 | /* |
2026 | * Finally, wait for transmitter to become empty |
2027 | * and restore UCR1/2/3 |
2028 | */ |
2029 | while (!(imx_uart_readl(sport, USR2) & USR2_TXDC)); |
2030 | |
2031 | imx_uart_ucrs_restore(sport, ucr: &old_ucr); |
2032 | |
2033 | if (locked) |
2034 | uart_port_unlock_irqrestore(up: &sport->port, flags); |
2035 | } |
2036 | |
2037 | /* |
2038 | * If the port was already initialised (eg, by a boot loader), |
2039 | * try to determine the current setup. |
2040 | */ |
2041 | static void |
2042 | imx_uart_console_get_options(struct imx_port *sport, int *baud, |
2043 | int *parity, int *bits) |
2044 | { |
2045 | |
2046 | if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) { |
2047 | /* ok, the port was enabled */ |
2048 | unsigned int ucr2, ubir, ubmr, uartclk; |
2049 | unsigned int baud_raw; |
2050 | unsigned int ucfr_rfdiv; |
2051 | |
2052 | ucr2 = imx_uart_readl(sport, UCR2); |
2053 | |
2054 | *parity = 'n'; |
2055 | if (ucr2 & UCR2_PREN) { |
2056 | if (ucr2 & UCR2_PROE) |
2057 | *parity = 'o'; |
2058 | else |
2059 | *parity = 'e'; |
2060 | } |
2061 | |
2062 | if (ucr2 & UCR2_WS) |
2063 | *bits = 8; |
2064 | else |
2065 | *bits = 7; |
2066 | |
2067 | ubir = imx_uart_readl(sport, UBIR) & 0xffff; |
2068 | ubmr = imx_uart_readl(sport, UBMR) & 0xffff; |
2069 | |
2070 | ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7; |
2071 | if (ucfr_rfdiv == 6) |
2072 | ucfr_rfdiv = 7; |
2073 | else |
2074 | ucfr_rfdiv = 6 - ucfr_rfdiv; |
2075 | |
2076 | uartclk = clk_get_rate(clk: sport->clk_per); |
2077 | uartclk /= ucfr_rfdiv; |
2078 | |
2079 | { /* |
2080 | * The next code provides exact computation of |
2081 | * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) |
2082 | * without need of float support or long long division, |
2083 | * which would be required to prevent 32bit arithmetic overflow |
2084 | */ |
2085 | unsigned int mul = ubir + 1; |
2086 | unsigned int div = 16 * (ubmr + 1); |
2087 | unsigned int rem = uartclk % div; |
2088 | |
2089 | baud_raw = (uartclk / div) * mul; |
2090 | baud_raw += (rem * mul + div / 2) / div; |
2091 | *baud = (baud_raw + 50) / 100 * 100; |
2092 | } |
2093 | |
2094 | if (*baud != baud_raw) |
2095 | dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n" , |
2096 | baud_raw, *baud); |
2097 | } |
2098 | } |
2099 | |
2100 | static int |
2101 | imx_uart_console_setup(struct console *co, char *options) |
2102 | { |
2103 | struct imx_port *sport; |
2104 | int baud = 9600; |
2105 | int bits = 8; |
2106 | int parity = 'n'; |
2107 | int flow = 'n'; |
2108 | int retval; |
2109 | |
2110 | /* |
2111 | * Check whether an invalid uart number has been specified, and |
2112 | * if so, search for the first available port that does have |
2113 | * console support. |
2114 | */ |
2115 | if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports)) |
2116 | co->index = 0; |
2117 | sport = imx_uart_ports[co->index]; |
2118 | if (sport == NULL) |
2119 | return -ENODEV; |
2120 | |
2121 | /* For setting the registers, we only need to enable the ipg clock. */ |
2122 | retval = clk_prepare_enable(clk: sport->clk_ipg); |
2123 | if (retval) |
2124 | goto error_console; |
2125 | |
2126 | if (options) |
2127 | uart_parse_options(options, baud: &baud, parity: &parity, bits: &bits, flow: &flow); |
2128 | else |
2129 | imx_uart_console_get_options(sport, baud: &baud, parity: &parity, bits: &bits); |
2130 | |
2131 | imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); |
2132 | |
2133 | retval = uart_set_options(port: &sport->port, co, baud, parity, bits, flow); |
2134 | |
2135 | if (retval) { |
2136 | clk_disable_unprepare(clk: sport->clk_ipg); |
2137 | goto error_console; |
2138 | } |
2139 | |
2140 | retval = clk_prepare_enable(clk: sport->clk_per); |
2141 | if (retval) |
2142 | clk_disable_unprepare(clk: sport->clk_ipg); |
2143 | |
2144 | error_console: |
2145 | return retval; |
2146 | } |
2147 | |
2148 | static int |
2149 | imx_uart_console_exit(struct console *co) |
2150 | { |
2151 | struct imx_port *sport = imx_uart_ports[co->index]; |
2152 | |
2153 | clk_disable_unprepare(clk: sport->clk_per); |
2154 | clk_disable_unprepare(clk: sport->clk_ipg); |
2155 | |
2156 | return 0; |
2157 | } |
2158 | |
2159 | static struct uart_driver imx_uart_uart_driver; |
2160 | static struct console imx_uart_console = { |
2161 | .name = DEV_NAME, |
2162 | .write = imx_uart_console_write, |
2163 | .device = uart_console_device, |
2164 | .setup = imx_uart_console_setup, |
2165 | .exit = imx_uart_console_exit, |
2166 | .flags = CON_PRINTBUFFER, |
2167 | .index = -1, |
2168 | .data = &imx_uart_uart_driver, |
2169 | }; |
2170 | |
2171 | #define IMX_CONSOLE &imx_uart_console |
2172 | |
2173 | #else |
2174 | #define IMX_CONSOLE NULL |
2175 | #endif |
2176 | |
2177 | static struct uart_driver imx_uart_uart_driver = { |
2178 | .owner = THIS_MODULE, |
2179 | .driver_name = DRIVER_NAME, |
2180 | .dev_name = DEV_NAME, |
2181 | .major = SERIAL_IMX_MAJOR, |
2182 | .minor = MINOR_START, |
2183 | .nr = ARRAY_SIZE(imx_uart_ports), |
2184 | .cons = IMX_CONSOLE, |
2185 | }; |
2186 | |
2187 | static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t) |
2188 | { |
2189 | struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx); |
2190 | unsigned long flags; |
2191 | |
2192 | uart_port_lock_irqsave(up: &sport->port, flags: &flags); |
2193 | if (sport->tx_state == WAIT_AFTER_RTS) |
2194 | imx_uart_start_tx(port: &sport->port); |
2195 | uart_port_unlock_irqrestore(up: &sport->port, flags); |
2196 | |
2197 | return HRTIMER_NORESTART; |
2198 | } |
2199 | |
2200 | static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t) |
2201 | { |
2202 | struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx); |
2203 | unsigned long flags; |
2204 | |
2205 | uart_port_lock_irqsave(up: &sport->port, flags: &flags); |
2206 | if (sport->tx_state == WAIT_AFTER_SEND) |
2207 | imx_uart_stop_tx(port: &sport->port); |
2208 | uart_port_unlock_irqrestore(up: &sport->port, flags); |
2209 | |
2210 | return HRTIMER_NORESTART; |
2211 | } |
2212 | |
2213 | static const struct serial_rs485 imx_no_rs485 = {}; /* No RS485 if no RTS */ |
2214 | static const struct serial_rs485 imx_rs485_supported = { |
2215 | .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND | |
2216 | SER_RS485_RX_DURING_TX, |
2217 | .delay_rts_before_send = 1, |
2218 | .delay_rts_after_send = 1, |
2219 | }; |
2220 | |
2221 | /* Default RX DMA buffer configuration */ |
2222 | #define RX_DMA_PERIODS 16 |
2223 | #define RX_DMA_PERIOD_LEN (PAGE_SIZE / 4) |
2224 | |
2225 | static int imx_uart_probe(struct platform_device *pdev) |
2226 | { |
2227 | struct device_node *np = pdev->dev.of_node; |
2228 | struct imx_port *sport; |
2229 | void __iomem *base; |
2230 | u32 dma_buf_conf[2]; |
2231 | int ret = 0; |
2232 | u32 ucr1, ucr2, uts; |
2233 | struct resource *res; |
2234 | int txirq, rxirq, rtsirq; |
2235 | |
2236 | sport = devm_kzalloc(dev: &pdev->dev, size: sizeof(*sport), GFP_KERNEL); |
2237 | if (!sport) |
2238 | return -ENOMEM; |
2239 | |
2240 | sport->devdata = of_device_get_match_data(dev: &pdev->dev); |
2241 | |
2242 | ret = of_alias_get_id(np, stem: "serial" ); |
2243 | if (ret < 0) { |
2244 | dev_err(&pdev->dev, "failed to get alias id, errno %d\n" , ret); |
2245 | return ret; |
2246 | } |
2247 | sport->port.line = ret; |
2248 | |
2249 | sport->have_rtscts = of_property_read_bool(np, propname: "uart-has-rtscts" ) || |
2250 | of_property_read_bool(np, propname: "fsl,uart-has-rtscts" ); /* deprecated */ |
2251 | |
2252 | sport->dte_mode = of_property_read_bool(np, propname: "fsl,dte-mode" ); |
2253 | |
2254 | sport->have_rtsgpio = of_property_present(np, propname: "rts-gpios" ); |
2255 | |
2256 | sport->inverted_tx = of_property_read_bool(np, propname: "fsl,inverted-tx" ); |
2257 | |
2258 | sport->inverted_rx = of_property_read_bool(np, propname: "fsl,inverted-rx" ); |
2259 | |
2260 | if (!of_property_read_u32_array(np, propname: "fsl,dma-info" , out_values: dma_buf_conf, sz: 2)) { |
2261 | sport->rx_period_length = dma_buf_conf[0]; |
2262 | sport->rx_periods = dma_buf_conf[1]; |
2263 | } else { |
2264 | sport->rx_period_length = RX_DMA_PERIOD_LEN; |
2265 | sport->rx_periods = RX_DMA_PERIODS; |
2266 | } |
2267 | |
2268 | if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) { |
2269 | dev_err(&pdev->dev, "serial%d out of range\n" , |
2270 | sport->port.line); |
2271 | return -EINVAL; |
2272 | } |
2273 | |
2274 | base = devm_platform_get_and_ioremap_resource(pdev, index: 0, res: &res); |
2275 | if (IS_ERR(ptr: base)) |
2276 | return PTR_ERR(ptr: base); |
2277 | |
2278 | rxirq = platform_get_irq(pdev, 0); |
2279 | if (rxirq < 0) |
2280 | return rxirq; |
2281 | txirq = platform_get_irq_optional(pdev, 1); |
2282 | rtsirq = platform_get_irq_optional(pdev, 2); |
2283 | |
2284 | sport->port.dev = &pdev->dev; |
2285 | sport->port.mapbase = res->start; |
2286 | sport->port.membase = base; |
2287 | sport->port.type = PORT_IMX; |
2288 | sport->port.iotype = UPIO_MEM; |
2289 | sport->port.irq = rxirq; |
2290 | sport->port.fifosize = 32; |
2291 | sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE); |
2292 | sport->port.ops = &imx_uart_pops; |
2293 | sport->port.rs485_config = imx_uart_rs485_config; |
2294 | /* RTS is required to control the RS485 transmitter */ |
2295 | if (sport->have_rtscts || sport->have_rtsgpio) |
2296 | sport->port.rs485_supported = imx_rs485_supported; |
2297 | else |
2298 | sport->port.rs485_supported = imx_no_rs485; |
2299 | sport->port.flags = UPF_BOOT_AUTOCONF; |
2300 | timer_setup(&sport->timer, imx_uart_timeout, 0); |
2301 | |
2302 | sport->gpios = mctrl_gpio_init(port: &sport->port, idx: 0); |
2303 | if (IS_ERR(ptr: sport->gpios)) |
2304 | return PTR_ERR(ptr: sport->gpios); |
2305 | |
2306 | sport->clk_ipg = devm_clk_get(dev: &pdev->dev, id: "ipg" ); |
2307 | if (IS_ERR(ptr: sport->clk_ipg)) { |
2308 | ret = PTR_ERR(ptr: sport->clk_ipg); |
2309 | dev_err(&pdev->dev, "failed to get ipg clk: %d\n" , ret); |
2310 | return ret; |
2311 | } |
2312 | |
2313 | sport->clk_per = devm_clk_get(dev: &pdev->dev, id: "per" ); |
2314 | if (IS_ERR(ptr: sport->clk_per)) { |
2315 | ret = PTR_ERR(ptr: sport->clk_per); |
2316 | dev_err(&pdev->dev, "failed to get per clk: %d\n" , ret); |
2317 | return ret; |
2318 | } |
2319 | |
2320 | sport->port.uartclk = clk_get_rate(clk: sport->clk_per); |
2321 | |
2322 | /* For register access, we only need to enable the ipg clock. */ |
2323 | ret = clk_prepare_enable(clk: sport->clk_ipg); |
2324 | if (ret) { |
2325 | dev_err(&pdev->dev, "failed to enable per clk: %d\n" , ret); |
2326 | return ret; |
2327 | } |
2328 | |
2329 | ret = uart_get_rs485_mode(port: &sport->port); |
2330 | if (ret) { |
2331 | clk_disable_unprepare(clk: sport->clk_ipg); |
2332 | return ret; |
2333 | } |
2334 | |
2335 | if (sport->port.rs485.flags & SER_RS485_ENABLED && |
2336 | (!sport->have_rtscts && !sport->have_rtsgpio)) |
2337 | dev_err(&pdev->dev, "no RTS control, disabling rs485\n" ); |
2338 | |
2339 | /* |
2340 | * If using the i.MX UART RTS/CTS control then the RTS (CTS_B) |
2341 | * signal cannot be set low during transmission in case the |
2342 | * receiver is off (limitation of the i.MX UART IP). |
2343 | */ |
2344 | if (sport->port.rs485.flags & SER_RS485_ENABLED && |
2345 | sport->have_rtscts && !sport->have_rtsgpio && |
2346 | (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) && |
2347 | !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX))) |
2348 | dev_err(&pdev->dev, |
2349 | "low-active RTS not possible when receiver is off, enabling receiver\n" ); |
2350 | |
2351 | /* Disable interrupts before requesting them */ |
2352 | ucr1 = imx_uart_readl(sport, UCR1); |
2353 | ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN); |
2354 | imx_uart_writel(sport, val: ucr1, UCR1); |
2355 | |
2356 | /* Disable Ageing Timer interrupt */ |
2357 | ucr2 = imx_uart_readl(sport, UCR2); |
2358 | ucr2 &= ~UCR2_ATEN; |
2359 | imx_uart_writel(sport, val: ucr2, UCR2); |
2360 | |
2361 | /* |
2362 | * In case RS485 is enabled without GPIO RTS control, the UART IP |
2363 | * is used to control CTS signal. Keep both the UART and Receiver |
2364 | * enabled, otherwise the UART IP pulls CTS signal always HIGH no |
2365 | * matter how the UCR2 CTSC and CTS bits are set. To prevent any |
2366 | * data from being fed into the RX FIFO, enable loopback mode in |
2367 | * UTS register, which disconnects the RX path from external RXD |
2368 | * pin and connects it to the Transceiver, which is disabled, so |
2369 | * no data can be fed to the RX FIFO that way. |
2370 | */ |
2371 | if (sport->port.rs485.flags & SER_RS485_ENABLED && |
2372 | sport->have_rtscts && !sport->have_rtsgpio) { |
2373 | uts = imx_uart_readl(sport, offset: imx_uart_uts_reg(sport)); |
2374 | uts |= UTS_LOOP; |
2375 | imx_uart_writel(sport, val: uts, offset: imx_uart_uts_reg(sport)); |
2376 | |
2377 | ucr1 = imx_uart_readl(sport, UCR1); |
2378 | ucr1 |= UCR1_UARTEN; |
2379 | imx_uart_writel(sport, val: ucr1, UCR1); |
2380 | |
2381 | ucr2 = imx_uart_readl(sport, UCR2); |
2382 | ucr2 |= UCR2_RXEN; |
2383 | imx_uart_writel(sport, val: ucr2, UCR2); |
2384 | } |
2385 | |
2386 | if (!imx_uart_is_imx1(sport) && sport->dte_mode) { |
2387 | /* |
2388 | * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI |
2389 | * and influences if UCR3_RI and UCR3_DCD changes the level of RI |
2390 | * and DCD (when they are outputs) or enables the respective |
2391 | * irqs. So set this bit early, i.e. before requesting irqs. |
2392 | */ |
2393 | u32 ufcr = imx_uart_readl(sport, UFCR); |
2394 | if (!(ufcr & UFCR_DCEDTE)) |
2395 | imx_uart_writel(sport, val: ufcr | UFCR_DCEDTE, UFCR); |
2396 | |
2397 | /* |
2398 | * Disable UCR3_RI and UCR3_DCD irqs. They are also not |
2399 | * enabled later because they cannot be cleared |
2400 | * (confirmed on i.MX25) which makes them unusable. |
2401 | */ |
2402 | imx_uart_writel(sport, |
2403 | IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR, |
2404 | UCR3); |
2405 | |
2406 | } else { |
2407 | u32 ucr3 = UCR3_DSR; |
2408 | u32 ufcr = imx_uart_readl(sport, UFCR); |
2409 | if (ufcr & UFCR_DCEDTE) |
2410 | imx_uart_writel(sport, val: ufcr & ~UFCR_DCEDTE, UFCR); |
2411 | |
2412 | if (!imx_uart_is_imx1(sport)) |
2413 | ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; |
2414 | imx_uart_writel(sport, val: ucr3, UCR3); |
2415 | } |
2416 | |
2417 | clk_disable_unprepare(clk: sport->clk_ipg); |
2418 | |
2419 | hrtimer_init(timer: &sport->trigger_start_tx, CLOCK_MONOTONIC, mode: HRTIMER_MODE_REL); |
2420 | hrtimer_init(timer: &sport->trigger_stop_tx, CLOCK_MONOTONIC, mode: HRTIMER_MODE_REL); |
2421 | sport->trigger_start_tx.function = imx_trigger_start_tx; |
2422 | sport->trigger_stop_tx.function = imx_trigger_stop_tx; |
2423 | |
2424 | /* |
2425 | * Allocate the IRQ(s) i.MX1 has three interrupts whereas later |
2426 | * chips only have one interrupt. |
2427 | */ |
2428 | if (txirq > 0) { |
2429 | ret = devm_request_irq(dev: &pdev->dev, irq: rxirq, handler: imx_uart_rxint, irqflags: 0, |
2430 | devname: dev_name(dev: &pdev->dev), dev_id: sport); |
2431 | if (ret) { |
2432 | dev_err(&pdev->dev, "failed to request rx irq: %d\n" , |
2433 | ret); |
2434 | return ret; |
2435 | } |
2436 | |
2437 | ret = devm_request_irq(dev: &pdev->dev, irq: txirq, handler: imx_uart_txint, irqflags: 0, |
2438 | devname: dev_name(dev: &pdev->dev), dev_id: sport); |
2439 | if (ret) { |
2440 | dev_err(&pdev->dev, "failed to request tx irq: %d\n" , |
2441 | ret); |
2442 | return ret; |
2443 | } |
2444 | |
2445 | ret = devm_request_irq(dev: &pdev->dev, irq: rtsirq, handler: imx_uart_rtsint, irqflags: 0, |
2446 | devname: dev_name(dev: &pdev->dev), dev_id: sport); |
2447 | if (ret) { |
2448 | dev_err(&pdev->dev, "failed to request rts irq: %d\n" , |
2449 | ret); |
2450 | return ret; |
2451 | } |
2452 | } else { |
2453 | ret = devm_request_irq(dev: &pdev->dev, irq: rxirq, handler: imx_uart_int, irqflags: 0, |
2454 | devname: dev_name(dev: &pdev->dev), dev_id: sport); |
2455 | if (ret) { |
2456 | dev_err(&pdev->dev, "failed to request irq: %d\n" , ret); |
2457 | return ret; |
2458 | } |
2459 | } |
2460 | |
2461 | imx_uart_ports[sport->port.line] = sport; |
2462 | |
2463 | platform_set_drvdata(pdev, data: sport); |
2464 | |
2465 | return uart_add_one_port(reg: &imx_uart_uart_driver, port: &sport->port); |
2466 | } |
2467 | |
2468 | static int imx_uart_remove(struct platform_device *pdev) |
2469 | { |
2470 | struct imx_port *sport = platform_get_drvdata(pdev); |
2471 | |
2472 | uart_remove_one_port(reg: &imx_uart_uart_driver, port: &sport->port); |
2473 | |
2474 | return 0; |
2475 | } |
2476 | |
2477 | static void imx_uart_restore_context(struct imx_port *sport) |
2478 | { |
2479 | unsigned long flags; |
2480 | |
2481 | uart_port_lock_irqsave(up: &sport->port, flags: &flags); |
2482 | if (!sport->context_saved) { |
2483 | uart_port_unlock_irqrestore(up: &sport->port, flags); |
2484 | return; |
2485 | } |
2486 | |
2487 | imx_uart_writel(sport, val: sport->saved_reg[4], UFCR); |
2488 | imx_uart_writel(sport, val: sport->saved_reg[5], UESC); |
2489 | imx_uart_writel(sport, val: sport->saved_reg[6], UTIM); |
2490 | imx_uart_writel(sport, val: sport->saved_reg[7], UBIR); |
2491 | imx_uart_writel(sport, val: sport->saved_reg[8], UBMR); |
2492 | imx_uart_writel(sport, val: sport->saved_reg[9], IMX21_UTS); |
2493 | imx_uart_writel(sport, val: sport->saved_reg[0], UCR1); |
2494 | imx_uart_writel(sport, val: sport->saved_reg[1] | UCR2_SRST, UCR2); |
2495 | imx_uart_writel(sport, val: sport->saved_reg[2], UCR3); |
2496 | imx_uart_writel(sport, val: sport->saved_reg[3], UCR4); |
2497 | sport->context_saved = false; |
2498 | uart_port_unlock_irqrestore(up: &sport->port, flags); |
2499 | } |
2500 | |
2501 | static void imx_uart_save_context(struct imx_port *sport) |
2502 | { |
2503 | unsigned long flags; |
2504 | |
2505 | /* Save necessary regs */ |
2506 | uart_port_lock_irqsave(up: &sport->port, flags: &flags); |
2507 | sport->saved_reg[0] = imx_uart_readl(sport, UCR1); |
2508 | sport->saved_reg[1] = imx_uart_readl(sport, UCR2); |
2509 | sport->saved_reg[2] = imx_uart_readl(sport, UCR3); |
2510 | sport->saved_reg[3] = imx_uart_readl(sport, UCR4); |
2511 | sport->saved_reg[4] = imx_uart_readl(sport, UFCR); |
2512 | sport->saved_reg[5] = imx_uart_readl(sport, UESC); |
2513 | sport->saved_reg[6] = imx_uart_readl(sport, UTIM); |
2514 | sport->saved_reg[7] = imx_uart_readl(sport, UBIR); |
2515 | sport->saved_reg[8] = imx_uart_readl(sport, UBMR); |
2516 | sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); |
2517 | sport->context_saved = true; |
2518 | uart_port_unlock_irqrestore(up: &sport->port, flags); |
2519 | } |
2520 | |
2521 | static void imx_uart_enable_wakeup(struct imx_port *sport, bool on) |
2522 | { |
2523 | u32 ucr3; |
2524 | |
2525 | ucr3 = imx_uart_readl(sport, UCR3); |
2526 | if (on) { |
2527 | imx_uart_writel(sport, USR1_AWAKE, USR1); |
2528 | ucr3 |= UCR3_AWAKEN; |
2529 | } else { |
2530 | ucr3 &= ~UCR3_AWAKEN; |
2531 | } |
2532 | imx_uart_writel(sport, val: ucr3, UCR3); |
2533 | |
2534 | if (sport->have_rtscts) { |
2535 | u32 ucr1 = imx_uart_readl(sport, UCR1); |
2536 | if (on) { |
2537 | imx_uart_writel(sport, USR1_RTSD, USR1); |
2538 | ucr1 |= UCR1_RTSDEN; |
2539 | } else { |
2540 | ucr1 &= ~UCR1_RTSDEN; |
2541 | } |
2542 | imx_uart_writel(sport, val: ucr1, UCR1); |
2543 | } |
2544 | } |
2545 | |
2546 | static int imx_uart_suspend_noirq(struct device *dev) |
2547 | { |
2548 | struct imx_port *sport = dev_get_drvdata(dev); |
2549 | |
2550 | imx_uart_save_context(sport); |
2551 | |
2552 | clk_disable(clk: sport->clk_ipg); |
2553 | |
2554 | pinctrl_pm_select_sleep_state(dev); |
2555 | |
2556 | return 0; |
2557 | } |
2558 | |
2559 | static int imx_uart_resume_noirq(struct device *dev) |
2560 | { |
2561 | struct imx_port *sport = dev_get_drvdata(dev); |
2562 | int ret; |
2563 | |
2564 | pinctrl_pm_select_default_state(dev); |
2565 | |
2566 | ret = clk_enable(clk: sport->clk_ipg); |
2567 | if (ret) |
2568 | return ret; |
2569 | |
2570 | imx_uart_restore_context(sport); |
2571 | |
2572 | return 0; |
2573 | } |
2574 | |
2575 | static int imx_uart_suspend(struct device *dev) |
2576 | { |
2577 | struct imx_port *sport = dev_get_drvdata(dev); |
2578 | int ret; |
2579 | |
2580 | uart_suspend_port(reg: &imx_uart_uart_driver, port: &sport->port); |
2581 | disable_irq(irq: sport->port.irq); |
2582 | |
2583 | ret = clk_prepare_enable(clk: sport->clk_ipg); |
2584 | if (ret) |
2585 | return ret; |
2586 | |
2587 | /* enable wakeup from i.MX UART */ |
2588 | imx_uart_enable_wakeup(sport, on: true); |
2589 | |
2590 | return 0; |
2591 | } |
2592 | |
2593 | static int imx_uart_resume(struct device *dev) |
2594 | { |
2595 | struct imx_port *sport = dev_get_drvdata(dev); |
2596 | |
2597 | /* disable wakeup from i.MX UART */ |
2598 | imx_uart_enable_wakeup(sport, on: false); |
2599 | |
2600 | uart_resume_port(reg: &imx_uart_uart_driver, port: &sport->port); |
2601 | enable_irq(irq: sport->port.irq); |
2602 | |
2603 | clk_disable_unprepare(clk: sport->clk_ipg); |
2604 | |
2605 | return 0; |
2606 | } |
2607 | |
2608 | static int imx_uart_freeze(struct device *dev) |
2609 | { |
2610 | struct imx_port *sport = dev_get_drvdata(dev); |
2611 | |
2612 | uart_suspend_port(reg: &imx_uart_uart_driver, port: &sport->port); |
2613 | |
2614 | return clk_prepare_enable(clk: sport->clk_ipg); |
2615 | } |
2616 | |
2617 | static int imx_uart_thaw(struct device *dev) |
2618 | { |
2619 | struct imx_port *sport = dev_get_drvdata(dev); |
2620 | |
2621 | uart_resume_port(reg: &imx_uart_uart_driver, port: &sport->port); |
2622 | |
2623 | clk_disable_unprepare(clk: sport->clk_ipg); |
2624 | |
2625 | return 0; |
2626 | } |
2627 | |
2628 | static const struct dev_pm_ops imx_uart_pm_ops = { |
2629 | .suspend_noirq = imx_uart_suspend_noirq, |
2630 | .resume_noirq = imx_uart_resume_noirq, |
2631 | .freeze_noirq = imx_uart_suspend_noirq, |
2632 | .thaw_noirq = imx_uart_resume_noirq, |
2633 | .restore_noirq = imx_uart_resume_noirq, |
2634 | .suspend = imx_uart_suspend, |
2635 | .resume = imx_uart_resume, |
2636 | .freeze = imx_uart_freeze, |
2637 | .thaw = imx_uart_thaw, |
2638 | .restore = imx_uart_thaw, |
2639 | }; |
2640 | |
2641 | static struct platform_driver imx_uart_platform_driver = { |
2642 | .probe = imx_uart_probe, |
2643 | .remove = imx_uart_remove, |
2644 | |
2645 | .driver = { |
2646 | .name = "imx-uart" , |
2647 | .of_match_table = imx_uart_dt_ids, |
2648 | .pm = &imx_uart_pm_ops, |
2649 | }, |
2650 | }; |
2651 | |
2652 | static int __init imx_uart_init(void) |
2653 | { |
2654 | int ret = uart_register_driver(uart: &imx_uart_uart_driver); |
2655 | |
2656 | if (ret) |
2657 | return ret; |
2658 | |
2659 | ret = platform_driver_register(&imx_uart_platform_driver); |
2660 | if (ret != 0) |
2661 | uart_unregister_driver(uart: &imx_uart_uart_driver); |
2662 | |
2663 | return ret; |
2664 | } |
2665 | |
2666 | static void __exit imx_uart_exit(void) |
2667 | { |
2668 | platform_driver_unregister(&imx_uart_platform_driver); |
2669 | uart_unregister_driver(uart: &imx_uart_uart_driver); |
2670 | } |
2671 | |
2672 | module_init(imx_uart_init); |
2673 | module_exit(imx_uart_exit); |
2674 | |
2675 | MODULE_AUTHOR("Sascha Hauer" ); |
2676 | MODULE_DESCRIPTION("IMX generic serial port driver" ); |
2677 | MODULE_LICENSE("GPL" ); |
2678 | MODULE_ALIAS("platform:imx-uart" ); |
2679 | |