1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Driver for Zilog serial chips found on SGI workstations and |
4 | * servers. This driver could actually be made more generic. |
5 | * |
6 | * This is based on the drivers/serial/sunzilog.c code as of 2.6.0-test7 and the |
7 | * old drivers/sgi/char/sgiserial.c code which itself is based of the original |
8 | * drivers/sbus/char/zs.c code. A lot of code has been simply moved over |
9 | * directly from there but much has been rewritten. Credits therefore go out |
10 | * to David S. Miller, Eddie C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell |
11 | * for their work there. |
12 | * |
13 | * Copyright (C) 2002 Ralf Baechle (ralf@linux-mips.org) |
14 | * Copyright (C) 2002 David S. Miller (davem@redhat.com) |
15 | */ |
16 | #include <linux/module.h> |
17 | #include <linux/kernel.h> |
18 | #include <linux/errno.h> |
19 | #include <linux/delay.h> |
20 | #include <linux/tty.h> |
21 | #include <linux/tty_flip.h> |
22 | #include <linux/major.h> |
23 | #include <linux/string.h> |
24 | #include <linux/ptrace.h> |
25 | #include <linux/ioport.h> |
26 | #include <linux/slab.h> |
27 | #include <linux/circ_buf.h> |
28 | #include <linux/serial.h> |
29 | #include <linux/sysrq.h> |
30 | #include <linux/console.h> |
31 | #include <linux/spinlock.h> |
32 | #include <linux/init.h> |
33 | |
34 | #include <linux/io.h> |
35 | #include <asm/irq.h> |
36 | #include <asm/sgialib.h> |
37 | #include <asm/sgi/ioc.h> |
38 | #include <asm/sgi/hpc3.h> |
39 | #include <asm/sgi/ip22.h> |
40 | |
41 | #include <linux/serial_core.h> |
42 | |
43 | #include "ip22zilog.h" |
44 | |
45 | /* |
46 | * On IP22 we need to delay after register accesses but we do not need to |
47 | * flush writes. |
48 | */ |
49 | #define ZSDELAY() udelay(5) |
50 | #define ZSDELAY_LONG() udelay(20) |
51 | #define ZS_WSYNC(channel) do { } while (0) |
52 | |
53 | #define NUM_IP22ZILOG 1 |
54 | #define NUM_CHANNELS (NUM_IP22ZILOG * 2) |
55 | |
56 | #define ZS_CLOCK 3672000 /* Zilog input clock rate. */ |
57 | #define ZS_CLOCK_DIVISOR 16 /* Divisor this driver uses. */ |
58 | |
59 | /* |
60 | * We wrap our port structure around the generic uart_port. |
61 | */ |
62 | struct uart_ip22zilog_port { |
63 | struct uart_port port; |
64 | |
65 | /* IRQ servicing chain. */ |
66 | struct uart_ip22zilog_port *next; |
67 | |
68 | /* Current values of Zilog write registers. */ |
69 | unsigned char curregs[NUM_ZSREGS]; |
70 | |
71 | unsigned int flags; |
72 | #define IP22ZILOG_FLAG_IS_CONS 0x00000004 |
73 | #define IP22ZILOG_FLAG_IS_KGDB 0x00000008 |
74 | #define IP22ZILOG_FLAG_MODEM_STATUS 0x00000010 |
75 | #define IP22ZILOG_FLAG_IS_CHANNEL_A 0x00000020 |
76 | #define IP22ZILOG_FLAG_REGS_HELD 0x00000040 |
77 | #define IP22ZILOG_FLAG_TX_STOPPED 0x00000080 |
78 | #define IP22ZILOG_FLAG_TX_ACTIVE 0x00000100 |
79 | #define IP22ZILOG_FLAG_RESET_DONE 0x00000200 |
80 | |
81 | unsigned int tty_break; |
82 | |
83 | unsigned char parity_mask; |
84 | unsigned char prev_status; |
85 | }; |
86 | |
87 | #define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel *)((PORT)->membase)) |
88 | #define UART_ZILOG(PORT) ((struct uart_ip22zilog_port *)(PORT)) |
89 | #define IP22ZILOG_GET_CURR_REG(PORT, REGNUM) \ |
90 | (UART_ZILOG(PORT)->curregs[REGNUM]) |
91 | #define IP22ZILOG_SET_CURR_REG(PORT, REGNUM, REGVAL) \ |
92 | ((UART_ZILOG(PORT)->curregs[REGNUM]) = (REGVAL)) |
93 | #define ZS_IS_CONS(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CONS) |
94 | #define ZS_IS_KGDB(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_KGDB) |
95 | #define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & IP22ZILOG_FLAG_MODEM_STATUS) |
96 | #define ZS_IS_CHANNEL_A(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CHANNEL_A) |
97 | #define ZS_REGS_HELD(UP) ((UP)->flags & IP22ZILOG_FLAG_REGS_HELD) |
98 | #define ZS_TX_STOPPED(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_STOPPED) |
99 | #define ZS_TX_ACTIVE(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_ACTIVE) |
100 | |
101 | /* Reading and writing Zilog8530 registers. The delays are to make this |
102 | * driver work on the IP22 which needs a settling delay after each chip |
103 | * register access, other machines handle this in hardware via auxiliary |
104 | * flip-flops which implement the settle time we do in software. |
105 | * |
106 | * The port lock must be held and local IRQs must be disabled |
107 | * when {read,write}_zsreg is invoked. |
108 | */ |
109 | static unsigned char read_zsreg(struct zilog_channel *channel, |
110 | unsigned char reg) |
111 | { |
112 | unsigned char retval; |
113 | |
114 | writeb(val: reg, addr: &channel->control); |
115 | ZSDELAY(); |
116 | retval = readb(addr: &channel->control); |
117 | ZSDELAY(); |
118 | |
119 | return retval; |
120 | } |
121 | |
122 | static void write_zsreg(struct zilog_channel *channel, |
123 | unsigned char reg, unsigned char value) |
124 | { |
125 | writeb(val: reg, addr: &channel->control); |
126 | ZSDELAY(); |
127 | writeb(val: value, addr: &channel->control); |
128 | ZSDELAY(); |
129 | } |
130 | |
131 | static void ip22zilog_clear_fifo(struct zilog_channel *channel) |
132 | { |
133 | int i; |
134 | |
135 | for (i = 0; i < 32; i++) { |
136 | unsigned char regval; |
137 | |
138 | regval = readb(addr: &channel->control); |
139 | ZSDELAY(); |
140 | if (regval & Rx_CH_AV) |
141 | break; |
142 | |
143 | regval = read_zsreg(channel, R1); |
144 | readb(addr: &channel->data); |
145 | ZSDELAY(); |
146 | |
147 | if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) { |
148 | writeb(ERR_RES, addr: &channel->control); |
149 | ZSDELAY(); |
150 | ZS_WSYNC(channel); |
151 | } |
152 | } |
153 | } |
154 | |
155 | /* This function must only be called when the TX is not busy. The UART |
156 | * port lock must be held and local interrupts disabled. |
157 | */ |
158 | static void __load_zsregs(struct zilog_channel *channel, unsigned char *regs) |
159 | { |
160 | int i; |
161 | |
162 | /* Let pending transmits finish. */ |
163 | for (i = 0; i < 1000; i++) { |
164 | unsigned char stat = read_zsreg(channel, R1); |
165 | if (stat & ALL_SNT) |
166 | break; |
167 | udelay(100); |
168 | } |
169 | |
170 | writeb(ERR_RES, addr: &channel->control); |
171 | ZSDELAY(); |
172 | ZS_WSYNC(channel); |
173 | |
174 | ip22zilog_clear_fifo(channel); |
175 | |
176 | /* Disable all interrupts. */ |
177 | write_zsreg(channel, R1, |
178 | value: regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB)); |
179 | |
180 | /* Set parity, sync config, stop bits, and clock divisor. */ |
181 | write_zsreg(channel, R4, value: regs[R4]); |
182 | |
183 | /* Set misc. TX/RX control bits. */ |
184 | write_zsreg(channel, R10, value: regs[R10]); |
185 | |
186 | /* Set TX/RX controls sans the enable bits. */ |
187 | write_zsreg(channel, R3, value: regs[R3] & ~RxENAB); |
188 | write_zsreg(channel, R5, value: regs[R5] & ~TxENAB); |
189 | |
190 | /* Synchronous mode config. */ |
191 | write_zsreg(channel, R6, value: regs[R6]); |
192 | write_zsreg(channel, R7, value: regs[R7]); |
193 | |
194 | /* Don't mess with the interrupt vector (R2, unused by us) and |
195 | * master interrupt control (R9). We make sure this is setup |
196 | * properly at probe time then never touch it again. |
197 | */ |
198 | |
199 | /* Disable baud generator. */ |
200 | write_zsreg(channel, R14, value: regs[R14] & ~BRENAB); |
201 | |
202 | /* Clock mode control. */ |
203 | write_zsreg(channel, R11, value: regs[R11]); |
204 | |
205 | /* Lower and upper byte of baud rate generator divisor. */ |
206 | write_zsreg(channel, R12, value: regs[R12]); |
207 | write_zsreg(channel, R13, value: regs[R13]); |
208 | |
209 | /* Now rewrite R14, with BRENAB (if set). */ |
210 | write_zsreg(channel, R14, value: regs[R14]); |
211 | |
212 | /* External status interrupt control. */ |
213 | write_zsreg(channel, R15, value: regs[R15]); |
214 | |
215 | /* Reset external status interrupts. */ |
216 | write_zsreg(channel, R0, RES_EXT_INT); |
217 | write_zsreg(channel, R0, RES_EXT_INT); |
218 | |
219 | /* Rewrite R3/R5, this time without enables masked. */ |
220 | write_zsreg(channel, R3, value: regs[R3]); |
221 | write_zsreg(channel, R5, value: regs[R5]); |
222 | |
223 | /* Rewrite R1, this time without IRQ enabled masked. */ |
224 | write_zsreg(channel, R1, value: regs[R1]); |
225 | } |
226 | |
227 | /* Reprogram the Zilog channel HW registers with the copies found in the |
228 | * software state struct. If the transmitter is busy, we defer this update |
229 | * until the next TX complete interrupt. Else, we do it right now. |
230 | * |
231 | * The UART port lock must be held and local interrupts disabled. |
232 | */ |
233 | static void ip22zilog_maybe_update_regs(struct uart_ip22zilog_port *up, |
234 | struct zilog_channel *channel) |
235 | { |
236 | if (!ZS_REGS_HELD(up)) { |
237 | if (ZS_TX_ACTIVE(up)) { |
238 | up->flags |= IP22ZILOG_FLAG_REGS_HELD; |
239 | } else { |
240 | __load_zsregs(channel, regs: up->curregs); |
241 | } |
242 | } |
243 | } |
244 | |
245 | #define Rx_BRK 0x0100 /* BREAK event software flag. */ |
246 | #define Rx_SYS 0x0200 /* SysRq event software flag. */ |
247 | |
248 | static bool ip22zilog_receive_chars(struct uart_ip22zilog_port *up, |
249 | struct zilog_channel *channel) |
250 | { |
251 | unsigned int r1; |
252 | u8 ch, flag; |
253 | bool push = up->port.state != NULL; |
254 | |
255 | for (;;) { |
256 | ch = readb(addr: &channel->control); |
257 | ZSDELAY(); |
258 | if (!(ch & Rx_CH_AV)) |
259 | break; |
260 | |
261 | r1 = read_zsreg(channel, R1); |
262 | if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) { |
263 | writeb(ERR_RES, addr: &channel->control); |
264 | ZSDELAY(); |
265 | ZS_WSYNC(channel); |
266 | } |
267 | |
268 | ch = readb(addr: &channel->data); |
269 | ZSDELAY(); |
270 | |
271 | ch &= up->parity_mask; |
272 | |
273 | /* Handle the null char got when BREAK is removed. */ |
274 | if (!ch) |
275 | r1 |= up->tty_break; |
276 | |
277 | /* A real serial line, record the character and status. */ |
278 | flag = TTY_NORMAL; |
279 | up->port.icount.rx++; |
280 | if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | Rx_SYS | Rx_BRK)) { |
281 | up->tty_break = 0; |
282 | |
283 | if (r1 & (Rx_SYS | Rx_BRK)) { |
284 | up->port.icount.brk++; |
285 | if (r1 & Rx_SYS) |
286 | continue; |
287 | r1 &= ~(PAR_ERR | CRC_ERR); |
288 | } |
289 | else if (r1 & PAR_ERR) |
290 | up->port.icount.parity++; |
291 | else if (r1 & CRC_ERR) |
292 | up->port.icount.frame++; |
293 | if (r1 & Rx_OVR) |
294 | up->port.icount.overrun++; |
295 | r1 &= up->port.read_status_mask; |
296 | if (r1 & Rx_BRK) |
297 | flag = TTY_BREAK; |
298 | else if (r1 & PAR_ERR) |
299 | flag = TTY_PARITY; |
300 | else if (r1 & CRC_ERR) |
301 | flag = TTY_FRAME; |
302 | } |
303 | |
304 | if (uart_handle_sysrq_char(port: &up->port, ch)) |
305 | continue; |
306 | |
307 | if (push) |
308 | uart_insert_char(port: &up->port, status: r1, Rx_OVR, ch, flag); |
309 | } |
310 | return push; |
311 | } |
312 | |
313 | static void ip22zilog_status_handle(struct uart_ip22zilog_port *up, |
314 | struct zilog_channel *channel) |
315 | { |
316 | unsigned char status; |
317 | |
318 | status = readb(addr: &channel->control); |
319 | ZSDELAY(); |
320 | |
321 | writeb(RES_EXT_INT, addr: &channel->control); |
322 | ZSDELAY(); |
323 | ZS_WSYNC(channel); |
324 | |
325 | if (up->curregs[R15] & BRKIE) { |
326 | if ((status & BRK_ABRT) && !(up->prev_status & BRK_ABRT)) { |
327 | if (uart_handle_break(port: &up->port)) |
328 | up->tty_break = Rx_SYS; |
329 | else |
330 | up->tty_break = Rx_BRK; |
331 | } |
332 | } |
333 | |
334 | if (ZS_WANTS_MODEM_STATUS(up)) { |
335 | if (status & SYNC) |
336 | up->port.icount.dsr++; |
337 | |
338 | /* The Zilog just gives us an interrupt when DCD/CTS/etc. change. |
339 | * But it does not tell us which bit has changed, we have to keep |
340 | * track of this ourselves. |
341 | */ |
342 | if ((status ^ up->prev_status) ^ DCD) |
343 | uart_handle_dcd_change(uport: &up->port, |
344 | active: (status & DCD)); |
345 | if ((status ^ up->prev_status) ^ CTS) |
346 | uart_handle_cts_change(uport: &up->port, |
347 | active: (status & CTS)); |
348 | |
349 | wake_up_interruptible(&up->port.state->port.delta_msr_wait); |
350 | } |
351 | |
352 | up->prev_status = status; |
353 | } |
354 | |
355 | static void ip22zilog_transmit_chars(struct uart_ip22zilog_port *up, |
356 | struct zilog_channel *channel) |
357 | { |
358 | struct circ_buf *xmit; |
359 | |
360 | if (ZS_IS_CONS(up)) { |
361 | unsigned char status = readb(addr: &channel->control); |
362 | ZSDELAY(); |
363 | |
364 | /* TX still busy? Just wait for the next TX done interrupt. |
365 | * |
366 | * It can occur because of how we do serial console writes. It would |
367 | * be nice to transmit console writes just like we normally would for |
368 | * a TTY line. (ie. buffered and TX interrupt driven). That is not |
369 | * easy because console writes cannot sleep. One solution might be |
370 | * to poll on enough port->xmit space becoming free. -DaveM |
371 | */ |
372 | if (!(status & Tx_BUF_EMP)) |
373 | return; |
374 | } |
375 | |
376 | up->flags &= ~IP22ZILOG_FLAG_TX_ACTIVE; |
377 | |
378 | if (ZS_REGS_HELD(up)) { |
379 | __load_zsregs(channel, regs: up->curregs); |
380 | up->flags &= ~IP22ZILOG_FLAG_REGS_HELD; |
381 | } |
382 | |
383 | if (ZS_TX_STOPPED(up)) { |
384 | up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED; |
385 | goto ack_tx_int; |
386 | } |
387 | |
388 | if (up->port.x_char) { |
389 | up->flags |= IP22ZILOG_FLAG_TX_ACTIVE; |
390 | writeb(val: up->port.x_char, addr: &channel->data); |
391 | ZSDELAY(); |
392 | ZS_WSYNC(channel); |
393 | |
394 | up->port.icount.tx++; |
395 | up->port.x_char = 0; |
396 | return; |
397 | } |
398 | |
399 | if (up->port.state == NULL) |
400 | goto ack_tx_int; |
401 | xmit = &up->port.state->xmit; |
402 | if (uart_circ_empty(xmit)) |
403 | goto ack_tx_int; |
404 | if (uart_tx_stopped(port: &up->port)) |
405 | goto ack_tx_int; |
406 | |
407 | up->flags |= IP22ZILOG_FLAG_TX_ACTIVE; |
408 | writeb(val: xmit->buf[xmit->tail], addr: &channel->data); |
409 | ZSDELAY(); |
410 | ZS_WSYNC(channel); |
411 | |
412 | uart_xmit_advance(up: &up->port, chars: 1); |
413 | |
414 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
415 | uart_write_wakeup(port: &up->port); |
416 | |
417 | return; |
418 | |
419 | ack_tx_int: |
420 | writeb(RES_Tx_P, addr: &channel->control); |
421 | ZSDELAY(); |
422 | ZS_WSYNC(channel); |
423 | } |
424 | |
425 | static irqreturn_t ip22zilog_interrupt(int irq, void *dev_id) |
426 | { |
427 | struct uart_ip22zilog_port *up = dev_id; |
428 | |
429 | while (up) { |
430 | struct zilog_channel *channel |
431 | = ZILOG_CHANNEL_FROM_PORT(&up->port); |
432 | unsigned char r3; |
433 | bool push = false; |
434 | |
435 | uart_port_lock(up: &up->port); |
436 | r3 = read_zsreg(channel, R3); |
437 | |
438 | /* Channel A */ |
439 | if (r3 & (CHAEXT | CHATxIP | CHARxIP)) { |
440 | writeb(RES_H_IUS, addr: &channel->control); |
441 | ZSDELAY(); |
442 | ZS_WSYNC(channel); |
443 | |
444 | if (r3 & CHARxIP) |
445 | push = ip22zilog_receive_chars(up, channel); |
446 | if (r3 & CHAEXT) |
447 | ip22zilog_status_handle(up, channel); |
448 | if (r3 & CHATxIP) |
449 | ip22zilog_transmit_chars(up, channel); |
450 | } |
451 | uart_port_unlock(up: &up->port); |
452 | |
453 | if (push) |
454 | tty_flip_buffer_push(port: &up->port.state->port); |
455 | |
456 | /* Channel B */ |
457 | up = up->next; |
458 | channel = ZILOG_CHANNEL_FROM_PORT(&up->port); |
459 | push = false; |
460 | |
461 | uart_port_lock(up: &up->port); |
462 | if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) { |
463 | writeb(RES_H_IUS, addr: &channel->control); |
464 | ZSDELAY(); |
465 | ZS_WSYNC(channel); |
466 | |
467 | if (r3 & CHBRxIP) |
468 | push = ip22zilog_receive_chars(up, channel); |
469 | if (r3 & CHBEXT) |
470 | ip22zilog_status_handle(up, channel); |
471 | if (r3 & CHBTxIP) |
472 | ip22zilog_transmit_chars(up, channel); |
473 | } |
474 | uart_port_unlock(up: &up->port); |
475 | |
476 | if (push) |
477 | tty_flip_buffer_push(port: &up->port.state->port); |
478 | |
479 | up = up->next; |
480 | } |
481 | |
482 | return IRQ_HANDLED; |
483 | } |
484 | |
485 | /* A convenient way to quickly get R0 status. The caller must _not_ hold the |
486 | * port lock, it is acquired here. |
487 | */ |
488 | static __inline__ unsigned char ip22zilog_read_channel_status(struct uart_port *port) |
489 | { |
490 | struct zilog_channel *channel; |
491 | unsigned char status; |
492 | |
493 | channel = ZILOG_CHANNEL_FROM_PORT(port); |
494 | status = readb(addr: &channel->control); |
495 | ZSDELAY(); |
496 | |
497 | return status; |
498 | } |
499 | |
500 | /* The port lock is not held. */ |
501 | static unsigned int ip22zilog_tx_empty(struct uart_port *port) |
502 | { |
503 | unsigned long flags; |
504 | unsigned char status; |
505 | unsigned int ret; |
506 | |
507 | uart_port_lock_irqsave(up: port, flags: &flags); |
508 | |
509 | status = ip22zilog_read_channel_status(port); |
510 | |
511 | uart_port_unlock_irqrestore(up: port, flags); |
512 | |
513 | if (status & Tx_BUF_EMP) |
514 | ret = TIOCSER_TEMT; |
515 | else |
516 | ret = 0; |
517 | |
518 | return ret; |
519 | } |
520 | |
521 | /* The port lock is held and interrupts are disabled. */ |
522 | static unsigned int ip22zilog_get_mctrl(struct uart_port *port) |
523 | { |
524 | unsigned char status; |
525 | unsigned int ret; |
526 | |
527 | status = ip22zilog_read_channel_status(port); |
528 | |
529 | ret = 0; |
530 | if (status & DCD) |
531 | ret |= TIOCM_CAR; |
532 | if (status & SYNC) |
533 | ret |= TIOCM_DSR; |
534 | if (status & CTS) |
535 | ret |= TIOCM_CTS; |
536 | |
537 | return ret; |
538 | } |
539 | |
540 | /* The port lock is held and interrupts are disabled. */ |
541 | static void ip22zilog_set_mctrl(struct uart_port *port, unsigned int mctrl) |
542 | { |
543 | struct uart_ip22zilog_port *up = |
544 | container_of(port, struct uart_ip22zilog_port, port); |
545 | struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); |
546 | unsigned char set_bits, clear_bits; |
547 | |
548 | set_bits = clear_bits = 0; |
549 | |
550 | if (mctrl & TIOCM_RTS) |
551 | set_bits |= RTS; |
552 | else |
553 | clear_bits |= RTS; |
554 | if (mctrl & TIOCM_DTR) |
555 | set_bits |= DTR; |
556 | else |
557 | clear_bits |= DTR; |
558 | |
559 | /* NOTE: Not subject to 'transmitter active' rule. */ |
560 | up->curregs[R5] |= set_bits; |
561 | up->curregs[R5] &= ~clear_bits; |
562 | write_zsreg(channel, R5, value: up->curregs[R5]); |
563 | } |
564 | |
565 | /* The port lock is held and interrupts are disabled. */ |
566 | static void ip22zilog_stop_tx(struct uart_port *port) |
567 | { |
568 | struct uart_ip22zilog_port *up = |
569 | container_of(port, struct uart_ip22zilog_port, port); |
570 | |
571 | up->flags |= IP22ZILOG_FLAG_TX_STOPPED; |
572 | } |
573 | |
574 | /* The port lock is held and interrupts are disabled. */ |
575 | static void ip22zilog_start_tx(struct uart_port *port) |
576 | { |
577 | struct uart_ip22zilog_port *up = |
578 | container_of(port, struct uart_ip22zilog_port, port); |
579 | struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); |
580 | unsigned char status; |
581 | |
582 | up->flags |= IP22ZILOG_FLAG_TX_ACTIVE; |
583 | up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED; |
584 | |
585 | status = readb(addr: &channel->control); |
586 | ZSDELAY(); |
587 | |
588 | /* TX busy? Just wait for the TX done interrupt. */ |
589 | if (!(status & Tx_BUF_EMP)) |
590 | return; |
591 | |
592 | /* Send the first character to jump-start the TX done |
593 | * IRQ sending engine. |
594 | */ |
595 | if (port->x_char) { |
596 | writeb(val: port->x_char, addr: &channel->data); |
597 | ZSDELAY(); |
598 | ZS_WSYNC(channel); |
599 | |
600 | port->icount.tx++; |
601 | port->x_char = 0; |
602 | } else { |
603 | struct circ_buf *xmit = &port->state->xmit; |
604 | |
605 | if (uart_circ_empty(xmit)) |
606 | return; |
607 | writeb(val: xmit->buf[xmit->tail], addr: &channel->data); |
608 | ZSDELAY(); |
609 | ZS_WSYNC(channel); |
610 | |
611 | uart_xmit_advance(up: port, chars: 1); |
612 | |
613 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
614 | uart_write_wakeup(port: &up->port); |
615 | } |
616 | } |
617 | |
618 | /* The port lock is held and interrupts are disabled. */ |
619 | static void ip22zilog_stop_rx(struct uart_port *port) |
620 | { |
621 | struct uart_ip22zilog_port *up = UART_ZILOG(port); |
622 | struct zilog_channel *channel; |
623 | |
624 | if (ZS_IS_CONS(up)) |
625 | return; |
626 | |
627 | channel = ZILOG_CHANNEL_FROM_PORT(port); |
628 | |
629 | /* Disable all RX interrupts. */ |
630 | up->curregs[R1] &= ~RxINT_MASK; |
631 | ip22zilog_maybe_update_regs(up, channel); |
632 | } |
633 | |
634 | /* The port lock is held. */ |
635 | static void ip22zilog_enable_ms(struct uart_port *port) |
636 | { |
637 | struct uart_ip22zilog_port *up = |
638 | container_of(port, struct uart_ip22zilog_port, port); |
639 | struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); |
640 | unsigned char new_reg; |
641 | |
642 | new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE); |
643 | if (new_reg != up->curregs[R15]) { |
644 | up->curregs[R15] = new_reg; |
645 | |
646 | /* NOTE: Not subject to 'transmitter active' rule. */ |
647 | write_zsreg(channel, R15, value: up->curregs[R15]); |
648 | } |
649 | } |
650 | |
651 | /* The port lock is not held. */ |
652 | static void ip22zilog_break_ctl(struct uart_port *port, int break_state) |
653 | { |
654 | struct uart_ip22zilog_port *up = |
655 | container_of(port, struct uart_ip22zilog_port, port); |
656 | struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); |
657 | unsigned char set_bits, clear_bits, new_reg; |
658 | unsigned long flags; |
659 | |
660 | set_bits = clear_bits = 0; |
661 | |
662 | if (break_state) |
663 | set_bits |= SND_BRK; |
664 | else |
665 | clear_bits |= SND_BRK; |
666 | |
667 | uart_port_lock_irqsave(up: port, flags: &flags); |
668 | |
669 | new_reg = (up->curregs[R5] | set_bits) & ~clear_bits; |
670 | if (new_reg != up->curregs[R5]) { |
671 | up->curregs[R5] = new_reg; |
672 | |
673 | /* NOTE: Not subject to 'transmitter active' rule. */ |
674 | write_zsreg(channel, R5, value: up->curregs[R5]); |
675 | } |
676 | |
677 | uart_port_unlock_irqrestore(up: port, flags); |
678 | } |
679 | |
680 | static void __ip22zilog_reset(struct uart_ip22zilog_port *up) |
681 | { |
682 | struct zilog_channel *channel; |
683 | int i; |
684 | |
685 | if (up->flags & IP22ZILOG_FLAG_RESET_DONE) |
686 | return; |
687 | |
688 | /* Let pending transmits finish. */ |
689 | channel = ZILOG_CHANNEL_FROM_PORT(&up->port); |
690 | for (i = 0; i < 1000; i++) { |
691 | unsigned char stat = read_zsreg(channel, R1); |
692 | if (stat & ALL_SNT) |
693 | break; |
694 | udelay(100); |
695 | } |
696 | |
697 | if (!ZS_IS_CHANNEL_A(up)) { |
698 | up++; |
699 | channel = ZILOG_CHANNEL_FROM_PORT(&up->port); |
700 | } |
701 | write_zsreg(channel, R9, FHWRES); |
702 | ZSDELAY_LONG(); |
703 | (void) read_zsreg(channel, R0); |
704 | |
705 | up->flags |= IP22ZILOG_FLAG_RESET_DONE; |
706 | up->next->flags |= IP22ZILOG_FLAG_RESET_DONE; |
707 | } |
708 | |
709 | static void __ip22zilog_startup(struct uart_ip22zilog_port *up) |
710 | { |
711 | struct zilog_channel *channel; |
712 | |
713 | channel = ZILOG_CHANNEL_FROM_PORT(&up->port); |
714 | |
715 | __ip22zilog_reset(up); |
716 | |
717 | __load_zsregs(channel, regs: up->curregs); |
718 | /* set master interrupt enable */ |
719 | write_zsreg(channel, R9, value: up->curregs[R9]); |
720 | up->prev_status = readb(addr: &channel->control); |
721 | |
722 | /* Enable receiver and transmitter. */ |
723 | up->curregs[R3] |= RxENAB; |
724 | up->curregs[R5] |= TxENAB; |
725 | |
726 | up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; |
727 | ip22zilog_maybe_update_regs(up, channel); |
728 | } |
729 | |
730 | static int ip22zilog_startup(struct uart_port *port) |
731 | { |
732 | struct uart_ip22zilog_port *up = UART_ZILOG(port); |
733 | unsigned long flags; |
734 | |
735 | if (ZS_IS_CONS(up)) |
736 | return 0; |
737 | |
738 | uart_port_lock_irqsave(up: port, flags: &flags); |
739 | __ip22zilog_startup(up); |
740 | uart_port_unlock_irqrestore(up: port, flags); |
741 | return 0; |
742 | } |
743 | |
744 | /* |
745 | * The test for ZS_IS_CONS is explained by the following e-mail: |
746 | ***** |
747 | * From: Russell King <rmk@arm.linux.org.uk> |
748 | * Date: Sun, 8 Dec 2002 10:18:38 +0000 |
749 | * |
750 | * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote: |
751 | * > I boot my 2.5 boxes using "console=ttyS0,9600" argument, |
752 | * > and I noticed that something is not right with reference |
753 | * > counting in this case. It seems that when the console |
754 | * > is open by kernel initially, this is not accounted |
755 | * > as an open, and uart_startup is not called. |
756 | * |
757 | * That is correct. We are unable to call uart_startup when the serial |
758 | * console is initialised because it may need to allocate memory (as |
759 | * request_irq does) and the memory allocators may not have been |
760 | * initialised. |
761 | * |
762 | * 1. initialise the port into a state where it can send characters in the |
763 | * console write method. |
764 | * |
765 | * 2. don't do the actual hardware shutdown in your shutdown() method (but |
766 | * do the normal software shutdown - ie, free irqs etc) |
767 | ***** |
768 | */ |
769 | static void ip22zilog_shutdown(struct uart_port *port) |
770 | { |
771 | struct uart_ip22zilog_port *up = UART_ZILOG(port); |
772 | struct zilog_channel *channel; |
773 | unsigned long flags; |
774 | |
775 | if (ZS_IS_CONS(up)) |
776 | return; |
777 | |
778 | uart_port_lock_irqsave(up: port, flags: &flags); |
779 | |
780 | channel = ZILOG_CHANNEL_FROM_PORT(port); |
781 | |
782 | /* Disable receiver and transmitter. */ |
783 | up->curregs[R3] &= ~RxENAB; |
784 | up->curregs[R5] &= ~TxENAB; |
785 | |
786 | /* Disable all interrupts and BRK assertion. */ |
787 | up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); |
788 | up->curregs[R5] &= ~SND_BRK; |
789 | ip22zilog_maybe_update_regs(up, channel); |
790 | |
791 | uart_port_unlock_irqrestore(up: port, flags); |
792 | } |
793 | |
794 | /* Shared by TTY driver and serial console setup. The port lock is held |
795 | * and local interrupts are disabled. |
796 | */ |
797 | static void |
798 | ip22zilog_convert_to_zs(struct uart_ip22zilog_port *up, unsigned int cflag, |
799 | unsigned int iflag, int brg) |
800 | { |
801 | |
802 | up->curregs[R10] = NRZ; |
803 | up->curregs[R11] = TCBR | RCBR; |
804 | |
805 | /* Program BAUD and clock source. */ |
806 | up->curregs[R4] &= ~XCLK_MASK; |
807 | up->curregs[R4] |= X16CLK; |
808 | up->curregs[R12] = brg & 0xff; |
809 | up->curregs[R13] = (brg >> 8) & 0xff; |
810 | up->curregs[R14] = BRENAB; |
811 | |
812 | /* Character size, stop bits, and parity. */ |
813 | up->curregs[3] &= ~RxN_MASK; |
814 | up->curregs[5] &= ~TxN_MASK; |
815 | switch (cflag & CSIZE) { |
816 | case CS5: |
817 | up->curregs[3] |= Rx5; |
818 | up->curregs[5] |= Tx5; |
819 | up->parity_mask = 0x1f; |
820 | break; |
821 | case CS6: |
822 | up->curregs[3] |= Rx6; |
823 | up->curregs[5] |= Tx6; |
824 | up->parity_mask = 0x3f; |
825 | break; |
826 | case CS7: |
827 | up->curregs[3] |= Rx7; |
828 | up->curregs[5] |= Tx7; |
829 | up->parity_mask = 0x7f; |
830 | break; |
831 | case CS8: |
832 | default: |
833 | up->curregs[3] |= Rx8; |
834 | up->curregs[5] |= Tx8; |
835 | up->parity_mask = 0xff; |
836 | break; |
837 | } |
838 | up->curregs[4] &= ~0x0c; |
839 | if (cflag & CSTOPB) |
840 | up->curregs[4] |= SB2; |
841 | else |
842 | up->curregs[4] |= SB1; |
843 | if (cflag & PARENB) |
844 | up->curregs[4] |= PAR_ENAB; |
845 | else |
846 | up->curregs[4] &= ~PAR_ENAB; |
847 | if (!(cflag & PARODD)) |
848 | up->curregs[4] |= PAR_EVEN; |
849 | else |
850 | up->curregs[4] &= ~PAR_EVEN; |
851 | |
852 | up->port.read_status_mask = Rx_OVR; |
853 | if (iflag & INPCK) |
854 | up->port.read_status_mask |= CRC_ERR | PAR_ERR; |
855 | if (iflag & (IGNBRK | BRKINT | PARMRK)) |
856 | up->port.read_status_mask |= BRK_ABRT; |
857 | |
858 | up->port.ignore_status_mask = 0; |
859 | if (iflag & IGNPAR) |
860 | up->port.ignore_status_mask |= CRC_ERR | PAR_ERR; |
861 | if (iflag & IGNBRK) { |
862 | up->port.ignore_status_mask |= BRK_ABRT; |
863 | if (iflag & IGNPAR) |
864 | up->port.ignore_status_mask |= Rx_OVR; |
865 | } |
866 | |
867 | if ((cflag & CREAD) == 0) |
868 | up->port.ignore_status_mask = 0xff; |
869 | } |
870 | |
871 | /* The port lock is not held. */ |
872 | static void |
873 | ip22zilog_set_termios(struct uart_port *port, struct ktermios *termios, |
874 | const struct ktermios *old) |
875 | { |
876 | struct uart_ip22zilog_port *up = |
877 | container_of(port, struct uart_ip22zilog_port, port); |
878 | unsigned long flags; |
879 | int baud, brg; |
880 | |
881 | baud = uart_get_baud_rate(port, termios, old, min: 1200, max: 76800); |
882 | |
883 | uart_port_lock_irqsave(up: &up->port, flags: &flags); |
884 | |
885 | brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR); |
886 | |
887 | ip22zilog_convert_to_zs(up, cflag: termios->c_cflag, iflag: termios->c_iflag, brg); |
888 | |
889 | if (UART_ENABLE_MS(&up->port, termios->c_cflag)) |
890 | up->flags |= IP22ZILOG_FLAG_MODEM_STATUS; |
891 | else |
892 | up->flags &= ~IP22ZILOG_FLAG_MODEM_STATUS; |
893 | |
894 | ip22zilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port)); |
895 | uart_update_timeout(port, cflag: termios->c_cflag, baud); |
896 | |
897 | uart_port_unlock_irqrestore(up: &up->port, flags); |
898 | } |
899 | |
900 | static const char *ip22zilog_type(struct uart_port *port) |
901 | { |
902 | return "IP22-Zilog" ; |
903 | } |
904 | |
905 | /* We do not request/release mappings of the registers here, this |
906 | * happens at early serial probe time. |
907 | */ |
908 | static void ip22zilog_release_port(struct uart_port *port) |
909 | { |
910 | } |
911 | |
912 | static int ip22zilog_request_port(struct uart_port *port) |
913 | { |
914 | return 0; |
915 | } |
916 | |
917 | /* These do not need to do anything interesting either. */ |
918 | static void ip22zilog_config_port(struct uart_port *port, int flags) |
919 | { |
920 | } |
921 | |
922 | /* We do not support letting the user mess with the divisor, IRQ, etc. */ |
923 | static int ip22zilog_verify_port(struct uart_port *port, struct serial_struct *ser) |
924 | { |
925 | return -EINVAL; |
926 | } |
927 | |
928 | static const struct uart_ops ip22zilog_pops = { |
929 | .tx_empty = ip22zilog_tx_empty, |
930 | .set_mctrl = ip22zilog_set_mctrl, |
931 | .get_mctrl = ip22zilog_get_mctrl, |
932 | .stop_tx = ip22zilog_stop_tx, |
933 | .start_tx = ip22zilog_start_tx, |
934 | .stop_rx = ip22zilog_stop_rx, |
935 | .enable_ms = ip22zilog_enable_ms, |
936 | .break_ctl = ip22zilog_break_ctl, |
937 | .startup = ip22zilog_startup, |
938 | .shutdown = ip22zilog_shutdown, |
939 | .set_termios = ip22zilog_set_termios, |
940 | .type = ip22zilog_type, |
941 | .release_port = ip22zilog_release_port, |
942 | .request_port = ip22zilog_request_port, |
943 | .config_port = ip22zilog_config_port, |
944 | .verify_port = ip22zilog_verify_port, |
945 | }; |
946 | |
947 | static struct uart_ip22zilog_port *ip22zilog_port_table; |
948 | static struct zilog_layout **ip22zilog_chip_regs; |
949 | |
950 | static struct uart_ip22zilog_port *ip22zilog_irq_chain; |
951 | static int zilog_irq = -1; |
952 | |
953 | static void * __init alloc_one_table(unsigned long size) |
954 | { |
955 | return kzalloc(size, GFP_KERNEL); |
956 | } |
957 | |
958 | static void __init ip22zilog_alloc_tables(void) |
959 | { |
960 | ip22zilog_port_table = (struct uart_ip22zilog_port *) |
961 | alloc_one_table(NUM_CHANNELS * sizeof(struct uart_ip22zilog_port)); |
962 | ip22zilog_chip_regs = (struct zilog_layout **) |
963 | alloc_one_table(NUM_IP22ZILOG * sizeof(struct zilog_layout *)); |
964 | |
965 | if (ip22zilog_port_table == NULL || ip22zilog_chip_regs == NULL) { |
966 | panic(fmt: "IP22-Zilog: Cannot allocate IP22-Zilog tables." ); |
967 | } |
968 | } |
969 | |
970 | /* Get the address of the registers for IP22-Zilog instance CHIP. */ |
971 | static struct zilog_layout * __init get_zs(int chip) |
972 | { |
973 | unsigned long base; |
974 | |
975 | if (chip < 0 || chip >= NUM_IP22ZILOG) { |
976 | panic(fmt: "IP22-Zilog: Illegal chip number %d in get_zs." , chip); |
977 | } |
978 | |
979 | /* Not probe-able, hard code it. */ |
980 | base = (unsigned long) &sgioc->uart; |
981 | |
982 | zilog_irq = SGI_SERIAL_IRQ; |
983 | request_mem_region(base, 8, "IP22-Zilog" ); |
984 | |
985 | return (struct zilog_layout *) base; |
986 | } |
987 | |
988 | #define ZS_PUT_CHAR_MAX_DELAY 2000 /* 10 ms */ |
989 | |
990 | #ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE |
991 | static void ip22zilog_put_char(struct uart_port *port, unsigned char ch) |
992 | { |
993 | struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); |
994 | int loops = ZS_PUT_CHAR_MAX_DELAY; |
995 | |
996 | /* This is a timed polling loop so do not switch the explicit |
997 | * udelay with ZSDELAY as that is a NOP on some platforms. -DaveM |
998 | */ |
999 | do { |
1000 | unsigned char val = readb(&channel->control); |
1001 | if (val & Tx_BUF_EMP) { |
1002 | ZSDELAY(); |
1003 | break; |
1004 | } |
1005 | udelay(5); |
1006 | } while (--loops); |
1007 | |
1008 | writeb(ch, &channel->data); |
1009 | ZSDELAY(); |
1010 | ZS_WSYNC(channel); |
1011 | } |
1012 | |
1013 | static void |
1014 | ip22zilog_console_write(struct console *con, const char *s, unsigned int count) |
1015 | { |
1016 | struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index]; |
1017 | unsigned long flags; |
1018 | |
1019 | uart_port_lock_irqsave(&up->port, &flags); |
1020 | uart_console_write(&up->port, s, count, ip22zilog_put_char); |
1021 | udelay(2); |
1022 | uart_port_unlock_irqrestore(&up->port, flags); |
1023 | } |
1024 | |
1025 | static int __init ip22zilog_console_setup(struct console *con, char *options) |
1026 | { |
1027 | struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index]; |
1028 | unsigned long flags; |
1029 | int baud = 9600, bits = 8; |
1030 | int parity = 'n'; |
1031 | int flow = 'n'; |
1032 | |
1033 | up->flags |= IP22ZILOG_FLAG_IS_CONS; |
1034 | |
1035 | printk(KERN_INFO "Console: ttyS%d (IP22-Zilog)\n" , con->index); |
1036 | |
1037 | uart_port_lock_irqsave(&up->port, &flags); |
1038 | |
1039 | up->curregs[R15] |= BRKIE; |
1040 | |
1041 | __ip22zilog_startup(up); |
1042 | |
1043 | uart_port_unlock_irqrestore(&up->port, flags); |
1044 | |
1045 | if (options) |
1046 | uart_parse_options(options, &baud, &parity, &bits, &flow); |
1047 | return uart_set_options(&up->port, con, baud, parity, bits, flow); |
1048 | } |
1049 | |
1050 | static struct uart_driver ip22zilog_reg; |
1051 | |
1052 | static struct console ip22zilog_console = { |
1053 | .name = "ttyS" , |
1054 | .write = ip22zilog_console_write, |
1055 | .device = uart_console_device, |
1056 | .setup = ip22zilog_console_setup, |
1057 | .flags = CON_PRINTBUFFER, |
1058 | .index = -1, |
1059 | .data = &ip22zilog_reg, |
1060 | }; |
1061 | #endif /* CONFIG_SERIAL_IP22_ZILOG_CONSOLE */ |
1062 | |
1063 | static struct uart_driver ip22zilog_reg = { |
1064 | .owner = THIS_MODULE, |
1065 | .driver_name = "serial" , |
1066 | .dev_name = "ttyS" , |
1067 | .major = TTY_MAJOR, |
1068 | .minor = 64, |
1069 | .nr = NUM_CHANNELS, |
1070 | #ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE |
1071 | .cons = &ip22zilog_console, |
1072 | #endif |
1073 | }; |
1074 | |
1075 | static void __init ip22zilog_prepare(void) |
1076 | { |
1077 | unsigned char sysrq_on = IS_ENABLED(CONFIG_SERIAL_IP22_ZILOG_CONSOLE); |
1078 | struct uart_ip22zilog_port *up; |
1079 | struct zilog_layout *rp; |
1080 | int channel, chip; |
1081 | |
1082 | /* |
1083 | * Temporary fix. |
1084 | */ |
1085 | for (channel = 0; channel < NUM_CHANNELS; channel++) |
1086 | spin_lock_init(&ip22zilog_port_table[channel].port.lock); |
1087 | |
1088 | ip22zilog_irq_chain = &ip22zilog_port_table[NUM_CHANNELS - 1]; |
1089 | up = &ip22zilog_port_table[0]; |
1090 | for (channel = NUM_CHANNELS - 1 ; channel > 0; channel--) |
1091 | up[channel].next = &up[channel - 1]; |
1092 | up[channel].next = NULL; |
1093 | |
1094 | for (chip = 0; chip < NUM_IP22ZILOG; chip++) { |
1095 | if (!ip22zilog_chip_regs[chip]) { |
1096 | ip22zilog_chip_regs[chip] = rp = get_zs(chip); |
1097 | |
1098 | up[(chip * 2) + 0].port.membase = (char *) &rp->channelB; |
1099 | up[(chip * 2) + 1].port.membase = (char *) &rp->channelA; |
1100 | |
1101 | /* In theory mapbase is the physical address ... */ |
1102 | up[(chip * 2) + 0].port.mapbase = |
1103 | (unsigned long) ioremap(offset: (unsigned long) &rp->channelB, size: 8); |
1104 | up[(chip * 2) + 1].port.mapbase = |
1105 | (unsigned long) ioremap(offset: (unsigned long) &rp->channelA, size: 8); |
1106 | } |
1107 | |
1108 | /* Channel A */ |
1109 | up[(chip * 2) + 0].port.iotype = UPIO_MEM; |
1110 | up[(chip * 2) + 0].port.irq = zilog_irq; |
1111 | up[(chip * 2) + 0].port.uartclk = ZS_CLOCK; |
1112 | up[(chip * 2) + 0].port.fifosize = 1; |
1113 | up[(chip * 2) + 0].port.has_sysrq = sysrq_on; |
1114 | up[(chip * 2) + 0].port.ops = &ip22zilog_pops; |
1115 | up[(chip * 2) + 0].port.type = PORT_IP22ZILOG; |
1116 | up[(chip * 2) + 0].port.flags = 0; |
1117 | up[(chip * 2) + 0].port.line = (chip * 2) + 0; |
1118 | up[(chip * 2) + 0].flags = 0; |
1119 | |
1120 | /* Channel B */ |
1121 | up[(chip * 2) + 1].port.iotype = UPIO_MEM; |
1122 | up[(chip * 2) + 1].port.irq = zilog_irq; |
1123 | up[(chip * 2) + 1].port.uartclk = ZS_CLOCK; |
1124 | up[(chip * 2) + 1].port.fifosize = 1; |
1125 | up[(chip * 2) + 1].port.has_sysrq = sysrq_on; |
1126 | up[(chip * 2) + 1].port.ops = &ip22zilog_pops; |
1127 | up[(chip * 2) + 1].port.type = PORT_IP22ZILOG; |
1128 | up[(chip * 2) + 1].port.line = (chip * 2) + 1; |
1129 | up[(chip * 2) + 1].flags |= IP22ZILOG_FLAG_IS_CHANNEL_A; |
1130 | } |
1131 | |
1132 | for (channel = 0; channel < NUM_CHANNELS; channel++) { |
1133 | struct uart_ip22zilog_port *up = &ip22zilog_port_table[channel]; |
1134 | int brg; |
1135 | |
1136 | /* Normal serial TTY. */ |
1137 | up->parity_mask = 0xff; |
1138 | up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; |
1139 | up->curregs[R4] = PAR_EVEN | X16CLK | SB1; |
1140 | up->curregs[R3] = RxENAB | Rx8; |
1141 | up->curregs[R5] = TxENAB | Tx8; |
1142 | up->curregs[R9] = NV | MIE; |
1143 | up->curregs[R10] = NRZ; |
1144 | up->curregs[R11] = TCBR | RCBR; |
1145 | brg = BPS_TO_BRG(9600, ZS_CLOCK / ZS_CLOCK_DIVISOR); |
1146 | up->curregs[R12] = (brg & 0xff); |
1147 | up->curregs[R13] = (brg >> 8) & 0xff; |
1148 | up->curregs[R14] = BRENAB; |
1149 | } |
1150 | } |
1151 | |
1152 | static int __init ip22zilog_ports_init(void) |
1153 | { |
1154 | int ret; |
1155 | |
1156 | printk(KERN_INFO "Serial: IP22 Zilog driver (%d chips).\n" , NUM_IP22ZILOG); |
1157 | |
1158 | ip22zilog_prepare(); |
1159 | |
1160 | if (request_irq(irq: zilog_irq, handler: ip22zilog_interrupt, flags: 0, |
1161 | name: "IP22-Zilog" , dev: ip22zilog_irq_chain)) { |
1162 | panic(fmt: "IP22-Zilog: Unable to register zs interrupt handler.\n" ); |
1163 | } |
1164 | |
1165 | ret = uart_register_driver(uart: &ip22zilog_reg); |
1166 | if (ret == 0) { |
1167 | int i; |
1168 | |
1169 | for (i = 0; i < NUM_CHANNELS; i++) { |
1170 | struct uart_ip22zilog_port *up = &ip22zilog_port_table[i]; |
1171 | |
1172 | uart_add_one_port(reg: &ip22zilog_reg, port: &up->port); |
1173 | } |
1174 | } |
1175 | |
1176 | return ret; |
1177 | } |
1178 | |
1179 | static int __init ip22zilog_init(void) |
1180 | { |
1181 | /* IP22 Zilog setup is hard coded, no probing to do. */ |
1182 | ip22zilog_alloc_tables(); |
1183 | ip22zilog_ports_init(); |
1184 | |
1185 | return 0; |
1186 | } |
1187 | |
1188 | static void __exit ip22zilog_exit(void) |
1189 | { |
1190 | int i; |
1191 | struct uart_ip22zilog_port *up; |
1192 | |
1193 | for (i = 0; i < NUM_CHANNELS; i++) { |
1194 | up = &ip22zilog_port_table[i]; |
1195 | |
1196 | uart_remove_one_port(reg: &ip22zilog_reg, port: &up->port); |
1197 | } |
1198 | |
1199 | /* Free IO mem */ |
1200 | up = &ip22zilog_port_table[0]; |
1201 | for (i = 0; i < NUM_IP22ZILOG; i++) { |
1202 | if (up[(i * 2) + 0].port.mapbase) { |
1203 | iounmap(addr: (void*)up[(i * 2) + 0].port.mapbase); |
1204 | up[(i * 2) + 0].port.mapbase = 0; |
1205 | } |
1206 | if (up[(i * 2) + 1].port.mapbase) { |
1207 | iounmap(addr: (void*)up[(i * 2) + 1].port.mapbase); |
1208 | up[(i * 2) + 1].port.mapbase = 0; |
1209 | } |
1210 | } |
1211 | |
1212 | uart_unregister_driver(uart: &ip22zilog_reg); |
1213 | } |
1214 | |
1215 | module_init(ip22zilog_init); |
1216 | module_exit(ip22zilog_exit); |
1217 | |
1218 | /* David wrote it but I'm to blame for the bugs ... */ |
1219 | MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>" ); |
1220 | MODULE_DESCRIPTION("SGI Zilog serial port driver" ); |
1221 | MODULE_LICENSE("GPL" ); |
1222 | |