1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. |
4 | * |
5 | * Copyright (C) 2004 Infineon IFAP DC COM CPE |
6 | * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org> |
7 | * Copyright (C) 2007 John Crispin <john@phrozen.org> |
8 | * Copyright (C) 2010 Thomas Langer, <thomas.langer@lantiq.com> |
9 | */ |
10 | |
11 | #include <linux/bitfield.h> |
12 | #include <linux/clk.h> |
13 | #include <linux/console.h> |
14 | #include <linux/device.h> |
15 | #include <linux/init.h> |
16 | #include <linux/io.h> |
17 | #include <linux/ioport.h> |
18 | #include <linux/lantiq.h> |
19 | #include <linux/module.h> |
20 | #include <linux/of.h> |
21 | #include <linux/platform_device.h> |
22 | #include <linux/serial.h> |
23 | #include <linux/serial_core.h> |
24 | #include <linux/slab.h> |
25 | #include <linux/sysrq.h> |
26 | #include <linux/tty.h> |
27 | #include <linux/tty_flip.h> |
28 | |
29 | #define PORT_LTQ_ASC 111 |
30 | #define MAXPORTS 2 |
31 | #define UART_DUMMY_UER_RX 1 |
32 | #define DRVNAME "lantiq,asc" |
33 | #ifdef __BIG_ENDIAN |
34 | #define LTQ_ASC_TBUF (0x0020 + 3) |
35 | #define LTQ_ASC_RBUF (0x0024 + 3) |
36 | #else |
37 | #define LTQ_ASC_TBUF 0x0020 |
38 | #define LTQ_ASC_RBUF 0x0024 |
39 | #endif |
40 | #define LTQ_ASC_FSTAT 0x0048 |
41 | #define LTQ_ASC_WHBSTATE 0x0018 |
42 | #define LTQ_ASC_STATE 0x0014 |
43 | #define LTQ_ASC_IRNCR 0x00F8 |
44 | #define LTQ_ASC_CLC 0x0000 |
45 | #define LTQ_ASC_ID 0x0008 |
46 | #define LTQ_ASC_PISEL 0x0004 |
47 | #define LTQ_ASC_TXFCON 0x0044 |
48 | #define LTQ_ASC_RXFCON 0x0040 |
49 | #define LTQ_ASC_CON 0x0010 |
50 | #define LTQ_ASC_BG 0x0050 |
51 | #define LTQ_ASC_IRNREN 0x00F4 |
52 | |
53 | #define ASC_IRNREN_TX 0x1 |
54 | #define ASC_IRNREN_RX 0x2 |
55 | #define ASC_IRNREN_ERR 0x4 |
56 | #define ASC_IRNREN_TX_BUF 0x8 |
57 | #define ASC_IRNCR_TIR 0x1 |
58 | #define ASC_IRNCR_RIR 0x2 |
59 | #define ASC_IRNCR_EIR 0x4 |
60 | #define ASC_IRNCR_MASK GENMASK(2, 0) |
61 | |
62 | #define ASCOPT_CSIZE 0x3 |
63 | #define TXFIFO_FL 1 |
64 | #define RXFIFO_FL 1 |
65 | #define ASCCLC_DISS 0x2 |
66 | #define ASCCLC_RMCMASK 0x0000FF00 |
67 | #define ASCCLC_RMCOFFSET 8 |
68 | #define ASCCON_M_8ASYNC 0x0 |
69 | #define ASCCON_M_7ASYNC 0x2 |
70 | #define ASCCON_ODD 0x00000020 |
71 | #define ASCCON_STP 0x00000080 |
72 | #define ASCCON_BRS 0x00000100 |
73 | #define ASCCON_FDE 0x00000200 |
74 | #define ASCCON_R 0x00008000 |
75 | #define ASCCON_FEN 0x00020000 |
76 | #define ASCCON_ROEN 0x00080000 |
77 | #define ASCCON_TOEN 0x00100000 |
78 | #define ASCSTATE_PE 0x00010000 |
79 | #define ASCSTATE_FE 0x00020000 |
80 | #define ASCSTATE_ROE 0x00080000 |
81 | #define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE) |
82 | #define ASCWHBSTATE_CLRREN 0x00000001 |
83 | #define ASCWHBSTATE_SETREN 0x00000002 |
84 | #define ASCWHBSTATE_CLRPE 0x00000004 |
85 | #define ASCWHBSTATE_CLRFE 0x00000008 |
86 | #define ASCWHBSTATE_CLRROE 0x00000020 |
87 | #define ASCTXFCON_TXFEN 0x0001 |
88 | #define ASCTXFCON_TXFFLU 0x0002 |
89 | #define ASCTXFCON_TXFITLMASK 0x3F00 |
90 | #define ASCTXFCON_TXFITLOFF 8 |
91 | #define ASCRXFCON_RXFEN 0x0001 |
92 | #define ASCRXFCON_RXFFLU 0x0002 |
93 | #define ASCRXFCON_RXFITLMASK 0x3F00 |
94 | #define ASCRXFCON_RXFITLOFF 8 |
95 | #define ASCFSTAT_RXFFLMASK 0x003F |
96 | #define ASCFSTAT_TXFFLMASK 0x3F00 |
97 | #define ASCFSTAT_TXFREEMASK 0x3F000000 |
98 | |
99 | static struct ltq_uart_port *lqasc_port[MAXPORTS]; |
100 | static struct uart_driver lqasc_reg; |
101 | |
102 | struct ltq_soc_data { |
103 | int (*fetch_irq)(struct device *dev, struct ltq_uart_port *ltq_port); |
104 | int (*request_irq)(struct uart_port *port); |
105 | void (*free_irq)(struct uart_port *port); |
106 | }; |
107 | |
108 | struct ltq_uart_port { |
109 | struct uart_port port; |
110 | /* clock used to derive divider */ |
111 | struct clk *freqclk; |
112 | /* clock gating of the ASC core */ |
113 | struct clk *clk; |
114 | unsigned int tx_irq; |
115 | unsigned int rx_irq; |
116 | unsigned int err_irq; |
117 | unsigned int common_irq; |
118 | spinlock_t lock; /* exclusive access for multi core */ |
119 | |
120 | const struct ltq_soc_data *soc; |
121 | }; |
122 | |
123 | static inline void asc_update_bits(u32 clear, u32 set, void __iomem *reg) |
124 | { |
125 | u32 tmp = __raw_readl(addr: reg); |
126 | |
127 | __raw_writel(val: (tmp & ~clear) | set, addr: reg); |
128 | } |
129 | |
130 | static inline struct |
131 | ltq_uart_port *to_ltq_uart_port(struct uart_port *port) |
132 | { |
133 | return container_of(port, struct ltq_uart_port, port); |
134 | } |
135 | |
136 | static void |
137 | lqasc_stop_tx(struct uart_port *port) |
138 | { |
139 | return; |
140 | } |
141 | |
142 | static bool lqasc_tx_ready(struct uart_port *port) |
143 | { |
144 | u32 fstat = __raw_readl(addr: port->membase + LTQ_ASC_FSTAT); |
145 | |
146 | return FIELD_GET(ASCFSTAT_TXFREEMASK, fstat); |
147 | } |
148 | |
149 | static void |
150 | lqasc_start_tx(struct uart_port *port) |
151 | { |
152 | unsigned long flags; |
153 | struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); |
154 | u8 ch; |
155 | |
156 | spin_lock_irqsave(<q_port->lock, flags); |
157 | uart_port_tx(port, ch, |
158 | lqasc_tx_ready(port), |
159 | writeb(ch, port->membase + LTQ_ASC_TBUF)); |
160 | spin_unlock_irqrestore(lock: <q_port->lock, flags); |
161 | return; |
162 | } |
163 | |
164 | static void |
165 | lqasc_stop_rx(struct uart_port *port) |
166 | { |
167 | __raw_writel(ASCWHBSTATE_CLRREN, addr: port->membase + LTQ_ASC_WHBSTATE); |
168 | } |
169 | |
170 | static int |
171 | lqasc_rx_chars(struct uart_port *port) |
172 | { |
173 | struct tty_port *tport = &port->state->port; |
174 | unsigned int ch = 0, rsr = 0, fifocnt; |
175 | |
176 | fifocnt = __raw_readl(addr: port->membase + LTQ_ASC_FSTAT) & |
177 | ASCFSTAT_RXFFLMASK; |
178 | while (fifocnt--) { |
179 | u8 flag = TTY_NORMAL; |
180 | ch = readb(addr: port->membase + LTQ_ASC_RBUF); |
181 | rsr = (__raw_readl(addr: port->membase + LTQ_ASC_STATE) |
182 | & ASCSTATE_ANY) | UART_DUMMY_UER_RX; |
183 | tty_flip_buffer_push(port: tport); |
184 | port->icount.rx++; |
185 | |
186 | /* |
187 | * Note that the error handling code is |
188 | * out of the main execution path |
189 | */ |
190 | if (rsr & ASCSTATE_ANY) { |
191 | if (rsr & ASCSTATE_PE) { |
192 | port->icount.parity++; |
193 | asc_update_bits(clear: 0, ASCWHBSTATE_CLRPE, |
194 | reg: port->membase + LTQ_ASC_WHBSTATE); |
195 | } else if (rsr & ASCSTATE_FE) { |
196 | port->icount.frame++; |
197 | asc_update_bits(clear: 0, ASCWHBSTATE_CLRFE, |
198 | reg: port->membase + LTQ_ASC_WHBSTATE); |
199 | } |
200 | if (rsr & ASCSTATE_ROE) { |
201 | port->icount.overrun++; |
202 | asc_update_bits(clear: 0, ASCWHBSTATE_CLRROE, |
203 | reg: port->membase + LTQ_ASC_WHBSTATE); |
204 | } |
205 | |
206 | rsr &= port->read_status_mask; |
207 | |
208 | if (rsr & ASCSTATE_PE) |
209 | flag = TTY_PARITY; |
210 | else if (rsr & ASCSTATE_FE) |
211 | flag = TTY_FRAME; |
212 | } |
213 | |
214 | if ((rsr & port->ignore_status_mask) == 0) |
215 | tty_insert_flip_char(port: tport, ch, flag); |
216 | |
217 | if (rsr & ASCSTATE_ROE) |
218 | /* |
219 | * Overrun is special, since it's reported |
220 | * immediately, and doesn't affect the current |
221 | * character |
222 | */ |
223 | tty_insert_flip_char(port: tport, ch: 0, TTY_OVERRUN); |
224 | } |
225 | |
226 | if (ch != 0) |
227 | tty_flip_buffer_push(port: tport); |
228 | |
229 | return 0; |
230 | } |
231 | |
232 | static irqreturn_t |
233 | lqasc_tx_int(int irq, void *_port) |
234 | { |
235 | unsigned long flags; |
236 | struct uart_port *port = (struct uart_port *)_port; |
237 | struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); |
238 | |
239 | spin_lock_irqsave(<q_port->lock, flags); |
240 | __raw_writel(ASC_IRNCR_TIR, addr: port->membase + LTQ_ASC_IRNCR); |
241 | spin_unlock_irqrestore(lock: <q_port->lock, flags); |
242 | lqasc_start_tx(port); |
243 | return IRQ_HANDLED; |
244 | } |
245 | |
246 | static irqreturn_t |
247 | lqasc_err_int(int irq, void *_port) |
248 | { |
249 | unsigned long flags; |
250 | struct uart_port *port = (struct uart_port *)_port; |
251 | struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); |
252 | |
253 | spin_lock_irqsave(<q_port->lock, flags); |
254 | __raw_writel(ASC_IRNCR_EIR, addr: port->membase + LTQ_ASC_IRNCR); |
255 | /* clear any pending interrupts */ |
256 | asc_update_bits(clear: 0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE | |
257 | ASCWHBSTATE_CLRROE, reg: port->membase + LTQ_ASC_WHBSTATE); |
258 | spin_unlock_irqrestore(lock: <q_port->lock, flags); |
259 | return IRQ_HANDLED; |
260 | } |
261 | |
262 | static irqreturn_t |
263 | lqasc_rx_int(int irq, void *_port) |
264 | { |
265 | unsigned long flags; |
266 | struct uart_port *port = (struct uart_port *)_port; |
267 | struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); |
268 | |
269 | spin_lock_irqsave(<q_port->lock, flags); |
270 | __raw_writel(ASC_IRNCR_RIR, addr: port->membase + LTQ_ASC_IRNCR); |
271 | lqasc_rx_chars(port); |
272 | spin_unlock_irqrestore(lock: <q_port->lock, flags); |
273 | return IRQ_HANDLED; |
274 | } |
275 | |
276 | static irqreturn_t lqasc_irq(int irq, void *p) |
277 | { |
278 | unsigned long flags; |
279 | u32 stat; |
280 | struct uart_port *port = p; |
281 | struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); |
282 | |
283 | spin_lock_irqsave(<q_port->lock, flags); |
284 | stat = readl(addr: port->membase + LTQ_ASC_IRNCR); |
285 | spin_unlock_irqrestore(lock: <q_port->lock, flags); |
286 | if (!(stat & ASC_IRNCR_MASK)) |
287 | return IRQ_NONE; |
288 | |
289 | if (stat & ASC_IRNCR_TIR) |
290 | lqasc_tx_int(irq, port: p); |
291 | |
292 | if (stat & ASC_IRNCR_RIR) |
293 | lqasc_rx_int(irq, port: p); |
294 | |
295 | if (stat & ASC_IRNCR_EIR) |
296 | lqasc_err_int(irq, port: p); |
297 | |
298 | return IRQ_HANDLED; |
299 | } |
300 | |
301 | static unsigned int |
302 | lqasc_tx_empty(struct uart_port *port) |
303 | { |
304 | int status; |
305 | status = __raw_readl(addr: port->membase + LTQ_ASC_FSTAT) & |
306 | ASCFSTAT_TXFFLMASK; |
307 | return status ? 0 : TIOCSER_TEMT; |
308 | } |
309 | |
310 | static unsigned int |
311 | lqasc_get_mctrl(struct uart_port *port) |
312 | { |
313 | return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR; |
314 | } |
315 | |
316 | static void |
317 | lqasc_set_mctrl(struct uart_port *port, u_int mctrl) |
318 | { |
319 | } |
320 | |
321 | static void |
322 | lqasc_break_ctl(struct uart_port *port, int break_state) |
323 | { |
324 | } |
325 | |
326 | static int |
327 | lqasc_startup(struct uart_port *port) |
328 | { |
329 | struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); |
330 | int retval; |
331 | unsigned long flags; |
332 | |
333 | if (!IS_ERR(ptr: ltq_port->clk)) |
334 | clk_prepare_enable(clk: ltq_port->clk); |
335 | port->uartclk = clk_get_rate(clk: ltq_port->freqclk); |
336 | |
337 | spin_lock_irqsave(<q_port->lock, flags); |
338 | asc_update_bits(ASCCLC_DISS | ASCCLC_RMCMASK, set: (1 << ASCCLC_RMCOFFSET), |
339 | reg: port->membase + LTQ_ASC_CLC); |
340 | |
341 | __raw_writel(val: 0, addr: port->membase + LTQ_ASC_PISEL); |
342 | __raw_writel( |
343 | val: ((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | |
344 | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, |
345 | addr: port->membase + LTQ_ASC_TXFCON); |
346 | __raw_writel( |
347 | val: ((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) |
348 | | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, |
349 | addr: port->membase + LTQ_ASC_RXFCON); |
350 | /* make sure other settings are written to hardware before |
351 | * setting enable bits |
352 | */ |
353 | wmb(); |
354 | asc_update_bits(clear: 0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | |
355 | ASCCON_ROEN, reg: port->membase + LTQ_ASC_CON); |
356 | |
357 | spin_unlock_irqrestore(lock: <q_port->lock, flags); |
358 | |
359 | retval = ltq_port->soc->request_irq(port); |
360 | if (retval) |
361 | return retval; |
362 | |
363 | __raw_writel(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX, |
364 | addr: port->membase + LTQ_ASC_IRNREN); |
365 | return retval; |
366 | } |
367 | |
368 | static void |
369 | lqasc_shutdown(struct uart_port *port) |
370 | { |
371 | struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); |
372 | unsigned long flags; |
373 | |
374 | ltq_port->soc->free_irq(port); |
375 | |
376 | spin_lock_irqsave(<q_port->lock, flags); |
377 | __raw_writel(val: 0, addr: port->membase + LTQ_ASC_CON); |
378 | asc_update_bits(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU, |
379 | reg: port->membase + LTQ_ASC_RXFCON); |
380 | asc_update_bits(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU, |
381 | reg: port->membase + LTQ_ASC_TXFCON); |
382 | spin_unlock_irqrestore(lock: <q_port->lock, flags); |
383 | if (!IS_ERR(ptr: ltq_port->clk)) |
384 | clk_disable_unprepare(clk: ltq_port->clk); |
385 | } |
386 | |
387 | static void |
388 | lqasc_set_termios(struct uart_port *port, struct ktermios *new, |
389 | const struct ktermios *old) |
390 | { |
391 | unsigned int cflag; |
392 | unsigned int iflag; |
393 | unsigned int divisor; |
394 | unsigned int baud; |
395 | unsigned int con = 0; |
396 | unsigned long flags; |
397 | struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); |
398 | |
399 | cflag = new->c_cflag; |
400 | iflag = new->c_iflag; |
401 | |
402 | switch (cflag & CSIZE) { |
403 | case CS7: |
404 | con = ASCCON_M_7ASYNC; |
405 | break; |
406 | |
407 | case CS5: |
408 | case CS6: |
409 | default: |
410 | new->c_cflag &= ~ CSIZE; |
411 | new->c_cflag |= CS8; |
412 | con = ASCCON_M_8ASYNC; |
413 | break; |
414 | } |
415 | |
416 | cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ |
417 | |
418 | if (cflag & CSTOPB) |
419 | con |= ASCCON_STP; |
420 | |
421 | if (cflag & PARENB) { |
422 | if (!(cflag & PARODD)) |
423 | con &= ~ASCCON_ODD; |
424 | else |
425 | con |= ASCCON_ODD; |
426 | } |
427 | |
428 | port->read_status_mask = ASCSTATE_ROE; |
429 | if (iflag & INPCK) |
430 | port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE; |
431 | |
432 | port->ignore_status_mask = 0; |
433 | if (iflag & IGNPAR) |
434 | port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE; |
435 | |
436 | if (iflag & IGNBRK) { |
437 | /* |
438 | * If we're ignoring parity and break indicators, |
439 | * ignore overruns too (for real raw support). |
440 | */ |
441 | if (iflag & IGNPAR) |
442 | port->ignore_status_mask |= ASCSTATE_ROE; |
443 | } |
444 | |
445 | if ((cflag & CREAD) == 0) |
446 | port->ignore_status_mask |= UART_DUMMY_UER_RX; |
447 | |
448 | /* set error signals - framing, parity and overrun, enable receiver */ |
449 | con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN; |
450 | |
451 | spin_lock_irqsave(<q_port->lock, flags); |
452 | |
453 | /* set up CON */ |
454 | asc_update_bits(clear: 0, set: con, reg: port->membase + LTQ_ASC_CON); |
455 | |
456 | /* Set baud rate - take a divider of 2 into account */ |
457 | baud = uart_get_baud_rate(port, termios: new, old, min: 0, max: port->uartclk / 16); |
458 | divisor = uart_get_divisor(port, baud); |
459 | divisor = divisor / 2 - 1; |
460 | |
461 | /* disable the baudrate generator */ |
462 | asc_update_bits(ASCCON_R, set: 0, reg: port->membase + LTQ_ASC_CON); |
463 | |
464 | /* make sure the fractional divider is off */ |
465 | asc_update_bits(ASCCON_FDE, set: 0, reg: port->membase + LTQ_ASC_CON); |
466 | |
467 | /* set up to use divisor of 2 */ |
468 | asc_update_bits(ASCCON_BRS, set: 0, reg: port->membase + LTQ_ASC_CON); |
469 | |
470 | /* now we can write the new baudrate into the register */ |
471 | __raw_writel(val: divisor, addr: port->membase + LTQ_ASC_BG); |
472 | |
473 | /* turn the baudrate generator back on */ |
474 | asc_update_bits(clear: 0, ASCCON_R, reg: port->membase + LTQ_ASC_CON); |
475 | |
476 | /* enable rx */ |
477 | __raw_writel(ASCWHBSTATE_SETREN, addr: port->membase + LTQ_ASC_WHBSTATE); |
478 | |
479 | spin_unlock_irqrestore(lock: <q_port->lock, flags); |
480 | |
481 | /* Don't rewrite B0 */ |
482 | if (tty_termios_baud_rate(termios: new)) |
483 | tty_termios_encode_baud_rate(termios: new, ibaud: baud, obaud: baud); |
484 | |
485 | uart_update_timeout(port, cflag, baud); |
486 | } |
487 | |
488 | static const char* |
489 | lqasc_type(struct uart_port *port) |
490 | { |
491 | if (port->type == PORT_LTQ_ASC) |
492 | return DRVNAME; |
493 | else |
494 | return NULL; |
495 | } |
496 | |
497 | static void |
498 | lqasc_release_port(struct uart_port *port) |
499 | { |
500 | struct platform_device *pdev = to_platform_device(port->dev); |
501 | |
502 | if (port->flags & UPF_IOREMAP) { |
503 | devm_iounmap(dev: &pdev->dev, addr: port->membase); |
504 | port->membase = NULL; |
505 | } |
506 | } |
507 | |
508 | static int |
509 | lqasc_request_port(struct uart_port *port) |
510 | { |
511 | struct platform_device *pdev = to_platform_device(port->dev); |
512 | struct resource *res; |
513 | int size; |
514 | |
515 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
516 | if (!res) { |
517 | dev_err(&pdev->dev, "cannot obtain I/O memory region" ); |
518 | return -ENODEV; |
519 | } |
520 | size = resource_size(res); |
521 | |
522 | res = devm_request_mem_region(&pdev->dev, res->start, |
523 | size, dev_name(&pdev->dev)); |
524 | if (!res) { |
525 | dev_err(&pdev->dev, "cannot request I/O memory region" ); |
526 | return -EBUSY; |
527 | } |
528 | |
529 | if (port->flags & UPF_IOREMAP) { |
530 | port->membase = devm_ioremap(dev: &pdev->dev, |
531 | offset: port->mapbase, size); |
532 | if (port->membase == NULL) |
533 | return -ENOMEM; |
534 | } |
535 | return 0; |
536 | } |
537 | |
538 | static void |
539 | lqasc_config_port(struct uart_port *port, int flags) |
540 | { |
541 | if (flags & UART_CONFIG_TYPE) { |
542 | port->type = PORT_LTQ_ASC; |
543 | lqasc_request_port(port); |
544 | } |
545 | } |
546 | |
547 | static int |
548 | lqasc_verify_port(struct uart_port *port, |
549 | struct serial_struct *ser) |
550 | { |
551 | int ret = 0; |
552 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_LTQ_ASC) |
553 | ret = -EINVAL; |
554 | if (ser->irq < 0 || ser->irq >= NR_IRQS) |
555 | ret = -EINVAL; |
556 | if (ser->baud_base < 9600) |
557 | ret = -EINVAL; |
558 | return ret; |
559 | } |
560 | |
561 | static const struct uart_ops lqasc_pops = { |
562 | .tx_empty = lqasc_tx_empty, |
563 | .set_mctrl = lqasc_set_mctrl, |
564 | .get_mctrl = lqasc_get_mctrl, |
565 | .stop_tx = lqasc_stop_tx, |
566 | .start_tx = lqasc_start_tx, |
567 | .stop_rx = lqasc_stop_rx, |
568 | .break_ctl = lqasc_break_ctl, |
569 | .startup = lqasc_startup, |
570 | .shutdown = lqasc_shutdown, |
571 | .set_termios = lqasc_set_termios, |
572 | .type = lqasc_type, |
573 | .release_port = lqasc_release_port, |
574 | .request_port = lqasc_request_port, |
575 | .config_port = lqasc_config_port, |
576 | .verify_port = lqasc_verify_port, |
577 | }; |
578 | |
579 | #ifdef CONFIG_SERIAL_LANTIQ_CONSOLE |
580 | static void |
581 | lqasc_console_putchar(struct uart_port *port, unsigned char ch) |
582 | { |
583 | if (!port->membase) |
584 | return; |
585 | |
586 | while (!lqasc_tx_ready(port)) |
587 | ; |
588 | |
589 | writeb(val: ch, addr: port->membase + LTQ_ASC_TBUF); |
590 | } |
591 | |
592 | static void lqasc_serial_port_write(struct uart_port *port, const char *s, |
593 | u_int count) |
594 | { |
595 | uart_console_write(port, s, count, putchar: lqasc_console_putchar); |
596 | } |
597 | |
598 | static void |
599 | lqasc_console_write(struct console *co, const char *s, u_int count) |
600 | { |
601 | struct ltq_uart_port *ltq_port; |
602 | unsigned long flags; |
603 | |
604 | if (co->index >= MAXPORTS) |
605 | return; |
606 | |
607 | ltq_port = lqasc_port[co->index]; |
608 | if (!ltq_port) |
609 | return; |
610 | |
611 | spin_lock_irqsave(<q_port->lock, flags); |
612 | lqasc_serial_port_write(port: <q_port->port, s, count); |
613 | spin_unlock_irqrestore(lock: <q_port->lock, flags); |
614 | } |
615 | |
616 | static int __init |
617 | lqasc_console_setup(struct console *co, char *options) |
618 | { |
619 | struct ltq_uart_port *ltq_port; |
620 | struct uart_port *port; |
621 | int baud = 115200; |
622 | int bits = 8; |
623 | int parity = 'n'; |
624 | int flow = 'n'; |
625 | |
626 | if (co->index >= MAXPORTS) |
627 | return -ENODEV; |
628 | |
629 | ltq_port = lqasc_port[co->index]; |
630 | if (!ltq_port) |
631 | return -ENODEV; |
632 | |
633 | port = <q_port->port; |
634 | |
635 | if (!IS_ERR(ptr: ltq_port->clk)) |
636 | clk_prepare_enable(clk: ltq_port->clk); |
637 | |
638 | port->uartclk = clk_get_rate(clk: ltq_port->freqclk); |
639 | |
640 | if (options) |
641 | uart_parse_options(options, baud: &baud, parity: &parity, bits: &bits, flow: &flow); |
642 | return uart_set_options(port, co, baud, parity, bits, flow); |
643 | } |
644 | |
645 | static struct console lqasc_console = { |
646 | .name = "ttyLTQ" , |
647 | .write = lqasc_console_write, |
648 | .device = uart_console_device, |
649 | .setup = lqasc_console_setup, |
650 | .flags = CON_PRINTBUFFER, |
651 | .index = -1, |
652 | .data = &lqasc_reg, |
653 | }; |
654 | |
655 | static int __init |
656 | lqasc_console_init(void) |
657 | { |
658 | register_console(&lqasc_console); |
659 | return 0; |
660 | } |
661 | console_initcall(lqasc_console_init); |
662 | |
663 | static void lqasc_serial_early_console_write(struct console *co, |
664 | const char *s, |
665 | u_int count) |
666 | { |
667 | struct earlycon_device *dev = co->data; |
668 | |
669 | lqasc_serial_port_write(port: &dev->port, s, count); |
670 | } |
671 | |
672 | static int __init |
673 | lqasc_serial_early_console_setup(struct earlycon_device *device, |
674 | const char *opt) |
675 | { |
676 | if (!device->port.membase) |
677 | return -ENODEV; |
678 | |
679 | device->con->write = lqasc_serial_early_console_write; |
680 | return 0; |
681 | } |
682 | OF_EARLYCON_DECLARE(lantiq, "lantiq,asc" , lqasc_serial_early_console_setup); |
683 | OF_EARLYCON_DECLARE(lantiq, "intel,lgm-asc" , lqasc_serial_early_console_setup); |
684 | |
685 | #define LANTIQ_SERIAL_CONSOLE (&lqasc_console) |
686 | |
687 | #else |
688 | |
689 | #define LANTIQ_SERIAL_CONSOLE NULL |
690 | |
691 | #endif /* CONFIG_SERIAL_LANTIQ_CONSOLE */ |
692 | |
693 | static struct uart_driver lqasc_reg = { |
694 | .owner = THIS_MODULE, |
695 | .driver_name = DRVNAME, |
696 | .dev_name = "ttyLTQ" , |
697 | .major = 0, |
698 | .minor = 0, |
699 | .nr = MAXPORTS, |
700 | .cons = LANTIQ_SERIAL_CONSOLE, |
701 | }; |
702 | |
703 | static int fetch_irq_lantiq(struct device *dev, struct ltq_uart_port *ltq_port) |
704 | { |
705 | struct uart_port *port = <q_port->port; |
706 | struct platform_device *pdev = to_platform_device(dev); |
707 | int irq; |
708 | |
709 | irq = platform_get_irq(pdev, 0); |
710 | if (irq < 0) |
711 | return irq; |
712 | ltq_port->tx_irq = irq; |
713 | irq = platform_get_irq(pdev, 1); |
714 | if (irq < 0) |
715 | return irq; |
716 | ltq_port->rx_irq = irq; |
717 | irq = platform_get_irq(pdev, 2); |
718 | if (irq < 0) |
719 | return irq; |
720 | ltq_port->err_irq = irq; |
721 | |
722 | port->irq = ltq_port->tx_irq; |
723 | |
724 | return 0; |
725 | } |
726 | |
727 | static int request_irq_lantiq(struct uart_port *port) |
728 | { |
729 | struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); |
730 | int retval; |
731 | |
732 | retval = request_irq(irq: ltq_port->tx_irq, handler: lqasc_tx_int, |
733 | flags: 0, name: "asc_tx" , dev: port); |
734 | if (retval) { |
735 | dev_err(port->dev, "failed to request asc_tx\n" ); |
736 | return retval; |
737 | } |
738 | |
739 | retval = request_irq(irq: ltq_port->rx_irq, handler: lqasc_rx_int, |
740 | flags: 0, name: "asc_rx" , dev: port); |
741 | if (retval) { |
742 | dev_err(port->dev, "failed to request asc_rx\n" ); |
743 | goto err1; |
744 | } |
745 | |
746 | retval = request_irq(irq: ltq_port->err_irq, handler: lqasc_err_int, |
747 | flags: 0, name: "asc_err" , dev: port); |
748 | if (retval) { |
749 | dev_err(port->dev, "failed to request asc_err\n" ); |
750 | goto err2; |
751 | } |
752 | return 0; |
753 | |
754 | err2: |
755 | free_irq(ltq_port->rx_irq, port); |
756 | err1: |
757 | free_irq(ltq_port->tx_irq, port); |
758 | return retval; |
759 | } |
760 | |
761 | static void free_irq_lantiq(struct uart_port *port) |
762 | { |
763 | struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); |
764 | |
765 | free_irq(ltq_port->tx_irq, port); |
766 | free_irq(ltq_port->rx_irq, port); |
767 | free_irq(ltq_port->err_irq, port); |
768 | } |
769 | |
770 | static int fetch_irq_intel(struct device *dev, struct ltq_uart_port *ltq_port) |
771 | { |
772 | struct uart_port *port = <q_port->port; |
773 | int ret; |
774 | |
775 | ret = platform_get_irq(to_platform_device(dev), 0); |
776 | if (ret < 0) { |
777 | dev_err(dev, "failed to fetch IRQ for serial port\n" ); |
778 | return ret; |
779 | } |
780 | ltq_port->common_irq = ret; |
781 | port->irq = ret; |
782 | |
783 | return 0; |
784 | } |
785 | |
786 | static int request_irq_intel(struct uart_port *port) |
787 | { |
788 | struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); |
789 | int retval; |
790 | |
791 | retval = request_irq(irq: ltq_port->common_irq, handler: lqasc_irq, flags: 0, |
792 | name: "asc_irq" , dev: port); |
793 | if (retval) |
794 | dev_err(port->dev, "failed to request asc_irq\n" ); |
795 | |
796 | return retval; |
797 | } |
798 | |
799 | static void free_irq_intel(struct uart_port *port) |
800 | { |
801 | struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); |
802 | |
803 | free_irq(ltq_port->common_irq, port); |
804 | } |
805 | |
806 | static int lqasc_probe(struct platform_device *pdev) |
807 | { |
808 | struct device_node *node = pdev->dev.of_node; |
809 | struct ltq_uart_port *ltq_port; |
810 | struct uart_port *port; |
811 | struct resource *mmres; |
812 | int line; |
813 | int ret; |
814 | |
815 | mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
816 | if (!mmres) { |
817 | dev_err(&pdev->dev, |
818 | "failed to get memory for serial port\n" ); |
819 | return -ENODEV; |
820 | } |
821 | |
822 | ltq_port = devm_kzalloc(dev: &pdev->dev, size: sizeof(struct ltq_uart_port), |
823 | GFP_KERNEL); |
824 | if (!ltq_port) |
825 | return -ENOMEM; |
826 | |
827 | port = <q_port->port; |
828 | |
829 | ltq_port->soc = of_device_get_match_data(dev: &pdev->dev); |
830 | ret = ltq_port->soc->fetch_irq(&pdev->dev, ltq_port); |
831 | if (ret) |
832 | return ret; |
833 | |
834 | /* get serial id */ |
835 | line = of_alias_get_id(np: node, stem: "serial" ); |
836 | if (line < 0) { |
837 | if (IS_ENABLED(CONFIG_LANTIQ)) { |
838 | if (mmres->start == CPHYSADDR(LTQ_EARLY_ASC)) |
839 | line = 0; |
840 | else |
841 | line = 1; |
842 | } else { |
843 | dev_err(&pdev->dev, "failed to get alias id, errno %d\n" , |
844 | line); |
845 | return line; |
846 | } |
847 | } |
848 | |
849 | if (lqasc_port[line]) { |
850 | dev_err(&pdev->dev, "port %d already allocated\n" , line); |
851 | return -EBUSY; |
852 | } |
853 | |
854 | port->iotype = SERIAL_IO_MEM; |
855 | port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP; |
856 | port->ops = &lqasc_pops; |
857 | port->fifosize = 16; |
858 | port->type = PORT_LTQ_ASC; |
859 | port->line = line; |
860 | port->dev = &pdev->dev; |
861 | /* unused, just to be backward-compatible */ |
862 | port->mapbase = mmres->start; |
863 | |
864 | if (IS_ENABLED(CONFIG_LANTIQ) && !IS_ENABLED(CONFIG_COMMON_CLK)) |
865 | ltq_port->freqclk = clk_get_fpi(); |
866 | else |
867 | ltq_port->freqclk = devm_clk_get(dev: &pdev->dev, id: "freq" ); |
868 | |
869 | |
870 | if (IS_ERR(ptr: ltq_port->freqclk)) { |
871 | pr_err("failed to get fpi clk\n" ); |
872 | return -ENOENT; |
873 | } |
874 | |
875 | /* not all asc ports have clock gates, lets ignore the return code */ |
876 | if (IS_ENABLED(CONFIG_LANTIQ) && !IS_ENABLED(CONFIG_COMMON_CLK)) |
877 | ltq_port->clk = clk_get(dev: &pdev->dev, NULL); |
878 | else |
879 | ltq_port->clk = devm_clk_get(dev: &pdev->dev, id: "asc" ); |
880 | |
881 | spin_lock_init(<q_port->lock); |
882 | lqasc_port[line] = ltq_port; |
883 | platform_set_drvdata(pdev, data: ltq_port); |
884 | |
885 | ret = uart_add_one_port(reg: &lqasc_reg, port); |
886 | |
887 | return ret; |
888 | } |
889 | |
890 | static int lqasc_remove(struct platform_device *pdev) |
891 | { |
892 | struct uart_port *port = platform_get_drvdata(pdev); |
893 | |
894 | uart_remove_one_port(reg: &lqasc_reg, port); |
895 | |
896 | return 0; |
897 | } |
898 | |
899 | static const struct ltq_soc_data soc_data_lantiq = { |
900 | .fetch_irq = fetch_irq_lantiq, |
901 | .request_irq = request_irq_lantiq, |
902 | .free_irq = free_irq_lantiq, |
903 | }; |
904 | |
905 | static const struct ltq_soc_data soc_data_intel = { |
906 | .fetch_irq = fetch_irq_intel, |
907 | .request_irq = request_irq_intel, |
908 | .free_irq = free_irq_intel, |
909 | }; |
910 | |
911 | static const struct of_device_id ltq_asc_match[] = { |
912 | { .compatible = "lantiq,asc" , .data = &soc_data_lantiq }, |
913 | { .compatible = "intel,lgm-asc" , .data = &soc_data_intel }, |
914 | {}, |
915 | }; |
916 | MODULE_DEVICE_TABLE(of, ltq_asc_match); |
917 | |
918 | static struct platform_driver lqasc_driver = { |
919 | .probe = lqasc_probe, |
920 | .remove = lqasc_remove, |
921 | .driver = { |
922 | .name = DRVNAME, |
923 | .of_match_table = ltq_asc_match, |
924 | }, |
925 | }; |
926 | |
927 | static int __init |
928 | init_lqasc(void) |
929 | { |
930 | int ret; |
931 | |
932 | ret = uart_register_driver(uart: &lqasc_reg); |
933 | if (ret != 0) |
934 | return ret; |
935 | |
936 | ret = platform_driver_register(&lqasc_driver); |
937 | if (ret != 0) |
938 | uart_unregister_driver(uart: &lqasc_reg); |
939 | |
940 | return ret; |
941 | } |
942 | |
943 | static void __exit exit_lqasc(void) |
944 | { |
945 | platform_driver_unregister(&lqasc_driver); |
946 | uart_unregister_driver(uart: &lqasc_reg); |
947 | } |
948 | |
949 | module_init(init_lqasc); |
950 | module_exit(exit_lqasc); |
951 | |
952 | MODULE_DESCRIPTION("Serial driver for Lantiq & Intel gateway SoCs" ); |
953 | MODULE_LICENSE("GPL v2" ); |
954 | |