1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * MEN 16z135 High Speed UART |
4 | * |
5 | * Copyright (C) 2014 MEN Mikroelektronik GmbH (www.men.de) |
6 | * Author: Johannes Thumshirn <johannes.thumshirn@men.de> |
7 | */ |
8 | #define pr_fmt(fmt) KBUILD_MODNAME ":" fmt |
9 | |
10 | #include <linux/kernel.h> |
11 | #include <linux/module.h> |
12 | #include <linux/interrupt.h> |
13 | #include <linux/serial_core.h> |
14 | #include <linux/ioport.h> |
15 | #include <linux/io.h> |
16 | #include <linux/tty_flip.h> |
17 | #include <linux/bitops.h> |
18 | #include <linux/mcb.h> |
19 | |
20 | #define MEN_Z135_MAX_PORTS 12 |
21 | #define MEN_Z135_BASECLK 29491200 |
22 | #define MEN_Z135_FIFO_SIZE 1024 |
23 | #define MEN_Z135_FIFO_WATERMARK 1020 |
24 | |
25 | #define MEN_Z135_STAT_REG 0x0 |
26 | #define MEN_Z135_RX_RAM 0x4 |
27 | #define MEN_Z135_TX_RAM 0x400 |
28 | #define MEN_Z135_RX_CTRL 0x800 |
29 | #define MEN_Z135_TX_CTRL 0x804 |
30 | #define MEN_Z135_CONF_REG 0x808 |
31 | #define MEN_Z135_UART_FREQ 0x80c |
32 | #define MEN_Z135_BAUD_REG 0x810 |
33 | #define MEN_Z135_TIMEOUT 0x814 |
34 | |
35 | #define IRQ_ID(x) ((x) & 0x1f) |
36 | |
37 | #define MEN_Z135_IER_RXCIEN BIT(0) /* RX Space IRQ */ |
38 | #define MEN_Z135_IER_TXCIEN BIT(1) /* TX Space IRQ */ |
39 | #define MEN_Z135_IER_RLSIEN BIT(2) /* Receiver Line Status IRQ */ |
40 | #define MEN_Z135_IER_MSIEN BIT(3) /* Modem Status IRQ */ |
41 | #define MEN_Z135_ALL_IRQS (MEN_Z135_IER_RXCIEN \ |
42 | | MEN_Z135_IER_RLSIEN \ |
43 | | MEN_Z135_IER_MSIEN \ |
44 | | MEN_Z135_IER_TXCIEN) |
45 | |
46 | #define MEN_Z135_MCR_DTR BIT(24) |
47 | #define MEN_Z135_MCR_RTS BIT(25) |
48 | #define MEN_Z135_MCR_OUT1 BIT(26) |
49 | #define MEN_Z135_MCR_OUT2 BIT(27) |
50 | #define MEN_Z135_MCR_LOOP BIT(28) |
51 | #define MEN_Z135_MCR_RCFC BIT(29) |
52 | |
53 | #define MEN_Z135_MSR_DCTS BIT(0) |
54 | #define MEN_Z135_MSR_DDSR BIT(1) |
55 | #define MEN_Z135_MSR_DRI BIT(2) |
56 | #define MEN_Z135_MSR_DDCD BIT(3) |
57 | #define MEN_Z135_MSR_CTS BIT(4) |
58 | #define MEN_Z135_MSR_DSR BIT(5) |
59 | #define MEN_Z135_MSR_RI BIT(6) |
60 | #define MEN_Z135_MSR_DCD BIT(7) |
61 | |
62 | #define MEN_Z135_LCR_SHIFT 8 /* LCR shift mask */ |
63 | |
64 | #define MEN_Z135_WL5 0 /* CS5 */ |
65 | #define MEN_Z135_WL6 1 /* CS6 */ |
66 | #define MEN_Z135_WL7 2 /* CS7 */ |
67 | #define MEN_Z135_WL8 3 /* CS8 */ |
68 | |
69 | #define MEN_Z135_STB_SHIFT 2 /* Stopbits */ |
70 | #define MEN_Z135_NSTB1 0 |
71 | #define MEN_Z135_NSTB2 1 |
72 | |
73 | #define MEN_Z135_PEN_SHIFT 3 /* Parity enable */ |
74 | #define MEN_Z135_PAR_DIS 0 |
75 | #define MEN_Z135_PAR_ENA 1 |
76 | |
77 | #define MEN_Z135_PTY_SHIFT 4 /* Parity type */ |
78 | #define MEN_Z135_PTY_ODD 0 |
79 | #define MEN_Z135_PTY_EVN 1 |
80 | |
81 | #define MEN_Z135_LSR_DR BIT(0) |
82 | #define MEN_Z135_LSR_OE BIT(1) |
83 | #define MEN_Z135_LSR_PE BIT(2) |
84 | #define MEN_Z135_LSR_FE BIT(3) |
85 | #define MEN_Z135_LSR_BI BIT(4) |
86 | #define MEN_Z135_LSR_THEP BIT(5) |
87 | #define MEN_Z135_LSR_TEXP BIT(6) |
88 | #define MEN_Z135_LSR_RXFIFOERR BIT(7) |
89 | |
90 | #define MEN_Z135_IRQ_ID_RLS BIT(0) |
91 | #define MEN_Z135_IRQ_ID_RDA BIT(1) |
92 | #define MEN_Z135_IRQ_ID_CTI BIT(2) |
93 | #define MEN_Z135_IRQ_ID_TSA BIT(3) |
94 | #define MEN_Z135_IRQ_ID_MST BIT(4) |
95 | |
96 | #define LCR(x) (((x) >> MEN_Z135_LCR_SHIFT) & 0xff) |
97 | |
98 | #define BYTES_TO_ALIGN(x) ((x) & 0x3) |
99 | |
100 | static int line; |
101 | |
102 | static int txlvl = 5; |
103 | module_param(txlvl, int, S_IRUGO); |
104 | MODULE_PARM_DESC(txlvl, "TX IRQ trigger level 0-7, default 5 (128 byte)" ); |
105 | |
106 | static int rxlvl = 6; |
107 | module_param(rxlvl, int, S_IRUGO); |
108 | MODULE_PARM_DESC(rxlvl, "RX IRQ trigger level 0-7, default 6 (256 byte)" ); |
109 | |
110 | static int align; |
111 | module_param(align, int, S_IRUGO); |
112 | MODULE_PARM_DESC(align, "Keep hardware FIFO write pointer aligned, default 0" ); |
113 | |
114 | static uint rx_timeout; |
115 | module_param(rx_timeout, uint, S_IRUGO); |
116 | MODULE_PARM_DESC(rx_timeout, "RX timeout. " |
117 | "Timeout in seconds = (timeout_reg * baud_reg * 4) / freq_reg" ); |
118 | |
119 | struct men_z135_port { |
120 | struct uart_port port; |
121 | struct mcb_device *mdev; |
122 | struct resource *mem; |
123 | unsigned char *rxbuf; |
124 | u32 stat_reg; |
125 | spinlock_t lock; |
126 | bool automode; |
127 | }; |
128 | #define to_men_z135(port) container_of((port), struct men_z135_port, port) |
129 | |
130 | /** |
131 | * men_z135_reg_set() - Set value in register |
132 | * @uart: The UART port |
133 | * @addr: Register address |
134 | * @val: value to set |
135 | */ |
136 | static inline void men_z135_reg_set(struct men_z135_port *uart, |
137 | u32 addr, u32 val) |
138 | { |
139 | struct uart_port *port = &uart->port; |
140 | unsigned long flags; |
141 | u32 reg; |
142 | |
143 | spin_lock_irqsave(&uart->lock, flags); |
144 | |
145 | reg = ioread32(port->membase + addr); |
146 | reg |= val; |
147 | iowrite32(reg, port->membase + addr); |
148 | |
149 | spin_unlock_irqrestore(lock: &uart->lock, flags); |
150 | } |
151 | |
152 | /** |
153 | * men_z135_reg_clr() - Unset value in register |
154 | * @uart: The UART port |
155 | * @addr: Register address |
156 | * @val: value to clear |
157 | */ |
158 | static void men_z135_reg_clr(struct men_z135_port *uart, |
159 | u32 addr, u32 val) |
160 | { |
161 | struct uart_port *port = &uart->port; |
162 | unsigned long flags; |
163 | u32 reg; |
164 | |
165 | spin_lock_irqsave(&uart->lock, flags); |
166 | |
167 | reg = ioread32(port->membase + addr); |
168 | reg &= ~val; |
169 | iowrite32(reg, port->membase + addr); |
170 | |
171 | spin_unlock_irqrestore(lock: &uart->lock, flags); |
172 | } |
173 | |
174 | /** |
175 | * men_z135_handle_modem_status() - Handle change of modem status |
176 | * @uart: The UART port |
177 | * |
178 | * Handle change of modem status register. This is done by reading the "delta" |
179 | * versions of DCD (Data Carrier Detect) and CTS (Clear To Send). |
180 | */ |
181 | static void men_z135_handle_modem_status(struct men_z135_port *uart) |
182 | { |
183 | u8 msr; |
184 | |
185 | msr = (uart->stat_reg >> 8) & 0xff; |
186 | |
187 | if (msr & MEN_Z135_MSR_DDCD) |
188 | uart_handle_dcd_change(uport: &uart->port, |
189 | active: msr & MEN_Z135_MSR_DCD); |
190 | if (msr & MEN_Z135_MSR_DCTS) |
191 | uart_handle_cts_change(uport: &uart->port, |
192 | active: msr & MEN_Z135_MSR_CTS); |
193 | } |
194 | |
195 | static void men_z135_handle_lsr(struct men_z135_port *uart) |
196 | { |
197 | struct uart_port *port = &uart->port; |
198 | u8 lsr; |
199 | |
200 | lsr = (uart->stat_reg >> 16) & 0xff; |
201 | |
202 | if (lsr & MEN_Z135_LSR_OE) |
203 | port->icount.overrun++; |
204 | if (lsr & MEN_Z135_LSR_PE) |
205 | port->icount.parity++; |
206 | if (lsr & MEN_Z135_LSR_FE) |
207 | port->icount.frame++; |
208 | if (lsr & MEN_Z135_LSR_BI) { |
209 | port->icount.brk++; |
210 | uart_handle_break(port); |
211 | } |
212 | } |
213 | |
214 | /** |
215 | * get_rx_fifo_content() - Get the number of bytes in RX FIFO |
216 | * @uart: The UART port |
217 | * |
218 | * Read RXC register from hardware and return current FIFO fill size. |
219 | */ |
220 | static u16 get_rx_fifo_content(struct men_z135_port *uart) |
221 | { |
222 | struct uart_port *port = &uart->port; |
223 | u32 stat_reg; |
224 | u16 rxc; |
225 | u8 rxc_lo; |
226 | u8 rxc_hi; |
227 | |
228 | stat_reg = ioread32(port->membase + MEN_Z135_STAT_REG); |
229 | rxc_lo = stat_reg >> 24; |
230 | rxc_hi = (stat_reg & 0xC0) >> 6; |
231 | |
232 | rxc = rxc_lo | (rxc_hi << 8); |
233 | |
234 | return rxc; |
235 | } |
236 | |
237 | /** |
238 | * men_z135_handle_rx() - RX tasklet routine |
239 | * @uart: Pointer to struct men_z135_port |
240 | * |
241 | * Copy from RX FIFO and acknowledge number of bytes copied. |
242 | */ |
243 | static void men_z135_handle_rx(struct men_z135_port *uart) |
244 | { |
245 | struct uart_port *port = &uart->port; |
246 | struct tty_port *tport = &port->state->port; |
247 | int copied; |
248 | u16 size; |
249 | int room; |
250 | |
251 | size = get_rx_fifo_content(uart); |
252 | |
253 | if (size == 0) |
254 | return; |
255 | |
256 | /* Avoid accidently accessing TX FIFO instead of RX FIFO. Last |
257 | * longword in RX FIFO cannot be read.(0x004-0x3FF) |
258 | */ |
259 | if (size > MEN_Z135_FIFO_WATERMARK) |
260 | size = MEN_Z135_FIFO_WATERMARK; |
261 | |
262 | room = tty_buffer_request_room(port: tport, size); |
263 | if (room != size) |
264 | dev_warn(&uart->mdev->dev, |
265 | "Not enough room in flip buffer, truncating to %d\n" , |
266 | room); |
267 | |
268 | if (room == 0) |
269 | return; |
270 | |
271 | memcpy_fromio(uart->rxbuf, port->membase + MEN_Z135_RX_RAM, room); |
272 | /* Be sure to first copy all data and then acknowledge it */ |
273 | mb(); |
274 | iowrite32(room, port->membase + MEN_Z135_RX_CTRL); |
275 | |
276 | copied = tty_insert_flip_string(port: tport, chars: uart->rxbuf, size: room); |
277 | if (copied != room) |
278 | dev_warn(&uart->mdev->dev, |
279 | "Only copied %d instead of %d bytes\n" , |
280 | copied, room); |
281 | |
282 | port->icount.rx += copied; |
283 | |
284 | tty_flip_buffer_push(port: tport); |
285 | |
286 | } |
287 | |
288 | /** |
289 | * men_z135_handle_tx() - TX tasklet routine |
290 | * @uart: Pointer to struct men_z135_port |
291 | * |
292 | */ |
293 | static void men_z135_handle_tx(struct men_z135_port *uart) |
294 | { |
295 | struct uart_port *port = &uart->port; |
296 | struct circ_buf *xmit = &port->state->xmit; |
297 | u32 txc; |
298 | u32 wptr; |
299 | int qlen; |
300 | int n; |
301 | int txfree; |
302 | int head; |
303 | int tail; |
304 | int s; |
305 | |
306 | if (uart_circ_empty(xmit)) |
307 | goto out; |
308 | |
309 | if (uart_tx_stopped(port)) |
310 | goto out; |
311 | |
312 | if (port->x_char) |
313 | goto out; |
314 | |
315 | /* calculate bytes to copy */ |
316 | qlen = uart_circ_chars_pending(xmit); |
317 | if (qlen <= 0) |
318 | goto out; |
319 | |
320 | wptr = ioread32(port->membase + MEN_Z135_TX_CTRL); |
321 | txc = (wptr >> 16) & 0x3ff; |
322 | wptr &= 0x3ff; |
323 | |
324 | if (txc > MEN_Z135_FIFO_WATERMARK) |
325 | txc = MEN_Z135_FIFO_WATERMARK; |
326 | |
327 | txfree = MEN_Z135_FIFO_WATERMARK - txc; |
328 | if (txfree <= 0) { |
329 | dev_err(&uart->mdev->dev, |
330 | "Not enough room in TX FIFO have %d, need %d\n" , |
331 | txfree, qlen); |
332 | goto irq_en; |
333 | } |
334 | |
335 | /* if we're not aligned, it's better to copy only 1 or 2 bytes and |
336 | * then the rest. |
337 | */ |
338 | if (align && qlen >= 3 && BYTES_TO_ALIGN(wptr)) |
339 | n = 4 - BYTES_TO_ALIGN(wptr); |
340 | else if (qlen > txfree) |
341 | n = txfree; |
342 | else |
343 | n = qlen; |
344 | |
345 | if (n <= 0) |
346 | goto irq_en; |
347 | |
348 | head = xmit->head & (UART_XMIT_SIZE - 1); |
349 | tail = xmit->tail & (UART_XMIT_SIZE - 1); |
350 | |
351 | s = ((head >= tail) ? head : UART_XMIT_SIZE) - tail; |
352 | n = min(n, s); |
353 | |
354 | memcpy_toio(port->membase + MEN_Z135_TX_RAM, &xmit->buf[xmit->tail], n); |
355 | iowrite32(n & 0x3ff, port->membase + MEN_Z135_TX_CTRL); |
356 | uart_xmit_advance(up: port, chars: n); |
357 | |
358 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
359 | uart_write_wakeup(port); |
360 | |
361 | irq_en: |
362 | if (!uart_circ_empty(xmit)) |
363 | men_z135_reg_set(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_TXCIEN); |
364 | else |
365 | men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_TXCIEN); |
366 | |
367 | out: |
368 | return; |
369 | |
370 | } |
371 | |
372 | /** |
373 | * men_z135_intr() - Handle legacy IRQs |
374 | * @irq: The IRQ number |
375 | * @data: Pointer to UART port |
376 | * |
377 | * Check IIR register to find the cause of the interrupt and handle it. |
378 | * It is possible that multiple interrupts reason bits are set and reading |
379 | * the IIR is a destructive read, so we always need to check for all possible |
380 | * interrupts and handle them. |
381 | */ |
382 | static irqreturn_t men_z135_intr(int irq, void *data) |
383 | { |
384 | struct men_z135_port *uart = (struct men_z135_port *)data; |
385 | struct uart_port *port = &uart->port; |
386 | bool handled = false; |
387 | int irq_id; |
388 | |
389 | uart->stat_reg = ioread32(port->membase + MEN_Z135_STAT_REG); |
390 | irq_id = IRQ_ID(uart->stat_reg); |
391 | |
392 | if (!irq_id) |
393 | goto out; |
394 | |
395 | uart_port_lock(up: port); |
396 | /* It's save to write to IIR[7:6] RXC[9:8] */ |
397 | iowrite8(irq_id, port->membase + MEN_Z135_STAT_REG); |
398 | |
399 | if (irq_id & MEN_Z135_IRQ_ID_RLS) { |
400 | men_z135_handle_lsr(uart); |
401 | handled = true; |
402 | } |
403 | |
404 | if (irq_id & (MEN_Z135_IRQ_ID_RDA | MEN_Z135_IRQ_ID_CTI)) { |
405 | if (irq_id & MEN_Z135_IRQ_ID_CTI) |
406 | dev_dbg(&uart->mdev->dev, "Character Timeout Indication\n" ); |
407 | men_z135_handle_rx(uart); |
408 | handled = true; |
409 | } |
410 | |
411 | if (irq_id & MEN_Z135_IRQ_ID_TSA) { |
412 | men_z135_handle_tx(uart); |
413 | handled = true; |
414 | } |
415 | |
416 | if (irq_id & MEN_Z135_IRQ_ID_MST) { |
417 | men_z135_handle_modem_status(uart); |
418 | handled = true; |
419 | } |
420 | |
421 | uart_port_unlock(up: port); |
422 | out: |
423 | return IRQ_RETVAL(handled); |
424 | } |
425 | |
426 | /** |
427 | * men_z135_request_irq() - Request IRQ for 16z135 core |
428 | * @uart: z135 private uart port structure |
429 | * |
430 | * Request an IRQ for 16z135 to use. First try using MSI, if it fails |
431 | * fall back to using legacy interrupts. |
432 | */ |
433 | static int men_z135_request_irq(struct men_z135_port *uart) |
434 | { |
435 | struct device *dev = &uart->mdev->dev; |
436 | struct uart_port *port = &uart->port; |
437 | int err = 0; |
438 | |
439 | err = request_irq(irq: port->irq, handler: men_z135_intr, IRQF_SHARED, |
440 | name: "men_z135_intr" , dev: uart); |
441 | if (err) |
442 | dev_err(dev, "Error %d getting interrupt\n" , err); |
443 | |
444 | return err; |
445 | } |
446 | |
447 | /** |
448 | * men_z135_tx_empty() - Handle tx_empty call |
449 | * @port: The UART port |
450 | * |
451 | * This function tests whether the TX FIFO and shifter for the port |
452 | * described by @port is empty. |
453 | */ |
454 | static unsigned int men_z135_tx_empty(struct uart_port *port) |
455 | { |
456 | u32 wptr; |
457 | u16 txc; |
458 | |
459 | wptr = ioread32(port->membase + MEN_Z135_TX_CTRL); |
460 | txc = (wptr >> 16) & 0x3ff; |
461 | |
462 | if (txc == 0) |
463 | return TIOCSER_TEMT; |
464 | else |
465 | return 0; |
466 | } |
467 | |
468 | /** |
469 | * men_z135_set_mctrl() - Set modem control lines |
470 | * @port: The UART port |
471 | * @mctrl: The modem control lines |
472 | * |
473 | * This function sets the modem control lines for a port described by @port |
474 | * to the state described by @mctrl |
475 | */ |
476 | static void men_z135_set_mctrl(struct uart_port *port, unsigned int mctrl) |
477 | { |
478 | u32 old; |
479 | u32 conf_reg; |
480 | |
481 | conf_reg = old = ioread32(port->membase + MEN_Z135_CONF_REG); |
482 | if (mctrl & TIOCM_RTS) |
483 | conf_reg |= MEN_Z135_MCR_RTS; |
484 | else |
485 | conf_reg &= ~MEN_Z135_MCR_RTS; |
486 | |
487 | if (mctrl & TIOCM_DTR) |
488 | conf_reg |= MEN_Z135_MCR_DTR; |
489 | else |
490 | conf_reg &= ~MEN_Z135_MCR_DTR; |
491 | |
492 | if (mctrl & TIOCM_OUT1) |
493 | conf_reg |= MEN_Z135_MCR_OUT1; |
494 | else |
495 | conf_reg &= ~MEN_Z135_MCR_OUT1; |
496 | |
497 | if (mctrl & TIOCM_OUT2) |
498 | conf_reg |= MEN_Z135_MCR_OUT2; |
499 | else |
500 | conf_reg &= ~MEN_Z135_MCR_OUT2; |
501 | |
502 | if (mctrl & TIOCM_LOOP) |
503 | conf_reg |= MEN_Z135_MCR_LOOP; |
504 | else |
505 | conf_reg &= ~MEN_Z135_MCR_LOOP; |
506 | |
507 | if (conf_reg != old) |
508 | iowrite32(conf_reg, port->membase + MEN_Z135_CONF_REG); |
509 | } |
510 | |
511 | /** |
512 | * men_z135_get_mctrl() - Get modem control lines |
513 | * @port: The UART port |
514 | * |
515 | * Retruns the current state of modem control inputs. |
516 | */ |
517 | static unsigned int men_z135_get_mctrl(struct uart_port *port) |
518 | { |
519 | unsigned int mctrl = 0; |
520 | u8 msr; |
521 | |
522 | msr = ioread8(port->membase + MEN_Z135_STAT_REG + 1); |
523 | |
524 | if (msr & MEN_Z135_MSR_CTS) |
525 | mctrl |= TIOCM_CTS; |
526 | if (msr & MEN_Z135_MSR_DSR) |
527 | mctrl |= TIOCM_DSR; |
528 | if (msr & MEN_Z135_MSR_RI) |
529 | mctrl |= TIOCM_RI; |
530 | if (msr & MEN_Z135_MSR_DCD) |
531 | mctrl |= TIOCM_CAR; |
532 | |
533 | return mctrl; |
534 | } |
535 | |
536 | /** |
537 | * men_z135_stop_tx() - Stop transmitting characters |
538 | * @port: The UART port |
539 | * |
540 | * Stop transmitting characters. This might be due to CTS line becomming |
541 | * inactive or the tty layer indicating we want to stop transmission due to |
542 | * an XOFF character. |
543 | */ |
544 | static void men_z135_stop_tx(struct uart_port *port) |
545 | { |
546 | struct men_z135_port *uart = to_men_z135(port); |
547 | |
548 | men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_TXCIEN); |
549 | } |
550 | |
551 | /* |
552 | * men_z135_disable_ms() - Disable Modem Status |
553 | * port: The UART port |
554 | * |
555 | * Enable Modem Status IRQ. |
556 | */ |
557 | static void men_z135_disable_ms(struct uart_port *port) |
558 | { |
559 | struct men_z135_port *uart = to_men_z135(port); |
560 | |
561 | men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_MSIEN); |
562 | } |
563 | |
564 | /** |
565 | * men_z135_start_tx() - Start transmitting characters |
566 | * @port: The UART port |
567 | * |
568 | * Start transmitting character. This actually doesn't transmit anything, but |
569 | * fires off the TX tasklet. |
570 | */ |
571 | static void men_z135_start_tx(struct uart_port *port) |
572 | { |
573 | struct men_z135_port *uart = to_men_z135(port); |
574 | |
575 | if (uart->automode) |
576 | men_z135_disable_ms(port); |
577 | |
578 | men_z135_handle_tx(uart); |
579 | } |
580 | |
581 | /** |
582 | * men_z135_stop_rx() - Stop receiving characters |
583 | * @port: The UART port |
584 | * |
585 | * Stop receiving characters; the port is in the process of being closed. |
586 | */ |
587 | static void men_z135_stop_rx(struct uart_port *port) |
588 | { |
589 | struct men_z135_port *uart = to_men_z135(port); |
590 | |
591 | men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_RXCIEN); |
592 | } |
593 | |
594 | /** |
595 | * men_z135_enable_ms() - Enable Modem Status |
596 | * @port: the port |
597 | * |
598 | * Enable Modem Status IRQ. |
599 | */ |
600 | static void men_z135_enable_ms(struct uart_port *port) |
601 | { |
602 | struct men_z135_port *uart = to_men_z135(port); |
603 | |
604 | men_z135_reg_set(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_MSIEN); |
605 | } |
606 | |
607 | static int men_z135_startup(struct uart_port *port) |
608 | { |
609 | struct men_z135_port *uart = to_men_z135(port); |
610 | int err; |
611 | u32 conf_reg = 0; |
612 | |
613 | err = men_z135_request_irq(uart); |
614 | if (err) |
615 | return -ENODEV; |
616 | |
617 | conf_reg = ioread32(port->membase + MEN_Z135_CONF_REG); |
618 | |
619 | /* Activate all but TX space available IRQ */ |
620 | conf_reg |= MEN_Z135_ALL_IRQS & ~MEN_Z135_IER_TXCIEN; |
621 | conf_reg &= ~(0xff << 16); |
622 | conf_reg |= (txlvl << 16); |
623 | conf_reg |= (rxlvl << 20); |
624 | |
625 | iowrite32(conf_reg, port->membase + MEN_Z135_CONF_REG); |
626 | |
627 | if (rx_timeout) |
628 | iowrite32(rx_timeout, port->membase + MEN_Z135_TIMEOUT); |
629 | |
630 | return 0; |
631 | } |
632 | |
633 | static void men_z135_shutdown(struct uart_port *port) |
634 | { |
635 | struct men_z135_port *uart = to_men_z135(port); |
636 | u32 conf_reg = 0; |
637 | |
638 | conf_reg |= MEN_Z135_ALL_IRQS; |
639 | |
640 | men_z135_reg_clr(uart, MEN_Z135_CONF_REG, val: conf_reg); |
641 | |
642 | free_irq(uart->port.irq, uart); |
643 | } |
644 | |
645 | static void men_z135_set_termios(struct uart_port *port, |
646 | struct ktermios *termios, |
647 | const struct ktermios *old) |
648 | { |
649 | struct men_z135_port *uart = to_men_z135(port); |
650 | unsigned int baud; |
651 | u32 conf_reg; |
652 | u32 bd_reg; |
653 | u32 uart_freq; |
654 | u8 lcr; |
655 | |
656 | conf_reg = ioread32(port->membase + MEN_Z135_CONF_REG); |
657 | lcr = LCR(conf_reg); |
658 | |
659 | /* byte size */ |
660 | switch (termios->c_cflag & CSIZE) { |
661 | case CS5: |
662 | lcr |= MEN_Z135_WL5; |
663 | break; |
664 | case CS6: |
665 | lcr |= MEN_Z135_WL6; |
666 | break; |
667 | case CS7: |
668 | lcr |= MEN_Z135_WL7; |
669 | break; |
670 | case CS8: |
671 | lcr |= MEN_Z135_WL8; |
672 | break; |
673 | } |
674 | |
675 | /* stop bits */ |
676 | if (termios->c_cflag & CSTOPB) |
677 | lcr |= MEN_Z135_NSTB2 << MEN_Z135_STB_SHIFT; |
678 | |
679 | /* parity */ |
680 | if (termios->c_cflag & PARENB) { |
681 | lcr |= MEN_Z135_PAR_ENA << MEN_Z135_PEN_SHIFT; |
682 | |
683 | if (termios->c_cflag & PARODD) |
684 | lcr |= MEN_Z135_PTY_ODD << MEN_Z135_PTY_SHIFT; |
685 | else |
686 | lcr |= MEN_Z135_PTY_EVN << MEN_Z135_PTY_SHIFT; |
687 | } else |
688 | lcr |= MEN_Z135_PAR_DIS << MEN_Z135_PEN_SHIFT; |
689 | |
690 | conf_reg |= MEN_Z135_IER_MSIEN; |
691 | if (termios->c_cflag & CRTSCTS) { |
692 | conf_reg |= MEN_Z135_MCR_RCFC; |
693 | uart->automode = true; |
694 | termios->c_cflag &= ~CLOCAL; |
695 | } else { |
696 | conf_reg &= ~MEN_Z135_MCR_RCFC; |
697 | uart->automode = false; |
698 | } |
699 | |
700 | termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ |
701 | |
702 | conf_reg |= lcr << MEN_Z135_LCR_SHIFT; |
703 | iowrite32(conf_reg, port->membase + MEN_Z135_CONF_REG); |
704 | |
705 | uart_freq = ioread32(port->membase + MEN_Z135_UART_FREQ); |
706 | if (uart_freq == 0) |
707 | uart_freq = MEN_Z135_BASECLK; |
708 | |
709 | baud = uart_get_baud_rate(port, termios, old, min: 0, max: uart_freq / 16); |
710 | |
711 | uart_port_lock_irq(up: port); |
712 | if (tty_termios_baud_rate(termios)) |
713 | tty_termios_encode_baud_rate(termios, ibaud: baud, obaud: baud); |
714 | |
715 | bd_reg = uart_freq / (4 * baud); |
716 | iowrite32(bd_reg, port->membase + MEN_Z135_BAUD_REG); |
717 | |
718 | uart_update_timeout(port, cflag: termios->c_cflag, baud); |
719 | uart_port_unlock_irq(up: port); |
720 | } |
721 | |
722 | static const char *men_z135_type(struct uart_port *port) |
723 | { |
724 | return KBUILD_MODNAME; |
725 | } |
726 | |
727 | static void men_z135_release_port(struct uart_port *port) |
728 | { |
729 | struct men_z135_port *uart = to_men_z135(port); |
730 | |
731 | iounmap(addr: port->membase); |
732 | port->membase = NULL; |
733 | |
734 | mcb_release_mem(mem: uart->mem); |
735 | } |
736 | |
737 | static int men_z135_request_port(struct uart_port *port) |
738 | { |
739 | struct men_z135_port *uart = to_men_z135(port); |
740 | struct mcb_device *mdev = uart->mdev; |
741 | struct resource *mem; |
742 | |
743 | mem = mcb_request_mem(dev: uart->mdev, name: dev_name(dev: &mdev->dev)); |
744 | if (IS_ERR(ptr: mem)) |
745 | return PTR_ERR(ptr: mem); |
746 | |
747 | port->mapbase = mem->start; |
748 | uart->mem = mem; |
749 | |
750 | port->membase = ioremap(offset: mem->start, size: resource_size(res: mem)); |
751 | if (port->membase == NULL) { |
752 | mcb_release_mem(mem); |
753 | return -ENOMEM; |
754 | } |
755 | |
756 | return 0; |
757 | } |
758 | |
759 | static void men_z135_config_port(struct uart_port *port, int type) |
760 | { |
761 | port->type = PORT_MEN_Z135; |
762 | men_z135_request_port(port); |
763 | } |
764 | |
765 | static int men_z135_verify_port(struct uart_port *port, |
766 | struct serial_struct *serinfo) |
767 | { |
768 | return -EINVAL; |
769 | } |
770 | |
771 | static const struct uart_ops men_z135_ops = { |
772 | .tx_empty = men_z135_tx_empty, |
773 | .set_mctrl = men_z135_set_mctrl, |
774 | .get_mctrl = men_z135_get_mctrl, |
775 | .stop_tx = men_z135_stop_tx, |
776 | .start_tx = men_z135_start_tx, |
777 | .stop_rx = men_z135_stop_rx, |
778 | .enable_ms = men_z135_enable_ms, |
779 | .startup = men_z135_startup, |
780 | .shutdown = men_z135_shutdown, |
781 | .set_termios = men_z135_set_termios, |
782 | .type = men_z135_type, |
783 | .release_port = men_z135_release_port, |
784 | .request_port = men_z135_request_port, |
785 | .config_port = men_z135_config_port, |
786 | .verify_port = men_z135_verify_port, |
787 | }; |
788 | |
789 | static struct uart_driver men_z135_driver = { |
790 | .owner = THIS_MODULE, |
791 | .driver_name = KBUILD_MODNAME, |
792 | .dev_name = "ttyHSU" , |
793 | .major = 0, |
794 | .minor = 0, |
795 | .nr = MEN_Z135_MAX_PORTS, |
796 | }; |
797 | |
798 | /** |
799 | * men_z135_probe() - Probe a z135 instance |
800 | * @mdev: The MCB device |
801 | * @id: The MCB device ID |
802 | * |
803 | * men_z135_probe does the basic setup of hardware resources and registers the |
804 | * new uart port to the tty layer. |
805 | */ |
806 | static int men_z135_probe(struct mcb_device *mdev, |
807 | const struct mcb_device_id *id) |
808 | { |
809 | struct men_z135_port *uart; |
810 | struct resource *mem; |
811 | struct device *dev; |
812 | int err; |
813 | |
814 | dev = &mdev->dev; |
815 | |
816 | uart = devm_kzalloc(dev, size: sizeof(struct men_z135_port), GFP_KERNEL); |
817 | if (!uart) |
818 | return -ENOMEM; |
819 | |
820 | uart->rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL); |
821 | if (!uart->rxbuf) |
822 | return -ENOMEM; |
823 | |
824 | mem = &mdev->mem; |
825 | |
826 | mcb_set_drvdata(dev: mdev, data: uart); |
827 | |
828 | uart->port.uartclk = MEN_Z135_BASECLK * 16; |
829 | uart->port.fifosize = MEN_Z135_FIFO_SIZE; |
830 | uart->port.iotype = UPIO_MEM; |
831 | uart->port.ops = &men_z135_ops; |
832 | uart->port.irq = mcb_get_irq(dev: mdev); |
833 | uart->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP; |
834 | uart->port.line = line++; |
835 | uart->port.dev = dev; |
836 | uart->port.type = PORT_MEN_Z135; |
837 | uart->port.mapbase = mem->start; |
838 | uart->port.membase = NULL; |
839 | uart->mdev = mdev; |
840 | |
841 | spin_lock_init(&uart->lock); |
842 | |
843 | err = uart_add_one_port(reg: &men_z135_driver, port: &uart->port); |
844 | if (err) |
845 | goto err; |
846 | |
847 | return 0; |
848 | |
849 | err: |
850 | free_page((unsigned long) uart->rxbuf); |
851 | dev_err(dev, "Failed to add UART: %d\n" , err); |
852 | |
853 | return err; |
854 | } |
855 | |
856 | /** |
857 | * men_z135_remove() - Remove a z135 instance from the system |
858 | * |
859 | * @mdev: The MCB device |
860 | */ |
861 | static void men_z135_remove(struct mcb_device *mdev) |
862 | { |
863 | struct men_z135_port *uart = mcb_get_drvdata(dev: mdev); |
864 | |
865 | line--; |
866 | uart_remove_one_port(reg: &men_z135_driver, port: &uart->port); |
867 | free_page((unsigned long) uart->rxbuf); |
868 | } |
869 | |
870 | static const struct mcb_device_id men_z135_ids[] = { |
871 | { .device = 0x87 }, |
872 | { } |
873 | }; |
874 | MODULE_DEVICE_TABLE(mcb, men_z135_ids); |
875 | |
876 | static struct mcb_driver mcb_driver = { |
877 | .driver = { |
878 | .name = "z135-uart" , |
879 | .owner = THIS_MODULE, |
880 | }, |
881 | .probe = men_z135_probe, |
882 | .remove = men_z135_remove, |
883 | .id_table = men_z135_ids, |
884 | }; |
885 | |
886 | /** |
887 | * men_z135_init() - Driver Registration Routine |
888 | * |
889 | * men_z135_init is the first routine called when the driver is loaded. All it |
890 | * does is register with the legacy MEN Chameleon subsystem. |
891 | */ |
892 | static int __init men_z135_init(void) |
893 | { |
894 | int err; |
895 | |
896 | err = uart_register_driver(uart: &men_z135_driver); |
897 | if (err) { |
898 | pr_err("Failed to register UART: %d\n" , err); |
899 | return err; |
900 | } |
901 | |
902 | err = mcb_register_driver(&mcb_driver); |
903 | if (err) { |
904 | pr_err("Failed to register MCB driver: %d\n" , err); |
905 | uart_unregister_driver(uart: &men_z135_driver); |
906 | return err; |
907 | } |
908 | |
909 | return 0; |
910 | } |
911 | module_init(men_z135_init); |
912 | |
913 | /** |
914 | * men_z135_exit() - Driver Exit Routine |
915 | * |
916 | * men_z135_exit is called just before the driver is removed from memory. |
917 | */ |
918 | static void __exit men_z135_exit(void) |
919 | { |
920 | mcb_unregister_driver(driver: &mcb_driver); |
921 | uart_unregister_driver(uart: &men_z135_driver); |
922 | } |
923 | module_exit(men_z135_exit); |
924 | |
925 | MODULE_AUTHOR("Johannes Thumshirn <johannes.thumshirn@men.de>" ); |
926 | MODULE_LICENSE("GPL v2" ); |
927 | MODULE_DESCRIPTION("MEN 16z135 High Speed UART" ); |
928 | MODULE_ALIAS("mcb:16z135" ); |
929 | MODULE_IMPORT_NS(MCB); |
930 | |