1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs. |
4 | * |
5 | * FIXME According to the usermanual the status bits in the status register |
6 | * are only updated when the peripherals access the FIFO and not when the |
7 | * CPU access them. So since we use this bits to know when we stop writing |
8 | * and reading, they may not be updated in-time and a race condition may |
9 | * exists. But I haven't be able to prove this and I don't care. But if |
10 | * any problem arises, it might worth checking. The TX/RX FIFO Stats |
11 | * registers should be used in addition. |
12 | * Update: Actually, they seem updated ... At least the bits we use. |
13 | * |
14 | * |
15 | * Maintainer : Sylvain Munaut <tnt@246tNt.com> |
16 | * |
17 | * Some of the code has been inspired/copied from the 2.4 code written |
18 | * by Dale Farnsworth <dfarnsworth@mvista.com>. |
19 | * |
20 | * Copyright (C) 2008 Freescale Semiconductor Inc. |
21 | * John Rigby <jrigby@gmail.com> |
22 | * Added support for MPC5121 |
23 | * Copyright (C) 2006 Secret Lab Technologies Ltd. |
24 | * Grant Likely <grant.likely@secretlab.ca> |
25 | * Copyright (C) 2004-2006 Sylvain Munaut <tnt@246tNt.com> |
26 | * Copyright (C) 2003 MontaVista, Software, Inc. |
27 | */ |
28 | |
29 | #undef DEBUG |
30 | |
31 | #include <linux/device.h> |
32 | #include <linux/module.h> |
33 | #include <linux/tty.h> |
34 | #include <linux/tty_flip.h> |
35 | #include <linux/serial.h> |
36 | #include <linux/sysrq.h> |
37 | #include <linux/console.h> |
38 | #include <linux/delay.h> |
39 | #include <linux/io.h> |
40 | #include <linux/of.h> |
41 | #include <linux/of_address.h> |
42 | #include <linux/of_irq.h> |
43 | #include <linux/platform_device.h> |
44 | #include <linux/clk.h> |
45 | |
46 | #include <asm/mpc52xx.h> |
47 | #include <asm/mpc52xx_psc.h> |
48 | |
49 | #include <linux/serial_core.h> |
50 | |
51 | |
52 | /* We've been assigned a range on the "Low-density serial ports" major */ |
53 | #define SERIAL_PSC_MAJOR 204 |
54 | #define SERIAL_PSC_MINOR 148 |
55 | |
56 | |
57 | #define ISR_PASS_LIMIT 256 /* Max number of iteration in the interrupt */ |
58 | |
59 | |
60 | static struct uart_port mpc52xx_uart_ports[MPC52xx_PSC_MAXNUM]; |
61 | /* Rem: - We use the read_status_mask as a shadow of |
62 | * psc->mpc52xx_psc_imr |
63 | * - It's important that is array is all zero on start as we |
64 | * use it to know if it's initialized or not ! If it's not sure |
65 | * it's cleared, then a memset(...,0,...) should be added to |
66 | * the console_init |
67 | */ |
68 | |
69 | /* lookup table for matching device nodes to index numbers */ |
70 | static struct device_node *mpc52xx_uart_nodes[MPC52xx_PSC_MAXNUM]; |
71 | |
72 | static void mpc52xx_uart_of_enumerate(void); |
73 | |
74 | |
75 | #define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase)) |
76 | |
77 | |
78 | /* Forward declaration of the interruption handling routine */ |
79 | static irqreturn_t mpc52xx_uart_int(int irq, void *dev_id); |
80 | static irqreturn_t mpc5xxx_uart_process_int(struct uart_port *port); |
81 | |
82 | /* ======================================================================== */ |
83 | /* PSC fifo operations for isolating differences between 52xx and 512x */ |
84 | /* ======================================================================== */ |
85 | |
86 | struct psc_ops { |
87 | void (*fifo_init)(struct uart_port *port); |
88 | unsigned int (*raw_rx_rdy)(struct uart_port *port); |
89 | unsigned int (*raw_tx_rdy)(struct uart_port *port); |
90 | unsigned int (*rx_rdy)(struct uart_port *port); |
91 | unsigned int (*tx_rdy)(struct uart_port *port); |
92 | unsigned int (*tx_empty)(struct uart_port *port); |
93 | void (*stop_rx)(struct uart_port *port); |
94 | void (*start_tx)(struct uart_port *port); |
95 | void (*stop_tx)(struct uart_port *port); |
96 | void (*rx_clr_irq)(struct uart_port *port); |
97 | void (*tx_clr_irq)(struct uart_port *port); |
98 | void (*write_char)(struct uart_port *port, unsigned char c); |
99 | unsigned char (*read_char)(struct uart_port *port); |
100 | void (*cw_disable_ints)(struct uart_port *port); |
101 | void (*cw_restore_ints)(struct uart_port *port); |
102 | unsigned int (*set_baudrate)(struct uart_port *port, |
103 | struct ktermios *new, |
104 | const struct ktermios *old); |
105 | int (*clock_alloc)(struct uart_port *port); |
106 | void (*clock_relse)(struct uart_port *port); |
107 | int (*clock)(struct uart_port *port, int enable); |
108 | int (*fifoc_init)(void); |
109 | void (*fifoc_uninit)(void); |
110 | void (*get_irq)(struct uart_port *, struct device_node *); |
111 | irqreturn_t (*handle_irq)(struct uart_port *port); |
112 | u16 (*get_status)(struct uart_port *port); |
113 | u8 (*get_ipcr)(struct uart_port *port); |
114 | void (*command)(struct uart_port *port, u8 cmd); |
115 | void (*set_mode)(struct uart_port *port, u8 mr1, u8 mr2); |
116 | void (*set_rts)(struct uart_port *port, int state); |
117 | void (*enable_ms)(struct uart_port *port); |
118 | void (*set_sicr)(struct uart_port *port, u32 val); |
119 | void (*set_imr)(struct uart_port *port, u16 val); |
120 | u8 (*get_mr1)(struct uart_port *port); |
121 | }; |
122 | |
123 | /* setting the prescaler and divisor reg is common for all chips */ |
124 | static inline void mpc52xx_set_divisor(struct mpc52xx_psc __iomem *psc, |
125 | u16 prescaler, unsigned int divisor) |
126 | { |
127 | /* select prescaler */ |
128 | out_be16(&psc->mpc52xx_psc_clock_select, prescaler); |
129 | out_8(&psc->ctur, divisor >> 8); |
130 | out_8(&psc->ctlr, divisor & 0xff); |
131 | } |
132 | |
133 | static u16 mpc52xx_psc_get_status(struct uart_port *port) |
134 | { |
135 | return in_be16(&PSC(port)->mpc52xx_psc_status); |
136 | } |
137 | |
138 | static u8 mpc52xx_psc_get_ipcr(struct uart_port *port) |
139 | { |
140 | return in_8(&PSC(port)->mpc52xx_psc_ipcr); |
141 | } |
142 | |
143 | static void mpc52xx_psc_command(struct uart_port *port, u8 cmd) |
144 | { |
145 | out_8(&PSC(port)->command, cmd); |
146 | } |
147 | |
148 | static void mpc52xx_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2) |
149 | { |
150 | out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1); |
151 | out_8(&PSC(port)->mode, mr1); |
152 | out_8(&PSC(port)->mode, mr2); |
153 | } |
154 | |
155 | static void mpc52xx_psc_set_rts(struct uart_port *port, int state) |
156 | { |
157 | if (state) |
158 | out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS); |
159 | else |
160 | out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS); |
161 | } |
162 | |
163 | static void mpc52xx_psc_enable_ms(struct uart_port *port) |
164 | { |
165 | struct mpc52xx_psc __iomem *psc = PSC(port); |
166 | |
167 | /* clear D_*-bits by reading them */ |
168 | in_8(&psc->mpc52xx_psc_ipcr); |
169 | /* enable CTS and DCD as IPC interrupts */ |
170 | out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD); |
171 | |
172 | port->read_status_mask |= MPC52xx_PSC_IMR_IPC; |
173 | out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); |
174 | } |
175 | |
176 | static void mpc52xx_psc_set_sicr(struct uart_port *port, u32 val) |
177 | { |
178 | out_be32(&PSC(port)->sicr, val); |
179 | } |
180 | |
181 | static void mpc52xx_psc_set_imr(struct uart_port *port, u16 val) |
182 | { |
183 | out_be16(&PSC(port)->mpc52xx_psc_imr, val); |
184 | } |
185 | |
186 | static u8 mpc52xx_psc_get_mr1(struct uart_port *port) |
187 | { |
188 | out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1); |
189 | return in_8(&PSC(port)->mode); |
190 | } |
191 | |
192 | #ifdef CONFIG_PPC_MPC52xx |
193 | #define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1)) |
194 | static void mpc52xx_psc_fifo_init(struct uart_port *port) |
195 | { |
196 | struct mpc52xx_psc __iomem *psc = PSC(port); |
197 | struct mpc52xx_psc_fifo __iomem *fifo = FIFO_52xx(port); |
198 | |
199 | out_8(&fifo->rfcntl, 0x00); |
200 | out_be16(&fifo->rfalarm, 0x1ff); |
201 | out_8(&fifo->tfcntl, 0x07); |
202 | out_be16(&fifo->tfalarm, 0x80); |
203 | |
204 | port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY; |
205 | out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); |
206 | } |
207 | |
208 | static unsigned int mpc52xx_psc_raw_rx_rdy(struct uart_port *port) |
209 | { |
210 | return in_be16(&PSC(port)->mpc52xx_psc_status) |
211 | & MPC52xx_PSC_SR_RXRDY; |
212 | } |
213 | |
214 | static unsigned int mpc52xx_psc_raw_tx_rdy(struct uart_port *port) |
215 | { |
216 | return in_be16(&PSC(port)->mpc52xx_psc_status) |
217 | & MPC52xx_PSC_SR_TXRDY; |
218 | } |
219 | |
220 | |
221 | static unsigned int mpc52xx_psc_rx_rdy(struct uart_port *port) |
222 | { |
223 | return in_be16(&PSC(port)->mpc52xx_psc_isr) |
224 | & port->read_status_mask |
225 | & MPC52xx_PSC_IMR_RXRDY; |
226 | } |
227 | |
228 | static unsigned int mpc52xx_psc_tx_rdy(struct uart_port *port) |
229 | { |
230 | return in_be16(&PSC(port)->mpc52xx_psc_isr) |
231 | & port->read_status_mask |
232 | & MPC52xx_PSC_IMR_TXRDY; |
233 | } |
234 | |
235 | static unsigned int mpc52xx_psc_tx_empty(struct uart_port *port) |
236 | { |
237 | u16 sts = in_be16(&PSC(port)->mpc52xx_psc_status); |
238 | |
239 | return (sts & MPC52xx_PSC_SR_TXEMP) ? TIOCSER_TEMT : 0; |
240 | } |
241 | |
242 | static void mpc52xx_psc_start_tx(struct uart_port *port) |
243 | { |
244 | port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY; |
245 | out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); |
246 | } |
247 | |
248 | static void mpc52xx_psc_stop_tx(struct uart_port *port) |
249 | { |
250 | port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY; |
251 | out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); |
252 | } |
253 | |
254 | static void mpc52xx_psc_stop_rx(struct uart_port *port) |
255 | { |
256 | port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY; |
257 | out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); |
258 | } |
259 | |
260 | static void mpc52xx_psc_rx_clr_irq(struct uart_port *port) |
261 | { |
262 | } |
263 | |
264 | static void mpc52xx_psc_tx_clr_irq(struct uart_port *port) |
265 | { |
266 | } |
267 | |
268 | static void mpc52xx_psc_write_char(struct uart_port *port, unsigned char c) |
269 | { |
270 | out_8(&PSC(port)->mpc52xx_psc_buffer_8, c); |
271 | } |
272 | |
273 | static unsigned char mpc52xx_psc_read_char(struct uart_port *port) |
274 | { |
275 | return in_8(&PSC(port)->mpc52xx_psc_buffer_8); |
276 | } |
277 | |
278 | static void mpc52xx_psc_cw_disable_ints(struct uart_port *port) |
279 | { |
280 | out_be16(&PSC(port)->mpc52xx_psc_imr, 0); |
281 | } |
282 | |
283 | static void mpc52xx_psc_cw_restore_ints(struct uart_port *port) |
284 | { |
285 | out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); |
286 | } |
287 | |
288 | static unsigned int mpc5200_psc_set_baudrate(struct uart_port *port, |
289 | struct ktermios *new, |
290 | const struct ktermios *old) |
291 | { |
292 | unsigned int baud; |
293 | unsigned int divisor; |
294 | |
295 | /* The 5200 has a fixed /32 prescaler, uartclk contains the ipb freq */ |
296 | baud = uart_get_baud_rate(port, new, old, |
297 | port->uartclk / (32 * 0xffff) + 1, |
298 | port->uartclk / 32); |
299 | divisor = (port->uartclk + 16 * baud) / (32 * baud); |
300 | |
301 | /* enable the /32 prescaler and set the divisor */ |
302 | mpc52xx_set_divisor(PSC(port), 0xdd00, divisor); |
303 | return baud; |
304 | } |
305 | |
306 | static unsigned int mpc5200b_psc_set_baudrate(struct uart_port *port, |
307 | struct ktermios *new, |
308 | const struct ktermios *old) |
309 | { |
310 | unsigned int baud; |
311 | unsigned int divisor; |
312 | u16 prescaler; |
313 | |
314 | /* The 5200B has a selectable /4 or /32 prescaler, uartclk contains the |
315 | * ipb freq */ |
316 | baud = uart_get_baud_rate(port, new, old, |
317 | port->uartclk / (32 * 0xffff) + 1, |
318 | port->uartclk / 4); |
319 | divisor = (port->uartclk + 2 * baud) / (4 * baud); |
320 | |
321 | /* select the proper prescaler and set the divisor |
322 | * prefer high prescaler for more tolerance on low baudrates */ |
323 | if (divisor > 0xffff || baud <= 115200) { |
324 | divisor = (divisor + 4) / 8; |
325 | prescaler = 0xdd00; /* /32 */ |
326 | } else |
327 | prescaler = 0xff00; /* /4 */ |
328 | mpc52xx_set_divisor(PSC(port), prescaler, divisor); |
329 | return baud; |
330 | } |
331 | |
332 | static void mpc52xx_psc_get_irq(struct uart_port *port, struct device_node *np) |
333 | { |
334 | port->irqflags = 0; |
335 | port->irq = irq_of_parse_and_map(np, 0); |
336 | } |
337 | |
338 | /* 52xx specific interrupt handler. The caller holds the port lock */ |
339 | static irqreturn_t mpc52xx_psc_handle_irq(struct uart_port *port) |
340 | { |
341 | return mpc5xxx_uart_process_int(port); |
342 | } |
343 | |
344 | static const struct psc_ops mpc52xx_psc_ops = { |
345 | .fifo_init = mpc52xx_psc_fifo_init, |
346 | .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy, |
347 | .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy, |
348 | .rx_rdy = mpc52xx_psc_rx_rdy, |
349 | .tx_rdy = mpc52xx_psc_tx_rdy, |
350 | .tx_empty = mpc52xx_psc_tx_empty, |
351 | .stop_rx = mpc52xx_psc_stop_rx, |
352 | .start_tx = mpc52xx_psc_start_tx, |
353 | .stop_tx = mpc52xx_psc_stop_tx, |
354 | .rx_clr_irq = mpc52xx_psc_rx_clr_irq, |
355 | .tx_clr_irq = mpc52xx_psc_tx_clr_irq, |
356 | .write_char = mpc52xx_psc_write_char, |
357 | .read_char = mpc52xx_psc_read_char, |
358 | .cw_disable_ints = mpc52xx_psc_cw_disable_ints, |
359 | .cw_restore_ints = mpc52xx_psc_cw_restore_ints, |
360 | .set_baudrate = mpc5200_psc_set_baudrate, |
361 | .get_irq = mpc52xx_psc_get_irq, |
362 | .handle_irq = mpc52xx_psc_handle_irq, |
363 | .get_status = mpc52xx_psc_get_status, |
364 | .get_ipcr = mpc52xx_psc_get_ipcr, |
365 | .command = mpc52xx_psc_command, |
366 | .set_mode = mpc52xx_psc_set_mode, |
367 | .set_rts = mpc52xx_psc_set_rts, |
368 | .enable_ms = mpc52xx_psc_enable_ms, |
369 | .set_sicr = mpc52xx_psc_set_sicr, |
370 | .set_imr = mpc52xx_psc_set_imr, |
371 | .get_mr1 = mpc52xx_psc_get_mr1, |
372 | }; |
373 | |
374 | static const struct psc_ops mpc5200b_psc_ops = { |
375 | .fifo_init = mpc52xx_psc_fifo_init, |
376 | .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy, |
377 | .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy, |
378 | .rx_rdy = mpc52xx_psc_rx_rdy, |
379 | .tx_rdy = mpc52xx_psc_tx_rdy, |
380 | .tx_empty = mpc52xx_psc_tx_empty, |
381 | .stop_rx = mpc52xx_psc_stop_rx, |
382 | .start_tx = mpc52xx_psc_start_tx, |
383 | .stop_tx = mpc52xx_psc_stop_tx, |
384 | .rx_clr_irq = mpc52xx_psc_rx_clr_irq, |
385 | .tx_clr_irq = mpc52xx_psc_tx_clr_irq, |
386 | .write_char = mpc52xx_psc_write_char, |
387 | .read_char = mpc52xx_psc_read_char, |
388 | .cw_disable_ints = mpc52xx_psc_cw_disable_ints, |
389 | .cw_restore_ints = mpc52xx_psc_cw_restore_ints, |
390 | .set_baudrate = mpc5200b_psc_set_baudrate, |
391 | .get_irq = mpc52xx_psc_get_irq, |
392 | .handle_irq = mpc52xx_psc_handle_irq, |
393 | .get_status = mpc52xx_psc_get_status, |
394 | .get_ipcr = mpc52xx_psc_get_ipcr, |
395 | .command = mpc52xx_psc_command, |
396 | .set_mode = mpc52xx_psc_set_mode, |
397 | .set_rts = mpc52xx_psc_set_rts, |
398 | .enable_ms = mpc52xx_psc_enable_ms, |
399 | .set_sicr = mpc52xx_psc_set_sicr, |
400 | .set_imr = mpc52xx_psc_set_imr, |
401 | .get_mr1 = mpc52xx_psc_get_mr1, |
402 | }; |
403 | |
404 | #endif /* CONFIG_PPC_MPC52xx */ |
405 | |
406 | #ifdef CONFIG_PPC_MPC512x |
407 | #define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1)) |
408 | |
409 | /* PSC FIFO Controller for mpc512x */ |
410 | struct psc_fifoc { |
411 | u32 fifoc_cmd; |
412 | u32 fifoc_int; |
413 | u32 fifoc_dma; |
414 | u32 fifoc_axe; |
415 | u32 fifoc_debug; |
416 | }; |
417 | |
418 | static struct psc_fifoc __iomem *psc_fifoc; |
419 | static unsigned int psc_fifoc_irq; |
420 | static struct clk *psc_fifoc_clk; |
421 | |
422 | static void mpc512x_psc_fifo_init(struct uart_port *port) |
423 | { |
424 | /* /32 prescaler */ |
425 | out_be16(&PSC(port)->mpc52xx_psc_clock_select, 0xdd00); |
426 | |
427 | out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE); |
428 | out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE); |
429 | out_be32(&FIFO_512x(port)->txalarm, 1); |
430 | out_be32(&FIFO_512x(port)->tximr, 0); |
431 | |
432 | out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE); |
433 | out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE); |
434 | out_be32(&FIFO_512x(port)->rxalarm, 1); |
435 | out_be32(&FIFO_512x(port)->rximr, 0); |
436 | |
437 | out_be32(&FIFO_512x(port)->tximr, MPC512x_PSC_FIFO_ALARM); |
438 | out_be32(&FIFO_512x(port)->rximr, MPC512x_PSC_FIFO_ALARM); |
439 | } |
440 | |
441 | static unsigned int mpc512x_psc_raw_rx_rdy(struct uart_port *port) |
442 | { |
443 | return !(in_be32(&FIFO_512x(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY); |
444 | } |
445 | |
446 | static unsigned int mpc512x_psc_raw_tx_rdy(struct uart_port *port) |
447 | { |
448 | return !(in_be32(&FIFO_512x(port)->txsr) & MPC512x_PSC_FIFO_FULL); |
449 | } |
450 | |
451 | static unsigned int mpc512x_psc_rx_rdy(struct uart_port *port) |
452 | { |
453 | return in_be32(&FIFO_512x(port)->rxsr) |
454 | & in_be32(&FIFO_512x(port)->rximr) |
455 | & MPC512x_PSC_FIFO_ALARM; |
456 | } |
457 | |
458 | static unsigned int mpc512x_psc_tx_rdy(struct uart_port *port) |
459 | { |
460 | return in_be32(&FIFO_512x(port)->txsr) |
461 | & in_be32(&FIFO_512x(port)->tximr) |
462 | & MPC512x_PSC_FIFO_ALARM; |
463 | } |
464 | |
465 | static unsigned int mpc512x_psc_tx_empty(struct uart_port *port) |
466 | { |
467 | return in_be32(&FIFO_512x(port)->txsr) |
468 | & MPC512x_PSC_FIFO_EMPTY; |
469 | } |
470 | |
471 | static void mpc512x_psc_stop_rx(struct uart_port *port) |
472 | { |
473 | unsigned long rx_fifo_imr; |
474 | |
475 | rx_fifo_imr = in_be32(&FIFO_512x(port)->rximr); |
476 | rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM; |
477 | out_be32(&FIFO_512x(port)->rximr, rx_fifo_imr); |
478 | } |
479 | |
480 | static void mpc512x_psc_start_tx(struct uart_port *port) |
481 | { |
482 | unsigned long tx_fifo_imr; |
483 | |
484 | tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr); |
485 | tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM; |
486 | out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr); |
487 | } |
488 | |
489 | static void mpc512x_psc_stop_tx(struct uart_port *port) |
490 | { |
491 | unsigned long tx_fifo_imr; |
492 | |
493 | tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr); |
494 | tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM; |
495 | out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr); |
496 | } |
497 | |
498 | static void mpc512x_psc_rx_clr_irq(struct uart_port *port) |
499 | { |
500 | out_be32(&FIFO_512x(port)->rxisr, in_be32(&FIFO_512x(port)->rxisr)); |
501 | } |
502 | |
503 | static void mpc512x_psc_tx_clr_irq(struct uart_port *port) |
504 | { |
505 | out_be32(&FIFO_512x(port)->txisr, in_be32(&FIFO_512x(port)->txisr)); |
506 | } |
507 | |
508 | static void mpc512x_psc_write_char(struct uart_port *port, unsigned char c) |
509 | { |
510 | out_8(&FIFO_512x(port)->txdata_8, c); |
511 | } |
512 | |
513 | static unsigned char mpc512x_psc_read_char(struct uart_port *port) |
514 | { |
515 | return in_8(&FIFO_512x(port)->rxdata_8); |
516 | } |
517 | |
518 | static void mpc512x_psc_cw_disable_ints(struct uart_port *port) |
519 | { |
520 | port->read_status_mask = |
521 | in_be32(&FIFO_512x(port)->tximr) << 16 | |
522 | in_be32(&FIFO_512x(port)->rximr); |
523 | out_be32(&FIFO_512x(port)->tximr, 0); |
524 | out_be32(&FIFO_512x(port)->rximr, 0); |
525 | } |
526 | |
527 | static void mpc512x_psc_cw_restore_ints(struct uart_port *port) |
528 | { |
529 | out_be32(&FIFO_512x(port)->tximr, |
530 | (port->read_status_mask >> 16) & 0x7f); |
531 | out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f); |
532 | } |
533 | |
534 | static unsigned int mpc512x_psc_set_baudrate(struct uart_port *port, |
535 | struct ktermios *new, |
536 | const struct ktermios *old) |
537 | { |
538 | unsigned int baud; |
539 | unsigned int divisor; |
540 | |
541 | /* |
542 | * The "MPC5121e Microcontroller Reference Manual, Rev. 3" says on |
543 | * pg. 30-10 that the chip supports a /32 and a /10 prescaler. |
544 | * Furthermore, it states that "After reset, the prescaler by 10 |
545 | * for the UART mode is selected", but the reset register value is |
546 | * 0x0000 which means a /32 prescaler. This is wrong. |
547 | * |
548 | * In reality using /32 prescaler doesn't work, as it is not supported! |
549 | * Use /16 or /10 prescaler, see "MPC5121e Hardware Design Guide", |
550 | * Chapter 4.1 PSC in UART Mode. |
551 | * Calculate with a /16 prescaler here. |
552 | */ |
553 | |
554 | /* uartclk contains the ips freq */ |
555 | baud = uart_get_baud_rate(port, new, old, |
556 | port->uartclk / (16 * 0xffff) + 1, |
557 | port->uartclk / 16); |
558 | divisor = (port->uartclk + 8 * baud) / (16 * baud); |
559 | |
560 | /* enable the /16 prescaler and set the divisor */ |
561 | mpc52xx_set_divisor(PSC(port), 0xdd00, divisor); |
562 | return baud; |
563 | } |
564 | |
565 | /* Init PSC FIFO Controller */ |
566 | static int __init mpc512x_psc_fifoc_init(void) |
567 | { |
568 | int err; |
569 | struct device_node *np; |
570 | struct clk *clk; |
571 | |
572 | /* default error code, potentially overwritten by clock calls */ |
573 | err = -ENODEV; |
574 | |
575 | np = of_find_compatible_node(NULL, NULL, |
576 | "fsl,mpc5121-psc-fifo" ); |
577 | if (!np) { |
578 | pr_err("%s: Can't find FIFOC node\n" , __func__); |
579 | goto out_err; |
580 | } |
581 | |
582 | clk = of_clk_get(np, 0); |
583 | if (IS_ERR(clk)) { |
584 | /* backwards compat with device trees that lack clock specs */ |
585 | clk = clk_get_sys(np->name, "ipg" ); |
586 | } |
587 | if (IS_ERR(clk)) { |
588 | pr_err("%s: Can't lookup FIFO clock\n" , __func__); |
589 | err = PTR_ERR(clk); |
590 | goto out_ofnode_put; |
591 | } |
592 | if (clk_prepare_enable(clk)) { |
593 | pr_err("%s: Can't enable FIFO clock\n" , __func__); |
594 | clk_put(clk); |
595 | goto out_ofnode_put; |
596 | } |
597 | psc_fifoc_clk = clk; |
598 | |
599 | psc_fifoc = of_iomap(np, 0); |
600 | if (!psc_fifoc) { |
601 | pr_err("%s: Can't map FIFOC\n" , __func__); |
602 | goto out_clk_disable; |
603 | } |
604 | |
605 | psc_fifoc_irq = irq_of_parse_and_map(np, 0); |
606 | if (psc_fifoc_irq == 0) { |
607 | pr_err("%s: Can't get FIFOC irq\n" , __func__); |
608 | goto out_unmap; |
609 | } |
610 | |
611 | of_node_put(np); |
612 | return 0; |
613 | |
614 | out_unmap: |
615 | iounmap(psc_fifoc); |
616 | out_clk_disable: |
617 | clk_disable_unprepare(psc_fifoc_clk); |
618 | clk_put(psc_fifoc_clk); |
619 | out_ofnode_put: |
620 | of_node_put(np); |
621 | out_err: |
622 | return err; |
623 | } |
624 | |
625 | static void __exit mpc512x_psc_fifoc_uninit(void) |
626 | { |
627 | iounmap(psc_fifoc); |
628 | |
629 | /* disable the clock, errors are not fatal */ |
630 | if (psc_fifoc_clk) { |
631 | clk_disable_unprepare(psc_fifoc_clk); |
632 | clk_put(psc_fifoc_clk); |
633 | psc_fifoc_clk = NULL; |
634 | } |
635 | } |
636 | |
637 | /* 512x specific interrupt handler. The caller holds the port lock */ |
638 | static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port) |
639 | { |
640 | unsigned long fifoc_int; |
641 | int psc_num; |
642 | |
643 | /* Read pending PSC FIFOC interrupts */ |
644 | fifoc_int = in_be32(&psc_fifoc->fifoc_int); |
645 | |
646 | /* Check if it is an interrupt for this port */ |
647 | psc_num = (port->mapbase & 0xf00) >> 8; |
648 | if (test_bit(psc_num, &fifoc_int) || |
649 | test_bit(psc_num + 16, &fifoc_int)) |
650 | return mpc5xxx_uart_process_int(port); |
651 | |
652 | return IRQ_NONE; |
653 | } |
654 | |
655 | static struct clk *psc_mclk_clk[MPC52xx_PSC_MAXNUM]; |
656 | static struct clk *psc_ipg_clk[MPC52xx_PSC_MAXNUM]; |
657 | |
658 | /* called from within the .request_port() callback (allocation) */ |
659 | static int mpc512x_psc_alloc_clock(struct uart_port *port) |
660 | { |
661 | int psc_num; |
662 | struct clk *clk; |
663 | int err; |
664 | |
665 | psc_num = (port->mapbase & 0xf00) >> 8; |
666 | |
667 | clk = devm_clk_get(port->dev, "mclk" ); |
668 | if (IS_ERR(clk)) { |
669 | dev_err(port->dev, "Failed to get MCLK!\n" ); |
670 | err = PTR_ERR(clk); |
671 | goto out_err; |
672 | } |
673 | err = clk_prepare_enable(clk); |
674 | if (err) { |
675 | dev_err(port->dev, "Failed to enable MCLK!\n" ); |
676 | goto out_err; |
677 | } |
678 | psc_mclk_clk[psc_num] = clk; |
679 | |
680 | clk = devm_clk_get(port->dev, "ipg" ); |
681 | if (IS_ERR(clk)) { |
682 | dev_err(port->dev, "Failed to get IPG clock!\n" ); |
683 | err = PTR_ERR(clk); |
684 | goto out_err; |
685 | } |
686 | err = clk_prepare_enable(clk); |
687 | if (err) { |
688 | dev_err(port->dev, "Failed to enable IPG clock!\n" ); |
689 | goto out_err; |
690 | } |
691 | psc_ipg_clk[psc_num] = clk; |
692 | |
693 | return 0; |
694 | |
695 | out_err: |
696 | if (psc_mclk_clk[psc_num]) { |
697 | clk_disable_unprepare(psc_mclk_clk[psc_num]); |
698 | psc_mclk_clk[psc_num] = NULL; |
699 | } |
700 | if (psc_ipg_clk[psc_num]) { |
701 | clk_disable_unprepare(psc_ipg_clk[psc_num]); |
702 | psc_ipg_clk[psc_num] = NULL; |
703 | } |
704 | return err; |
705 | } |
706 | |
707 | /* called from within the .release_port() callback (release) */ |
708 | static void mpc512x_psc_relse_clock(struct uart_port *port) |
709 | { |
710 | int psc_num; |
711 | struct clk *clk; |
712 | |
713 | psc_num = (port->mapbase & 0xf00) >> 8; |
714 | clk = psc_mclk_clk[psc_num]; |
715 | if (clk) { |
716 | clk_disable_unprepare(clk); |
717 | psc_mclk_clk[psc_num] = NULL; |
718 | } |
719 | if (psc_ipg_clk[psc_num]) { |
720 | clk_disable_unprepare(psc_ipg_clk[psc_num]); |
721 | psc_ipg_clk[psc_num] = NULL; |
722 | } |
723 | } |
724 | |
725 | /* implementation of the .clock() callback (enable/disable) */ |
726 | static int mpc512x_psc_endis_clock(struct uart_port *port, int enable) |
727 | { |
728 | int psc_num; |
729 | struct clk *psc_clk; |
730 | int ret; |
731 | |
732 | if (uart_console(port)) |
733 | return 0; |
734 | |
735 | psc_num = (port->mapbase & 0xf00) >> 8; |
736 | psc_clk = psc_mclk_clk[psc_num]; |
737 | if (!psc_clk) { |
738 | dev_err(port->dev, "Failed to get PSC clock entry!\n" ); |
739 | return -ENODEV; |
740 | } |
741 | |
742 | dev_dbg(port->dev, "mclk %sable\n" , enable ? "en" : "dis" ); |
743 | if (enable) { |
744 | ret = clk_enable(psc_clk); |
745 | if (ret) |
746 | dev_err(port->dev, "Failed to enable MCLK!\n" ); |
747 | return ret; |
748 | } else { |
749 | clk_disable(psc_clk); |
750 | return 0; |
751 | } |
752 | } |
753 | |
754 | static void mpc512x_psc_get_irq(struct uart_port *port, struct device_node *np) |
755 | { |
756 | port->irqflags = IRQF_SHARED; |
757 | port->irq = psc_fifoc_irq; |
758 | } |
759 | |
760 | #define PSC_5125(port) ((struct mpc5125_psc __iomem *)((port)->membase)) |
761 | #define FIFO_5125(port) ((struct mpc512x_psc_fifo __iomem *)(PSC_5125(port)+1)) |
762 | |
763 | static void mpc5125_psc_fifo_init(struct uart_port *port) |
764 | { |
765 | /* /32 prescaler */ |
766 | out_8(&PSC_5125(port)->mpc52xx_psc_clock_select, 0xdd); |
767 | |
768 | out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE); |
769 | out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE); |
770 | out_be32(&FIFO_5125(port)->txalarm, 1); |
771 | out_be32(&FIFO_5125(port)->tximr, 0); |
772 | |
773 | out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE); |
774 | out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE); |
775 | out_be32(&FIFO_5125(port)->rxalarm, 1); |
776 | out_be32(&FIFO_5125(port)->rximr, 0); |
777 | |
778 | out_be32(&FIFO_5125(port)->tximr, MPC512x_PSC_FIFO_ALARM); |
779 | out_be32(&FIFO_5125(port)->rximr, MPC512x_PSC_FIFO_ALARM); |
780 | } |
781 | |
782 | static unsigned int mpc5125_psc_raw_rx_rdy(struct uart_port *port) |
783 | { |
784 | return !(in_be32(&FIFO_5125(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY); |
785 | } |
786 | |
787 | static unsigned int mpc5125_psc_raw_tx_rdy(struct uart_port *port) |
788 | { |
789 | return !(in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_FULL); |
790 | } |
791 | |
792 | static unsigned int mpc5125_psc_rx_rdy(struct uart_port *port) |
793 | { |
794 | return in_be32(&FIFO_5125(port)->rxsr) & |
795 | in_be32(&FIFO_5125(port)->rximr) & MPC512x_PSC_FIFO_ALARM; |
796 | } |
797 | |
798 | static unsigned int mpc5125_psc_tx_rdy(struct uart_port *port) |
799 | { |
800 | return in_be32(&FIFO_5125(port)->txsr) & |
801 | in_be32(&FIFO_5125(port)->tximr) & MPC512x_PSC_FIFO_ALARM; |
802 | } |
803 | |
804 | static unsigned int mpc5125_psc_tx_empty(struct uart_port *port) |
805 | { |
806 | return in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_EMPTY; |
807 | } |
808 | |
809 | static void mpc5125_psc_stop_rx(struct uart_port *port) |
810 | { |
811 | unsigned long rx_fifo_imr; |
812 | |
813 | rx_fifo_imr = in_be32(&FIFO_5125(port)->rximr); |
814 | rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM; |
815 | out_be32(&FIFO_5125(port)->rximr, rx_fifo_imr); |
816 | } |
817 | |
818 | static void mpc5125_psc_start_tx(struct uart_port *port) |
819 | { |
820 | unsigned long tx_fifo_imr; |
821 | |
822 | tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr); |
823 | tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM; |
824 | out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr); |
825 | } |
826 | |
827 | static void mpc5125_psc_stop_tx(struct uart_port *port) |
828 | { |
829 | unsigned long tx_fifo_imr; |
830 | |
831 | tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr); |
832 | tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM; |
833 | out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr); |
834 | } |
835 | |
836 | static void mpc5125_psc_rx_clr_irq(struct uart_port *port) |
837 | { |
838 | out_be32(&FIFO_5125(port)->rxisr, in_be32(&FIFO_5125(port)->rxisr)); |
839 | } |
840 | |
841 | static void mpc5125_psc_tx_clr_irq(struct uart_port *port) |
842 | { |
843 | out_be32(&FIFO_5125(port)->txisr, in_be32(&FIFO_5125(port)->txisr)); |
844 | } |
845 | |
846 | static void mpc5125_psc_write_char(struct uart_port *port, unsigned char c) |
847 | { |
848 | out_8(&FIFO_5125(port)->txdata_8, c); |
849 | } |
850 | |
851 | static unsigned char mpc5125_psc_read_char(struct uart_port *port) |
852 | { |
853 | return in_8(&FIFO_5125(port)->rxdata_8); |
854 | } |
855 | |
856 | static void mpc5125_psc_cw_disable_ints(struct uart_port *port) |
857 | { |
858 | port->read_status_mask = |
859 | in_be32(&FIFO_5125(port)->tximr) << 16 | |
860 | in_be32(&FIFO_5125(port)->rximr); |
861 | out_be32(&FIFO_5125(port)->tximr, 0); |
862 | out_be32(&FIFO_5125(port)->rximr, 0); |
863 | } |
864 | |
865 | static void mpc5125_psc_cw_restore_ints(struct uart_port *port) |
866 | { |
867 | out_be32(&FIFO_5125(port)->tximr, |
868 | (port->read_status_mask >> 16) & 0x7f); |
869 | out_be32(&FIFO_5125(port)->rximr, port->read_status_mask & 0x7f); |
870 | } |
871 | |
872 | static inline void mpc5125_set_divisor(struct mpc5125_psc __iomem *psc, |
873 | u8 prescaler, unsigned int divisor) |
874 | { |
875 | /* select prescaler */ |
876 | out_8(&psc->mpc52xx_psc_clock_select, prescaler); |
877 | out_8(&psc->ctur, divisor >> 8); |
878 | out_8(&psc->ctlr, divisor & 0xff); |
879 | } |
880 | |
881 | static unsigned int mpc5125_psc_set_baudrate(struct uart_port *port, |
882 | struct ktermios *new, |
883 | const struct ktermios *old) |
884 | { |
885 | unsigned int baud; |
886 | unsigned int divisor; |
887 | |
888 | /* |
889 | * Calculate with a /16 prescaler here. |
890 | */ |
891 | |
892 | /* uartclk contains the ips freq */ |
893 | baud = uart_get_baud_rate(port, new, old, |
894 | port->uartclk / (16 * 0xffff) + 1, |
895 | port->uartclk / 16); |
896 | divisor = (port->uartclk + 8 * baud) / (16 * baud); |
897 | |
898 | /* enable the /16 prescaler and set the divisor */ |
899 | mpc5125_set_divisor(PSC_5125(port), 0xdd, divisor); |
900 | return baud; |
901 | } |
902 | |
903 | /* |
904 | * MPC5125 have compatible PSC FIFO Controller. |
905 | * Special init not needed. |
906 | */ |
907 | static u16 mpc5125_psc_get_status(struct uart_port *port) |
908 | { |
909 | return in_be16(&PSC_5125(port)->mpc52xx_psc_status); |
910 | } |
911 | |
912 | static u8 mpc5125_psc_get_ipcr(struct uart_port *port) |
913 | { |
914 | return in_8(&PSC_5125(port)->mpc52xx_psc_ipcr); |
915 | } |
916 | |
917 | static void mpc5125_psc_command(struct uart_port *port, u8 cmd) |
918 | { |
919 | out_8(&PSC_5125(port)->command, cmd); |
920 | } |
921 | |
922 | static void mpc5125_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2) |
923 | { |
924 | out_8(&PSC_5125(port)->mr1, mr1); |
925 | out_8(&PSC_5125(port)->mr2, mr2); |
926 | } |
927 | |
928 | static void mpc5125_psc_set_rts(struct uart_port *port, int state) |
929 | { |
930 | if (state & TIOCM_RTS) |
931 | out_8(&PSC_5125(port)->op1, MPC52xx_PSC_OP_RTS); |
932 | else |
933 | out_8(&PSC_5125(port)->op0, MPC52xx_PSC_OP_RTS); |
934 | } |
935 | |
936 | static void mpc5125_psc_enable_ms(struct uart_port *port) |
937 | { |
938 | struct mpc5125_psc __iomem *psc = PSC_5125(port); |
939 | |
940 | /* clear D_*-bits by reading them */ |
941 | in_8(&psc->mpc52xx_psc_ipcr); |
942 | /* enable CTS and DCD as IPC interrupts */ |
943 | out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD); |
944 | |
945 | port->read_status_mask |= MPC52xx_PSC_IMR_IPC; |
946 | out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); |
947 | } |
948 | |
949 | static void mpc5125_psc_set_sicr(struct uart_port *port, u32 val) |
950 | { |
951 | out_be32(&PSC_5125(port)->sicr, val); |
952 | } |
953 | |
954 | static void mpc5125_psc_set_imr(struct uart_port *port, u16 val) |
955 | { |
956 | out_be16(&PSC_5125(port)->mpc52xx_psc_imr, val); |
957 | } |
958 | |
959 | static u8 mpc5125_psc_get_mr1(struct uart_port *port) |
960 | { |
961 | return in_8(&PSC_5125(port)->mr1); |
962 | } |
963 | |
964 | static const struct psc_ops mpc5125_psc_ops = { |
965 | .fifo_init = mpc5125_psc_fifo_init, |
966 | .raw_rx_rdy = mpc5125_psc_raw_rx_rdy, |
967 | .raw_tx_rdy = mpc5125_psc_raw_tx_rdy, |
968 | .rx_rdy = mpc5125_psc_rx_rdy, |
969 | .tx_rdy = mpc5125_psc_tx_rdy, |
970 | .tx_empty = mpc5125_psc_tx_empty, |
971 | .stop_rx = mpc5125_psc_stop_rx, |
972 | .start_tx = mpc5125_psc_start_tx, |
973 | .stop_tx = mpc5125_psc_stop_tx, |
974 | .rx_clr_irq = mpc5125_psc_rx_clr_irq, |
975 | .tx_clr_irq = mpc5125_psc_tx_clr_irq, |
976 | .write_char = mpc5125_psc_write_char, |
977 | .read_char = mpc5125_psc_read_char, |
978 | .cw_disable_ints = mpc5125_psc_cw_disable_ints, |
979 | .cw_restore_ints = mpc5125_psc_cw_restore_ints, |
980 | .set_baudrate = mpc5125_psc_set_baudrate, |
981 | .clock_alloc = mpc512x_psc_alloc_clock, |
982 | .clock_relse = mpc512x_psc_relse_clock, |
983 | .clock = mpc512x_psc_endis_clock, |
984 | .fifoc_init = mpc512x_psc_fifoc_init, |
985 | .fifoc_uninit = mpc512x_psc_fifoc_uninit, |
986 | .get_irq = mpc512x_psc_get_irq, |
987 | .handle_irq = mpc512x_psc_handle_irq, |
988 | .get_status = mpc5125_psc_get_status, |
989 | .get_ipcr = mpc5125_psc_get_ipcr, |
990 | .command = mpc5125_psc_command, |
991 | .set_mode = mpc5125_psc_set_mode, |
992 | .set_rts = mpc5125_psc_set_rts, |
993 | .enable_ms = mpc5125_psc_enable_ms, |
994 | .set_sicr = mpc5125_psc_set_sicr, |
995 | .set_imr = mpc5125_psc_set_imr, |
996 | .get_mr1 = mpc5125_psc_get_mr1, |
997 | }; |
998 | |
999 | static const struct psc_ops mpc512x_psc_ops = { |
1000 | .fifo_init = mpc512x_psc_fifo_init, |
1001 | .raw_rx_rdy = mpc512x_psc_raw_rx_rdy, |
1002 | .raw_tx_rdy = mpc512x_psc_raw_tx_rdy, |
1003 | .rx_rdy = mpc512x_psc_rx_rdy, |
1004 | .tx_rdy = mpc512x_psc_tx_rdy, |
1005 | .tx_empty = mpc512x_psc_tx_empty, |
1006 | .stop_rx = mpc512x_psc_stop_rx, |
1007 | .start_tx = mpc512x_psc_start_tx, |
1008 | .stop_tx = mpc512x_psc_stop_tx, |
1009 | .rx_clr_irq = mpc512x_psc_rx_clr_irq, |
1010 | .tx_clr_irq = mpc512x_psc_tx_clr_irq, |
1011 | .write_char = mpc512x_psc_write_char, |
1012 | .read_char = mpc512x_psc_read_char, |
1013 | .cw_disable_ints = mpc512x_psc_cw_disable_ints, |
1014 | .cw_restore_ints = mpc512x_psc_cw_restore_ints, |
1015 | .set_baudrate = mpc512x_psc_set_baudrate, |
1016 | .clock_alloc = mpc512x_psc_alloc_clock, |
1017 | .clock_relse = mpc512x_psc_relse_clock, |
1018 | .clock = mpc512x_psc_endis_clock, |
1019 | .fifoc_init = mpc512x_psc_fifoc_init, |
1020 | .fifoc_uninit = mpc512x_psc_fifoc_uninit, |
1021 | .get_irq = mpc512x_psc_get_irq, |
1022 | .handle_irq = mpc512x_psc_handle_irq, |
1023 | .get_status = mpc52xx_psc_get_status, |
1024 | .get_ipcr = mpc52xx_psc_get_ipcr, |
1025 | .command = mpc52xx_psc_command, |
1026 | .set_mode = mpc52xx_psc_set_mode, |
1027 | .set_rts = mpc52xx_psc_set_rts, |
1028 | .enable_ms = mpc52xx_psc_enable_ms, |
1029 | .set_sicr = mpc52xx_psc_set_sicr, |
1030 | .set_imr = mpc52xx_psc_set_imr, |
1031 | .get_mr1 = mpc52xx_psc_get_mr1, |
1032 | }; |
1033 | #endif /* CONFIG_PPC_MPC512x */ |
1034 | |
1035 | |
1036 | static const struct psc_ops *psc_ops; |
1037 | |
1038 | /* ======================================================================== */ |
1039 | /* UART operations */ |
1040 | /* ======================================================================== */ |
1041 | |
1042 | static unsigned int |
1043 | mpc52xx_uart_tx_empty(struct uart_port *port) |
1044 | { |
1045 | return psc_ops->tx_empty(port) ? TIOCSER_TEMT : 0; |
1046 | } |
1047 | |
1048 | static void |
1049 | mpc52xx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) |
1050 | { |
1051 | psc_ops->set_rts(port, mctrl & TIOCM_RTS); |
1052 | } |
1053 | |
1054 | static unsigned int |
1055 | mpc52xx_uart_get_mctrl(struct uart_port *port) |
1056 | { |
1057 | unsigned int ret = TIOCM_DSR; |
1058 | u8 status = psc_ops->get_ipcr(port); |
1059 | |
1060 | if (!(status & MPC52xx_PSC_CTS)) |
1061 | ret |= TIOCM_CTS; |
1062 | if (!(status & MPC52xx_PSC_DCD)) |
1063 | ret |= TIOCM_CAR; |
1064 | |
1065 | return ret; |
1066 | } |
1067 | |
1068 | static void |
1069 | mpc52xx_uart_stop_tx(struct uart_port *port) |
1070 | { |
1071 | /* port->lock taken by caller */ |
1072 | psc_ops->stop_tx(port); |
1073 | } |
1074 | |
1075 | static void |
1076 | mpc52xx_uart_start_tx(struct uart_port *port) |
1077 | { |
1078 | /* port->lock taken by caller */ |
1079 | psc_ops->start_tx(port); |
1080 | } |
1081 | |
1082 | static void |
1083 | mpc52xx_uart_stop_rx(struct uart_port *port) |
1084 | { |
1085 | /* port->lock taken by caller */ |
1086 | psc_ops->stop_rx(port); |
1087 | } |
1088 | |
1089 | static void |
1090 | mpc52xx_uart_enable_ms(struct uart_port *port) |
1091 | { |
1092 | psc_ops->enable_ms(port); |
1093 | } |
1094 | |
1095 | static void |
1096 | mpc52xx_uart_break_ctl(struct uart_port *port, int ctl) |
1097 | { |
1098 | unsigned long flags; |
1099 | uart_port_lock_irqsave(up: port, flags: &flags); |
1100 | |
1101 | if (ctl == -1) |
1102 | psc_ops->command(port, MPC52xx_PSC_START_BRK); |
1103 | else |
1104 | psc_ops->command(port, MPC52xx_PSC_STOP_BRK); |
1105 | |
1106 | uart_port_unlock_irqrestore(up: port, flags); |
1107 | } |
1108 | |
1109 | static int |
1110 | mpc52xx_uart_startup(struct uart_port *port) |
1111 | { |
1112 | int ret; |
1113 | |
1114 | if (psc_ops->clock) { |
1115 | ret = psc_ops->clock(port, 1); |
1116 | if (ret) |
1117 | return ret; |
1118 | } |
1119 | |
1120 | /* Request IRQ */ |
1121 | ret = request_irq(irq: port->irq, handler: mpc52xx_uart_int, |
1122 | flags: port->irqflags, name: "mpc52xx_psc_uart" , dev: port); |
1123 | if (ret) |
1124 | return ret; |
1125 | |
1126 | /* Reset/activate the port, clear and enable interrupts */ |
1127 | psc_ops->command(port, MPC52xx_PSC_RST_RX); |
1128 | psc_ops->command(port, MPC52xx_PSC_RST_TX); |
1129 | |
1130 | /* |
1131 | * According to Freescale's support the RST_TX command can produce a |
1132 | * spike on the TX pin. So they recommend to delay "for one character". |
1133 | * One millisecond should be enough for everyone. |
1134 | */ |
1135 | msleep(msecs: 1); |
1136 | |
1137 | psc_ops->set_sicr(port, 0); /* UART mode DCD ignored */ |
1138 | |
1139 | psc_ops->fifo_init(port); |
1140 | |
1141 | psc_ops->command(port, MPC52xx_PSC_TX_ENABLE); |
1142 | psc_ops->command(port, MPC52xx_PSC_RX_ENABLE); |
1143 | |
1144 | return 0; |
1145 | } |
1146 | |
1147 | static void |
1148 | mpc52xx_uart_shutdown(struct uart_port *port) |
1149 | { |
1150 | /* Shut down the port. Leave TX active if on a console port */ |
1151 | psc_ops->command(port, MPC52xx_PSC_RST_RX); |
1152 | if (!uart_console(port)) |
1153 | psc_ops->command(port, MPC52xx_PSC_RST_TX); |
1154 | |
1155 | port->read_status_mask = 0; |
1156 | psc_ops->set_imr(port, port->read_status_mask); |
1157 | |
1158 | if (psc_ops->clock) |
1159 | psc_ops->clock(port, 0); |
1160 | |
1161 | /* Disable interrupt */ |
1162 | psc_ops->cw_disable_ints(port); |
1163 | |
1164 | /* Release interrupt */ |
1165 | free_irq(port->irq, port); |
1166 | } |
1167 | |
1168 | static void |
1169 | mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new, |
1170 | const struct ktermios *old) |
1171 | { |
1172 | unsigned long flags; |
1173 | unsigned char mr1, mr2; |
1174 | unsigned int j; |
1175 | unsigned int baud; |
1176 | |
1177 | /* Prepare what we're gonna write */ |
1178 | mr1 = 0; |
1179 | |
1180 | switch (new->c_cflag & CSIZE) { |
1181 | case CS5: mr1 |= MPC52xx_PSC_MODE_5_BITS; |
1182 | break; |
1183 | case CS6: mr1 |= MPC52xx_PSC_MODE_6_BITS; |
1184 | break; |
1185 | case CS7: mr1 |= MPC52xx_PSC_MODE_7_BITS; |
1186 | break; |
1187 | case CS8: |
1188 | default: mr1 |= MPC52xx_PSC_MODE_8_BITS; |
1189 | } |
1190 | |
1191 | if (new->c_cflag & PARENB) { |
1192 | if (new->c_cflag & CMSPAR) |
1193 | mr1 |= MPC52xx_PSC_MODE_PARFORCE; |
1194 | |
1195 | /* With CMSPAR, PARODD also means high parity (same as termios) */ |
1196 | mr1 |= (new->c_cflag & PARODD) ? |
1197 | MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN; |
1198 | } else { |
1199 | mr1 |= MPC52xx_PSC_MODE_PARNONE; |
1200 | } |
1201 | |
1202 | mr2 = 0; |
1203 | |
1204 | if (new->c_cflag & CSTOPB) |
1205 | mr2 |= MPC52xx_PSC_MODE_TWO_STOP; |
1206 | else |
1207 | mr2 |= ((new->c_cflag & CSIZE) == CS5) ? |
1208 | MPC52xx_PSC_MODE_ONE_STOP_5_BITS : |
1209 | MPC52xx_PSC_MODE_ONE_STOP; |
1210 | |
1211 | if (new->c_cflag & CRTSCTS) { |
1212 | mr1 |= MPC52xx_PSC_MODE_RXRTS; |
1213 | mr2 |= MPC52xx_PSC_MODE_TXCTS; |
1214 | } |
1215 | |
1216 | /* Get the lock */ |
1217 | uart_port_lock_irqsave(up: port, flags: &flags); |
1218 | |
1219 | /* Do our best to flush TX & RX, so we don't lose anything */ |
1220 | /* But we don't wait indefinitely ! */ |
1221 | j = 5000000; /* Maximum wait */ |
1222 | /* FIXME Can't receive chars since set_termios might be called at early |
1223 | * boot for the console, all stuff is not yet ready to receive at that |
1224 | * time and that just makes the kernel oops */ |
1225 | /* while (j-- && mpc52xx_uart_int_rx_chars(port)); */ |
1226 | while (!mpc52xx_uart_tx_empty(port) && --j) |
1227 | udelay(1); |
1228 | |
1229 | if (!j) |
1230 | printk(KERN_ERR "mpc52xx_uart.c: " |
1231 | "Unable to flush RX & TX fifos in-time in set_termios." |
1232 | "Some chars may have been lost.\n" ); |
1233 | |
1234 | /* Reset the TX & RX */ |
1235 | psc_ops->command(port, MPC52xx_PSC_RST_RX); |
1236 | psc_ops->command(port, MPC52xx_PSC_RST_TX); |
1237 | |
1238 | /* Send new mode settings */ |
1239 | psc_ops->set_mode(port, mr1, mr2); |
1240 | baud = psc_ops->set_baudrate(port, new, old); |
1241 | |
1242 | /* Update the per-port timeout */ |
1243 | uart_update_timeout(port, cflag: new->c_cflag, baud); |
1244 | |
1245 | if (UART_ENABLE_MS(port, new->c_cflag)) |
1246 | mpc52xx_uart_enable_ms(port); |
1247 | |
1248 | /* Reenable TX & RX */ |
1249 | psc_ops->command(port, MPC52xx_PSC_TX_ENABLE); |
1250 | psc_ops->command(port, MPC52xx_PSC_RX_ENABLE); |
1251 | |
1252 | /* We're all set, release the lock */ |
1253 | uart_port_unlock_irqrestore(up: port, flags); |
1254 | } |
1255 | |
1256 | static const char * |
1257 | mpc52xx_uart_type(struct uart_port *port) |
1258 | { |
1259 | /* |
1260 | * We keep using PORT_MPC52xx for historic reasons although it applies |
1261 | * for MPC512x, too, but print "MPC5xxx" to not irritate users |
1262 | */ |
1263 | return port->type == PORT_MPC52xx ? "MPC5xxx PSC" : NULL; |
1264 | } |
1265 | |
1266 | static void |
1267 | mpc52xx_uart_release_port(struct uart_port *port) |
1268 | { |
1269 | if (psc_ops->clock_relse) |
1270 | psc_ops->clock_relse(port); |
1271 | |
1272 | /* remapped by us ? */ |
1273 | if (port->flags & UPF_IOREMAP) { |
1274 | iounmap(addr: port->membase); |
1275 | port->membase = NULL; |
1276 | } |
1277 | |
1278 | release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc)); |
1279 | } |
1280 | |
1281 | static int |
1282 | mpc52xx_uart_request_port(struct uart_port *port) |
1283 | { |
1284 | int err; |
1285 | |
1286 | if (port->flags & UPF_IOREMAP) /* Need to remap ? */ |
1287 | port->membase = ioremap(port->mapbase, |
1288 | sizeof(struct mpc52xx_psc)); |
1289 | |
1290 | if (!port->membase) |
1291 | return -EINVAL; |
1292 | |
1293 | err = request_mem_region(port->mapbase, sizeof(struct mpc52xx_psc), |
1294 | "mpc52xx_psc_uart" ) != NULL ? 0 : -EBUSY; |
1295 | |
1296 | if (err) |
1297 | goto out_membase; |
1298 | |
1299 | if (psc_ops->clock_alloc) { |
1300 | err = psc_ops->clock_alloc(port); |
1301 | if (err) |
1302 | goto out_mapregion; |
1303 | } |
1304 | |
1305 | return 0; |
1306 | |
1307 | out_mapregion: |
1308 | release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc)); |
1309 | out_membase: |
1310 | if (port->flags & UPF_IOREMAP) { |
1311 | iounmap(addr: port->membase); |
1312 | port->membase = NULL; |
1313 | } |
1314 | return err; |
1315 | } |
1316 | |
1317 | static void |
1318 | mpc52xx_uart_config_port(struct uart_port *port, int flags) |
1319 | { |
1320 | if ((flags & UART_CONFIG_TYPE) |
1321 | && (mpc52xx_uart_request_port(port) == 0)) |
1322 | port->type = PORT_MPC52xx; |
1323 | } |
1324 | |
1325 | static int |
1326 | mpc52xx_uart_verify_port(struct uart_port *port, struct serial_struct *ser) |
1327 | { |
1328 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPC52xx) |
1329 | return -EINVAL; |
1330 | |
1331 | if ((ser->irq != port->irq) || |
1332 | (ser->io_type != UPIO_MEM) || |
1333 | (ser->baud_base != port->uartclk) || |
1334 | (ser->iomem_base != (void *)port->mapbase) || |
1335 | (ser->hub6 != 0)) |
1336 | return -EINVAL; |
1337 | |
1338 | return 0; |
1339 | } |
1340 | |
1341 | |
1342 | static const struct uart_ops mpc52xx_uart_ops = { |
1343 | .tx_empty = mpc52xx_uart_tx_empty, |
1344 | .set_mctrl = mpc52xx_uart_set_mctrl, |
1345 | .get_mctrl = mpc52xx_uart_get_mctrl, |
1346 | .stop_tx = mpc52xx_uart_stop_tx, |
1347 | .start_tx = mpc52xx_uart_start_tx, |
1348 | .stop_rx = mpc52xx_uart_stop_rx, |
1349 | .enable_ms = mpc52xx_uart_enable_ms, |
1350 | .break_ctl = mpc52xx_uart_break_ctl, |
1351 | .startup = mpc52xx_uart_startup, |
1352 | .shutdown = mpc52xx_uart_shutdown, |
1353 | .set_termios = mpc52xx_uart_set_termios, |
1354 | /* .pm = mpc52xx_uart_pm, Not supported yet */ |
1355 | .type = mpc52xx_uart_type, |
1356 | .release_port = mpc52xx_uart_release_port, |
1357 | .request_port = mpc52xx_uart_request_port, |
1358 | .config_port = mpc52xx_uart_config_port, |
1359 | .verify_port = mpc52xx_uart_verify_port |
1360 | }; |
1361 | |
1362 | |
1363 | /* ======================================================================== */ |
1364 | /* Interrupt handling */ |
1365 | /* ======================================================================== */ |
1366 | |
1367 | static inline bool |
1368 | mpc52xx_uart_int_rx_chars(struct uart_port *port) |
1369 | { |
1370 | struct tty_port *tport = &port->state->port; |
1371 | unsigned char ch, flag; |
1372 | unsigned short status; |
1373 | |
1374 | /* While we can read, do so ! */ |
1375 | while (psc_ops->raw_rx_rdy(port)) { |
1376 | /* Get the char */ |
1377 | ch = psc_ops->read_char(port); |
1378 | |
1379 | /* Handle sysreq char */ |
1380 | if (uart_handle_sysrq_char(port, ch)) |
1381 | continue; |
1382 | |
1383 | /* Store it */ |
1384 | |
1385 | flag = TTY_NORMAL; |
1386 | port->icount.rx++; |
1387 | |
1388 | status = psc_ops->get_status(port); |
1389 | |
1390 | if (status & (MPC52xx_PSC_SR_PE | |
1391 | MPC52xx_PSC_SR_FE | |
1392 | MPC52xx_PSC_SR_RB)) { |
1393 | |
1394 | if (status & MPC52xx_PSC_SR_RB) { |
1395 | flag = TTY_BREAK; |
1396 | uart_handle_break(port); |
1397 | port->icount.brk++; |
1398 | } else if (status & MPC52xx_PSC_SR_PE) { |
1399 | flag = TTY_PARITY; |
1400 | port->icount.parity++; |
1401 | } |
1402 | else if (status & MPC52xx_PSC_SR_FE) { |
1403 | flag = TTY_FRAME; |
1404 | port->icount.frame++; |
1405 | } |
1406 | |
1407 | /* Clear error condition */ |
1408 | psc_ops->command(port, MPC52xx_PSC_RST_ERR_STAT); |
1409 | |
1410 | } |
1411 | tty_insert_flip_char(port: tport, ch, flag); |
1412 | if (status & MPC52xx_PSC_SR_OE) { |
1413 | /* |
1414 | * Overrun is special, since it's |
1415 | * reported immediately, and doesn't |
1416 | * affect the current character |
1417 | */ |
1418 | tty_insert_flip_char(port: tport, ch: 0, TTY_OVERRUN); |
1419 | port->icount.overrun++; |
1420 | } |
1421 | } |
1422 | |
1423 | tty_flip_buffer_push(port: tport); |
1424 | |
1425 | return psc_ops->raw_rx_rdy(port); |
1426 | } |
1427 | |
1428 | static inline bool |
1429 | mpc52xx_uart_int_tx_chars(struct uart_port *port) |
1430 | { |
1431 | u8 ch; |
1432 | |
1433 | return uart_port_tx(port, ch, |
1434 | psc_ops->raw_tx_rdy(port), |
1435 | psc_ops->write_char(port, ch)); |
1436 | } |
1437 | |
1438 | static irqreturn_t |
1439 | mpc5xxx_uart_process_int(struct uart_port *port) |
1440 | { |
1441 | unsigned long pass = ISR_PASS_LIMIT; |
1442 | bool keepgoing; |
1443 | u8 status; |
1444 | |
1445 | /* While we have stuff to do, we continue */ |
1446 | do { |
1447 | /* If we don't find anything to do, we stop */ |
1448 | keepgoing = false; |
1449 | |
1450 | psc_ops->rx_clr_irq(port); |
1451 | if (psc_ops->rx_rdy(port)) |
1452 | keepgoing |= mpc52xx_uart_int_rx_chars(port); |
1453 | |
1454 | psc_ops->tx_clr_irq(port); |
1455 | if (psc_ops->tx_rdy(port)) |
1456 | keepgoing |= mpc52xx_uart_int_tx_chars(port); |
1457 | |
1458 | status = psc_ops->get_ipcr(port); |
1459 | if (status & MPC52xx_PSC_D_DCD) |
1460 | uart_handle_dcd_change(port, !(status & MPC52xx_PSC_DCD)); |
1461 | |
1462 | if (status & MPC52xx_PSC_D_CTS) |
1463 | uart_handle_cts_change(port, !(status & MPC52xx_PSC_CTS)); |
1464 | |
1465 | /* Limit number of iteration */ |
1466 | if (!(--pass)) |
1467 | keepgoing = false; |
1468 | |
1469 | } while (keepgoing); |
1470 | |
1471 | return IRQ_HANDLED; |
1472 | } |
1473 | |
1474 | static irqreturn_t |
1475 | mpc52xx_uart_int(int irq, void *dev_id) |
1476 | { |
1477 | struct uart_port *port = dev_id; |
1478 | irqreturn_t ret; |
1479 | |
1480 | uart_port_lock(up: port); |
1481 | |
1482 | ret = psc_ops->handle_irq(port); |
1483 | |
1484 | uart_port_unlock(up: port); |
1485 | |
1486 | return ret; |
1487 | } |
1488 | |
1489 | /* ======================================================================== */ |
1490 | /* Console ( if applicable ) */ |
1491 | /* ======================================================================== */ |
1492 | |
1493 | #ifdef CONFIG_SERIAL_MPC52xx_CONSOLE |
1494 | |
1495 | static void __init |
1496 | mpc52xx_console_get_options(struct uart_port *port, |
1497 | int *baud, int *parity, int *bits, int *flow) |
1498 | { |
1499 | unsigned char mr1; |
1500 | |
1501 | pr_debug("mpc52xx_console_get_options(port=%p)\n" , port); |
1502 | |
1503 | /* Read the mode registers */ |
1504 | mr1 = psc_ops->get_mr1(port); |
1505 | |
1506 | /* CT{U,L}R are write-only ! */ |
1507 | *baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD; |
1508 | |
1509 | /* Parse them */ |
1510 | switch (mr1 & MPC52xx_PSC_MODE_BITS_MASK) { |
1511 | case MPC52xx_PSC_MODE_5_BITS: |
1512 | *bits = 5; |
1513 | break; |
1514 | case MPC52xx_PSC_MODE_6_BITS: |
1515 | *bits = 6; |
1516 | break; |
1517 | case MPC52xx_PSC_MODE_7_BITS: |
1518 | *bits = 7; |
1519 | break; |
1520 | case MPC52xx_PSC_MODE_8_BITS: |
1521 | default: |
1522 | *bits = 8; |
1523 | } |
1524 | |
1525 | if (mr1 & MPC52xx_PSC_MODE_PARNONE) |
1526 | *parity = 'n'; |
1527 | else |
1528 | *parity = mr1 & MPC52xx_PSC_MODE_PARODD ? 'o' : 'e'; |
1529 | } |
1530 | |
1531 | static void |
1532 | mpc52xx_console_write(struct console *co, const char *s, unsigned int count) |
1533 | { |
1534 | struct uart_port *port = &mpc52xx_uart_ports[co->index]; |
1535 | unsigned int i, j; |
1536 | |
1537 | /* Disable interrupts */ |
1538 | psc_ops->cw_disable_ints(port); |
1539 | |
1540 | /* Wait the TX buffer to be empty */ |
1541 | j = 5000000; /* Maximum wait */ |
1542 | while (!mpc52xx_uart_tx_empty(port) && --j) |
1543 | udelay(1); |
1544 | |
1545 | /* Write all the chars */ |
1546 | for (i = 0; i < count; i++, s++) { |
1547 | /* Line return handling */ |
1548 | if (*s == '\n') |
1549 | psc_ops->write_char(port, '\r'); |
1550 | |
1551 | /* Send the char */ |
1552 | psc_ops->write_char(port, *s); |
1553 | |
1554 | /* Wait the TX buffer to be empty */ |
1555 | j = 20000; /* Maximum wait */ |
1556 | while (!mpc52xx_uart_tx_empty(port) && --j) |
1557 | udelay(1); |
1558 | } |
1559 | |
1560 | /* Restore interrupt state */ |
1561 | psc_ops->cw_restore_ints(port); |
1562 | } |
1563 | |
1564 | |
1565 | static int __init |
1566 | mpc52xx_console_setup(struct console *co, char *options) |
1567 | { |
1568 | struct uart_port *port = &mpc52xx_uart_ports[co->index]; |
1569 | struct device_node *np = mpc52xx_uart_nodes[co->index]; |
1570 | unsigned int uartclk; |
1571 | struct resource res; |
1572 | int ret; |
1573 | |
1574 | int baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD; |
1575 | int bits = 8; |
1576 | int parity = 'n'; |
1577 | int flow = 'n'; |
1578 | |
1579 | pr_debug("mpc52xx_console_setup co=%p, co->index=%i, options=%s\n" , |
1580 | co, co->index, options); |
1581 | |
1582 | if ((co->index < 0) || (co->index >= MPC52xx_PSC_MAXNUM)) { |
1583 | pr_debug("PSC%x out of range\n" , co->index); |
1584 | return -EINVAL; |
1585 | } |
1586 | |
1587 | if (!np) { |
1588 | pr_debug("PSC%x not found in device tree\n" , co->index); |
1589 | return -EINVAL; |
1590 | } |
1591 | |
1592 | pr_debug("Console on ttyPSC%x is %pOF\n" , |
1593 | co->index, mpc52xx_uart_nodes[co->index]); |
1594 | |
1595 | /* Fetch register locations */ |
1596 | ret = of_address_to_resource(np, 0, &res); |
1597 | if (ret) { |
1598 | pr_debug("Could not get resources for PSC%x\n" , co->index); |
1599 | return ret; |
1600 | } |
1601 | |
1602 | uartclk = mpc5xxx_fwnode_get_bus_frequency(of_fwnode_handle(np)); |
1603 | if (uartclk == 0) { |
1604 | pr_debug("Could not find uart clock frequency!\n" ); |
1605 | return -EINVAL; |
1606 | } |
1607 | |
1608 | /* Basic port init. Needed since we use some uart_??? func before |
1609 | * real init for early access */ |
1610 | spin_lock_init(&port->lock); |
1611 | port->uartclk = uartclk; |
1612 | port->ops = &mpc52xx_uart_ops; |
1613 | port->mapbase = res.start; |
1614 | port->membase = ioremap(res.start, sizeof(struct mpc52xx_psc)); |
1615 | port->irq = irq_of_parse_and_map(np, 0); |
1616 | |
1617 | if (port->membase == NULL) |
1618 | return -EINVAL; |
1619 | |
1620 | pr_debug("mpc52xx-psc uart at %p, mapped to %p, irq=%x, freq=%i\n" , |
1621 | (void *)port->mapbase, port->membase, |
1622 | port->irq, port->uartclk); |
1623 | |
1624 | /* Setup the port parameters accoding to options */ |
1625 | if (options) |
1626 | uart_parse_options(options, &baud, &parity, &bits, &flow); |
1627 | else |
1628 | mpc52xx_console_get_options(port, &baud, &parity, &bits, &flow); |
1629 | |
1630 | pr_debug("Setting console parameters: %i %i%c1 flow=%c\n" , |
1631 | baud, bits, parity, flow); |
1632 | |
1633 | return uart_set_options(port, co, baud, parity, bits, flow); |
1634 | } |
1635 | |
1636 | |
1637 | static struct uart_driver mpc52xx_uart_driver; |
1638 | |
1639 | static struct console mpc52xx_console = { |
1640 | .name = "ttyPSC" , |
1641 | .write = mpc52xx_console_write, |
1642 | .device = uart_console_device, |
1643 | .setup = mpc52xx_console_setup, |
1644 | .flags = CON_PRINTBUFFER, |
1645 | .index = -1, /* Specified on the cmdline (e.g. console=ttyPSC0) */ |
1646 | .data = &mpc52xx_uart_driver, |
1647 | }; |
1648 | |
1649 | |
1650 | static int __init |
1651 | mpc52xx_console_init(void) |
1652 | { |
1653 | mpc52xx_uart_of_enumerate(); |
1654 | register_console(&mpc52xx_console); |
1655 | return 0; |
1656 | } |
1657 | |
1658 | console_initcall(mpc52xx_console_init); |
1659 | |
1660 | #define MPC52xx_PSC_CONSOLE &mpc52xx_console |
1661 | #else |
1662 | #define MPC52xx_PSC_CONSOLE NULL |
1663 | #endif |
1664 | |
1665 | |
1666 | /* ======================================================================== */ |
1667 | /* UART Driver */ |
1668 | /* ======================================================================== */ |
1669 | |
1670 | static struct uart_driver mpc52xx_uart_driver = { |
1671 | .driver_name = "mpc52xx_psc_uart" , |
1672 | .dev_name = "ttyPSC" , |
1673 | .major = SERIAL_PSC_MAJOR, |
1674 | .minor = SERIAL_PSC_MINOR, |
1675 | .nr = MPC52xx_PSC_MAXNUM, |
1676 | .cons = MPC52xx_PSC_CONSOLE, |
1677 | }; |
1678 | |
1679 | /* ======================================================================== */ |
1680 | /* OF Platform Driver */ |
1681 | /* ======================================================================== */ |
1682 | |
1683 | static const struct of_device_id mpc52xx_uart_of_match[] = { |
1684 | #ifdef CONFIG_PPC_MPC52xx |
1685 | { .compatible = "fsl,mpc5200b-psc-uart" , .data = &mpc5200b_psc_ops, }, |
1686 | { .compatible = "fsl,mpc5200-psc-uart" , .data = &mpc52xx_psc_ops, }, |
1687 | /* binding used by old lite5200 device trees: */ |
1688 | { .compatible = "mpc5200-psc-uart" , .data = &mpc52xx_psc_ops, }, |
1689 | /* binding used by efika: */ |
1690 | { .compatible = "mpc5200-serial" , .data = &mpc52xx_psc_ops, }, |
1691 | #endif |
1692 | #ifdef CONFIG_PPC_MPC512x |
1693 | { .compatible = "fsl,mpc5121-psc-uart" , .data = &mpc512x_psc_ops, }, |
1694 | { .compatible = "fsl,mpc5125-psc-uart" , .data = &mpc5125_psc_ops, }, |
1695 | #endif |
1696 | {}, |
1697 | }; |
1698 | |
1699 | static int mpc52xx_uart_of_probe(struct platform_device *op) |
1700 | { |
1701 | int idx = -1; |
1702 | unsigned int uartclk; |
1703 | struct uart_port *port = NULL; |
1704 | struct resource res; |
1705 | int ret; |
1706 | |
1707 | /* Check validity & presence */ |
1708 | for (idx = 0; idx < MPC52xx_PSC_MAXNUM; idx++) |
1709 | if (mpc52xx_uart_nodes[idx] == op->dev.of_node) |
1710 | break; |
1711 | if (idx >= MPC52xx_PSC_MAXNUM) |
1712 | return -EINVAL; |
1713 | pr_debug("Found %pOF assigned to ttyPSC%x\n" , |
1714 | mpc52xx_uart_nodes[idx], idx); |
1715 | |
1716 | /* set the uart clock to the input clock of the psc, the different |
1717 | * prescalers are taken into account in the set_baudrate() methods |
1718 | * of the respective chip */ |
1719 | uartclk = mpc5xxx_get_bus_frequency(&op->dev); |
1720 | if (uartclk == 0) { |
1721 | dev_dbg(&op->dev, "Could not find uart clock frequency!\n" ); |
1722 | return -EINVAL; |
1723 | } |
1724 | |
1725 | /* Init the port structure */ |
1726 | port = &mpc52xx_uart_ports[idx]; |
1727 | |
1728 | spin_lock_init(&port->lock); |
1729 | port->uartclk = uartclk; |
1730 | port->fifosize = 512; |
1731 | port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MPC52xx_CONSOLE); |
1732 | port->iotype = UPIO_MEM; |
1733 | port->flags = UPF_BOOT_AUTOCONF | |
1734 | (uart_console(port) ? 0 : UPF_IOREMAP); |
1735 | port->line = idx; |
1736 | port->ops = &mpc52xx_uart_ops; |
1737 | port->dev = &op->dev; |
1738 | |
1739 | /* Search for IRQ and mapbase */ |
1740 | ret = of_address_to_resource(dev: op->dev.of_node, index: 0, r: &res); |
1741 | if (ret) |
1742 | return ret; |
1743 | |
1744 | port->mapbase = res.start; |
1745 | if (!port->mapbase) { |
1746 | dev_dbg(&op->dev, "Could not allocate resources for PSC\n" ); |
1747 | return -EINVAL; |
1748 | } |
1749 | |
1750 | psc_ops->get_irq(port, op->dev.of_node); |
1751 | if (port->irq == 0) { |
1752 | dev_dbg(&op->dev, "Could not get irq\n" ); |
1753 | return -EINVAL; |
1754 | } |
1755 | |
1756 | dev_dbg(&op->dev, "mpc52xx-psc uart at %p, irq=%x, freq=%i\n" , |
1757 | (void *)port->mapbase, port->irq, port->uartclk); |
1758 | |
1759 | /* Add the port to the uart sub-system */ |
1760 | ret = uart_add_one_port(reg: &mpc52xx_uart_driver, port); |
1761 | if (ret) |
1762 | return ret; |
1763 | |
1764 | platform_set_drvdata(pdev: op, data: (void *)port); |
1765 | return 0; |
1766 | } |
1767 | |
1768 | static int |
1769 | mpc52xx_uart_of_remove(struct platform_device *op) |
1770 | { |
1771 | struct uart_port *port = platform_get_drvdata(pdev: op); |
1772 | |
1773 | if (port) |
1774 | uart_remove_one_port(reg: &mpc52xx_uart_driver, port); |
1775 | |
1776 | return 0; |
1777 | } |
1778 | |
1779 | #ifdef CONFIG_PM |
1780 | static int |
1781 | mpc52xx_uart_of_suspend(struct platform_device *op, pm_message_t state) |
1782 | { |
1783 | struct uart_port *port = platform_get_drvdata(pdev: op); |
1784 | |
1785 | if (port) |
1786 | uart_suspend_port(reg: &mpc52xx_uart_driver, port); |
1787 | |
1788 | return 0; |
1789 | } |
1790 | |
1791 | static int |
1792 | mpc52xx_uart_of_resume(struct platform_device *op) |
1793 | { |
1794 | struct uart_port *port = platform_get_drvdata(pdev: op); |
1795 | |
1796 | if (port) |
1797 | uart_resume_port(reg: &mpc52xx_uart_driver, port); |
1798 | |
1799 | return 0; |
1800 | } |
1801 | #endif |
1802 | |
1803 | static void |
1804 | mpc52xx_uart_of_assign(struct device_node *np) |
1805 | { |
1806 | int i; |
1807 | |
1808 | /* Find the first free PSC number */ |
1809 | for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) { |
1810 | if (mpc52xx_uart_nodes[i] == NULL) { |
1811 | of_node_get(np); |
1812 | mpc52xx_uart_nodes[i] = np; |
1813 | return; |
1814 | } |
1815 | } |
1816 | } |
1817 | |
1818 | static void |
1819 | mpc52xx_uart_of_enumerate(void) |
1820 | { |
1821 | static int enum_done; |
1822 | struct device_node *np; |
1823 | const struct of_device_id *match; |
1824 | int i; |
1825 | |
1826 | if (enum_done) |
1827 | return; |
1828 | |
1829 | /* Assign index to each PSC in device tree */ |
1830 | for_each_matching_node(np, mpc52xx_uart_of_match) { |
1831 | match = of_match_node(matches: mpc52xx_uart_of_match, node: np); |
1832 | psc_ops = match->data; |
1833 | mpc52xx_uart_of_assign(np); |
1834 | } |
1835 | |
1836 | enum_done = 1; |
1837 | |
1838 | for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) { |
1839 | if (mpc52xx_uart_nodes[i]) |
1840 | pr_debug("%pOF assigned to ttyPSC%x\n" , |
1841 | mpc52xx_uart_nodes[i], i); |
1842 | } |
1843 | } |
1844 | |
1845 | MODULE_DEVICE_TABLE(of, mpc52xx_uart_of_match); |
1846 | |
1847 | static struct platform_driver mpc52xx_uart_of_driver = { |
1848 | .probe = mpc52xx_uart_of_probe, |
1849 | .remove = mpc52xx_uart_of_remove, |
1850 | #ifdef CONFIG_PM |
1851 | .suspend = mpc52xx_uart_of_suspend, |
1852 | .resume = mpc52xx_uart_of_resume, |
1853 | #endif |
1854 | .driver = { |
1855 | .name = "mpc52xx-psc-uart" , |
1856 | .of_match_table = mpc52xx_uart_of_match, |
1857 | }, |
1858 | }; |
1859 | |
1860 | |
1861 | /* ======================================================================== */ |
1862 | /* Module */ |
1863 | /* ======================================================================== */ |
1864 | |
1865 | static int __init |
1866 | mpc52xx_uart_init(void) |
1867 | { |
1868 | int ret; |
1869 | |
1870 | printk(KERN_INFO "Serial: MPC52xx PSC UART driver\n" ); |
1871 | |
1872 | ret = uart_register_driver(uart: &mpc52xx_uart_driver); |
1873 | if (ret) { |
1874 | printk(KERN_ERR "%s: uart_register_driver failed (%i)\n" , |
1875 | __FILE__, ret); |
1876 | return ret; |
1877 | } |
1878 | |
1879 | mpc52xx_uart_of_enumerate(); |
1880 | |
1881 | /* |
1882 | * Map the PSC FIFO Controller and init if on MPC512x. |
1883 | */ |
1884 | if (psc_ops && psc_ops->fifoc_init) { |
1885 | ret = psc_ops->fifoc_init(); |
1886 | if (ret) |
1887 | goto err_init; |
1888 | } |
1889 | |
1890 | ret = platform_driver_register(&mpc52xx_uart_of_driver); |
1891 | if (ret) { |
1892 | printk(KERN_ERR "%s: platform_driver_register failed (%i)\n" , |
1893 | __FILE__, ret); |
1894 | goto err_reg; |
1895 | } |
1896 | |
1897 | return 0; |
1898 | err_reg: |
1899 | if (psc_ops && psc_ops->fifoc_uninit) |
1900 | psc_ops->fifoc_uninit(); |
1901 | err_init: |
1902 | uart_unregister_driver(uart: &mpc52xx_uart_driver); |
1903 | return ret; |
1904 | } |
1905 | |
1906 | static void __exit |
1907 | mpc52xx_uart_exit(void) |
1908 | { |
1909 | if (psc_ops->fifoc_uninit) |
1910 | psc_ops->fifoc_uninit(); |
1911 | |
1912 | platform_driver_unregister(&mpc52xx_uart_of_driver); |
1913 | uart_unregister_driver(uart: &mpc52xx_uart_driver); |
1914 | } |
1915 | |
1916 | |
1917 | module_init(mpc52xx_uart_init); |
1918 | module_exit(mpc52xx_uart_exit); |
1919 | |
1920 | MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>" ); |
1921 | MODULE_DESCRIPTION("Freescale MPC52xx PSC UART" ); |
1922 | MODULE_LICENSE("GPL" ); |
1923 | |