1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Application UART driver for:
4 * Freescale STMP37XX/STMP378X
5 * Alphascale ASM9260
6 *
7 * Author: dmitry pervushin <dimka@embeddedalley.com>
8 *
9 * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
10 * Provide Alphascale ASM9260 support.
11 * Copyright 2008-2010 Freescale Semiconductor, Inc.
12 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
13 */
14
15#include <linux/kernel.h>
16#include <linux/errno.h>
17#include <linux/init.h>
18#include <linux/console.h>
19#include <linux/interrupt.h>
20#include <linux/module.h>
21#include <linux/slab.h>
22#include <linux/wait.h>
23#include <linux/tty.h>
24#include <linux/tty_driver.h>
25#include <linux/tty_flip.h>
26#include <linux/serial.h>
27#include <linux/serial_core.h>
28#include <linux/platform_device.h>
29#include <linux/device.h>
30#include <linux/clk.h>
31#include <linux/delay.h>
32#include <linux/io.h>
33#include <linux/of.h>
34#include <linux/dma-mapping.h>
35#include <linux/dmaengine.h>
36
37#include <linux/gpio/consumer.h>
38#include <linux/err.h>
39#include <linux/irq.h>
40#include "serial_mctrl_gpio.h"
41
42#define MXS_AUART_PORTS 5
43#define MXS_AUART_FIFO_SIZE 16
44
45#define SET_REG 0x4
46#define CLR_REG 0x8
47#define TOG_REG 0xc
48
49#define AUART_CTRL0 0x00000000
50#define AUART_CTRL1 0x00000010
51#define AUART_CTRL2 0x00000020
52#define AUART_LINECTRL 0x00000030
53#define AUART_LINECTRL2 0x00000040
54#define AUART_INTR 0x00000050
55#define AUART_DATA 0x00000060
56#define AUART_STAT 0x00000070
57#define AUART_DEBUG 0x00000080
58#define AUART_VERSION 0x00000090
59#define AUART_AUTOBAUD 0x000000a0
60
61#define AUART_CTRL0_SFTRST (1 << 31)
62#define AUART_CTRL0_CLKGATE (1 << 30)
63#define AUART_CTRL0_RXTO_ENABLE (1 << 27)
64#define AUART_CTRL0_RXTIMEOUT(v) (((v) & 0x7ff) << 16)
65#define AUART_CTRL0_XFER_COUNT(v) ((v) & 0xffff)
66
67#define AUART_CTRL1_XFER_COUNT(v) ((v) & 0xffff)
68
69#define AUART_CTRL2_DMAONERR (1 << 26)
70#define AUART_CTRL2_TXDMAE (1 << 25)
71#define AUART_CTRL2_RXDMAE (1 << 24)
72
73#define AUART_CTRL2_CTSEN (1 << 15)
74#define AUART_CTRL2_RTSEN (1 << 14)
75#define AUART_CTRL2_RTS (1 << 11)
76#define AUART_CTRL2_RXE (1 << 9)
77#define AUART_CTRL2_TXE (1 << 8)
78#define AUART_CTRL2_UARTEN (1 << 0)
79
80#define AUART_LINECTRL_BAUD_DIV_MAX 0x003fffc0
81#define AUART_LINECTRL_BAUD_DIV_MIN 0x000000ec
82#define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16
83#define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000
84#define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16)
85#define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8
86#define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00
87#define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8)
88#define AUART_LINECTRL_SPS (1 << 7)
89#define AUART_LINECTRL_WLEN_MASK 0x00000060
90#define AUART_LINECTRL_WLEN(v) ((((v) - 5) & 0x3) << 5)
91#define AUART_LINECTRL_FEN (1 << 4)
92#define AUART_LINECTRL_STP2 (1 << 3)
93#define AUART_LINECTRL_EPS (1 << 2)
94#define AUART_LINECTRL_PEN (1 << 1)
95#define AUART_LINECTRL_BRK (1 << 0)
96
97#define AUART_INTR_RTIEN (1 << 22)
98#define AUART_INTR_TXIEN (1 << 21)
99#define AUART_INTR_RXIEN (1 << 20)
100#define AUART_INTR_CTSMIEN (1 << 17)
101#define AUART_INTR_RTIS (1 << 6)
102#define AUART_INTR_TXIS (1 << 5)
103#define AUART_INTR_RXIS (1 << 4)
104#define AUART_INTR_CTSMIS (1 << 1)
105
106#define AUART_STAT_BUSY (1 << 29)
107#define AUART_STAT_CTS (1 << 28)
108#define AUART_STAT_TXFE (1 << 27)
109#define AUART_STAT_TXFF (1 << 25)
110#define AUART_STAT_RXFE (1 << 24)
111#define AUART_STAT_OERR (1 << 19)
112#define AUART_STAT_BERR (1 << 18)
113#define AUART_STAT_PERR (1 << 17)
114#define AUART_STAT_FERR (1 << 16)
115#define AUART_STAT_RXCOUNT_MASK 0xffff
116
117/*
118 * Start of Alphascale asm9260 defines
119 * This list contains only differences of existing bits
120 * between imx2x and asm9260
121 */
122#define ASM9260_HW_CTRL0 0x0000
123/*
124 * RW. Tell the UART to execute the RX DMA Command. The
125 * UART will clear this bit at the end of receive execution.
126 */
127#define ASM9260_BM_CTRL0_RXDMA_RUN BIT(28)
128/* RW. 0 use FIFO for status register; 1 use DMA */
129#define ASM9260_BM_CTRL0_RXTO_SOURCE_STATUS BIT(25)
130/*
131 * RW. RX TIMEOUT Enable. Valid for FIFO and DMA.
132 * Warning: If this bit is set to 0, the RX timeout will not affect receive DMA
133 * operation. If this bit is set to 1, a receive timeout will cause the receive
134 * DMA logic to terminate by filling the remaining DMA bytes with garbage data.
135 */
136#define ASM9260_BM_CTRL0_RXTO_ENABLE BIT(24)
137/*
138 * RW. Receive Timeout Counter Value: number of 8-bit-time to wait before
139 * asserting timeout on the RX input. If the RXFIFO is not empty and the RX
140 * input is idle, then the watchdog counter will decrement each bit-time. Note
141 * 7-bit-time is added to the programmed value, so a value of zero will set
142 * the counter to 7-bit-time, a value of 0x1 gives 15-bit-time and so on. Also
143 * note that the counter is reloaded at the end of each frame, so if the frame
144 * is 10 bits long and the timeout counter value is zero, then timeout will
145 * occur (when FIFO is not empty) even if the RX input is not idle. The default
146 * value is 0x3 (31 bit-time).
147 */
148#define ASM9260_BM_CTRL0_RXTO_MASK (0xff << 16)
149/* TIMEOUT = (100*7+1)*(1/BAUD) */
150#define ASM9260_BM_CTRL0_DEFAULT_RXTIMEOUT (20 << 16)
151
152/* TX ctrl register */
153#define ASM9260_HW_CTRL1 0x0010
154/*
155 * RW. Tell the UART to execute the TX DMA Command. The
156 * UART will clear this bit at the end of transmit execution.
157 */
158#define ASM9260_BM_CTRL1_TXDMA_RUN BIT(28)
159
160#define ASM9260_HW_CTRL2 0x0020
161/*
162 * RW. Receive Interrupt FIFO Level Select.
163 * The trigger points for the receive interrupt are as follows:
164 * ONE_EIGHTHS = 0x0 Trigger on FIFO full to at least 2 of 16 entries.
165 * ONE_QUARTER = 0x1 Trigger on FIFO full to at least 4 of 16 entries.
166 * ONE_HALF = 0x2 Trigger on FIFO full to at least 8 of 16 entries.
167 * THREE_QUARTERS = 0x3 Trigger on FIFO full to at least 12 of 16 entries.
168 * SEVEN_EIGHTHS = 0x4 Trigger on FIFO full to at least 14 of 16 entries.
169 */
170#define ASM9260_BM_CTRL2_RXIFLSEL (7 << 20)
171#define ASM9260_BM_CTRL2_DEFAULT_RXIFLSEL (3 << 20)
172/* RW. Same as RXIFLSEL */
173#define ASM9260_BM_CTRL2_TXIFLSEL (7 << 16)
174#define ASM9260_BM_CTRL2_DEFAULT_TXIFLSEL (2 << 16)
175/* RW. Set DTR. When this bit is 1, the output is 0. */
176#define ASM9260_BM_CTRL2_DTR BIT(10)
177/* RW. Loop Back Enable */
178#define ASM9260_BM_CTRL2_LBE BIT(7)
179#define ASM9260_BM_CTRL2_PORT_ENABLE BIT(0)
180
181#define ASM9260_HW_LINECTRL 0x0030
182/*
183 * RW. Stick Parity Select. When bits 1, 2, and 7 of this register are set, the
184 * parity bit is transmitted and checked as a 0. When bits 1 and 7 are set,
185 * and bit 2 is 0, the parity bit is transmitted and checked as a 1. When this
186 * bit is cleared stick parity is disabled.
187 */
188#define ASM9260_BM_LCTRL_SPS BIT(7)
189/* RW. Word length */
190#define ASM9260_BM_LCTRL_WLEN (3 << 5)
191#define ASM9260_BM_LCTRL_CHRL_5 (0 << 5)
192#define ASM9260_BM_LCTRL_CHRL_6 (1 << 5)
193#define ASM9260_BM_LCTRL_CHRL_7 (2 << 5)
194#define ASM9260_BM_LCTRL_CHRL_8 (3 << 5)
195
196/*
197 * Interrupt register.
198 * contains the interrupt enables and the interrupt status bits
199 */
200#define ASM9260_HW_INTR 0x0040
201/* Tx FIFO EMPTY Raw Interrupt enable */
202#define ASM9260_BM_INTR_TFEIEN BIT(27)
203/* Overrun Error Interrupt Enable. */
204#define ASM9260_BM_INTR_OEIEN BIT(26)
205/* Break Error Interrupt Enable. */
206#define ASM9260_BM_INTR_BEIEN BIT(25)
207/* Parity Error Interrupt Enable. */
208#define ASM9260_BM_INTR_PEIEN BIT(24)
209/* Framing Error Interrupt Enable. */
210#define ASM9260_BM_INTR_FEIEN BIT(23)
211
212/* nUARTDSR Modem Interrupt Enable. */
213#define ASM9260_BM_INTR_DSRMIEN BIT(19)
214/* nUARTDCD Modem Interrupt Enable. */
215#define ASM9260_BM_INTR_DCDMIEN BIT(18)
216/* nUARTRI Modem Interrupt Enable. */
217#define ASM9260_BM_INTR_RIMIEN BIT(16)
218/* Auto-Boud Timeout */
219#define ASM9260_BM_INTR_ABTO BIT(13)
220#define ASM9260_BM_INTR_ABEO BIT(12)
221/* Tx FIFO EMPTY Raw Interrupt state */
222#define ASM9260_BM_INTR_TFEIS BIT(11)
223/* Overrun Error */
224#define ASM9260_BM_INTR_OEIS BIT(10)
225/* Break Error */
226#define ASM9260_BM_INTR_BEIS BIT(9)
227/* Parity Error */
228#define ASM9260_BM_INTR_PEIS BIT(8)
229/* Framing Error */
230#define ASM9260_BM_INTR_FEIS BIT(7)
231#define ASM9260_BM_INTR_DSRMIS BIT(3)
232#define ASM9260_BM_INTR_DCDMIS BIT(2)
233#define ASM9260_BM_INTR_RIMIS BIT(0)
234
235/*
236 * RW. In DMA mode, up to 4 Received/Transmit characters can be accessed at a
237 * time. In PIO mode, only one character can be accessed at a time. The status
238 * register contains the receive data flags and valid bits.
239 */
240#define ASM9260_HW_DATA 0x0050
241
242#define ASM9260_HW_STAT 0x0060
243/* RO. If 1, UARTAPP is present in this product. */
244#define ASM9260_BM_STAT_PRESENT BIT(31)
245/* RO. If 1, HISPEED is present in this product. */
246#define ASM9260_BM_STAT_HISPEED BIT(30)
247/* RO. Receive FIFO Full. */
248#define ASM9260_BM_STAT_RXFULL BIT(26)
249
250/* RO. The UART Debug Register contains the state of the DMA signals. */
251#define ASM9260_HW_DEBUG 0x0070
252/* DMA Command Run Status */
253#define ASM9260_BM_DEBUG_TXDMARUN BIT(5)
254#define ASM9260_BM_DEBUG_RXDMARUN BIT(4)
255/* DMA Command End Status */
256#define ASM9260_BM_DEBUG_TXCMDEND BIT(3)
257#define ASM9260_BM_DEBUG_RXCMDEND BIT(2)
258/* DMA Request Status */
259#define ASM9260_BM_DEBUG_TXDMARQ BIT(1)
260#define ASM9260_BM_DEBUG_RXDMARQ BIT(0)
261
262#define ASM9260_HW_ILPR 0x0080
263
264#define ASM9260_HW_RS485CTRL 0x0090
265/*
266 * RW. This bit reverses the polarity of the direction control signal on the RTS
267 * (or DTR) pin.
268 * If 0, The direction control pin will be driven to logic ‘0’ when the
269 * transmitter has data to be sent. It will be driven to logic ‘1’ after the
270 * last bit of data has been transmitted.
271 */
272#define ASM9260_BM_RS485CTRL_ONIV BIT(5)
273/* RW. Enable Auto Direction Control. */
274#define ASM9260_BM_RS485CTRL_DIR_CTRL BIT(4)
275/*
276 * RW. If 0 and DIR_CTRL = 1, pin RTS is used for direction control.
277 * If 1 and DIR_CTRL = 1, pin DTR is used for direction control.
278 */
279#define ASM9260_BM_RS485CTRL_PINSEL BIT(3)
280/* RW. Enable Auto Address Detect (AAD). */
281#define ASM9260_BM_RS485CTRL_AADEN BIT(2)
282/* RW. Disable receiver. */
283#define ASM9260_BM_RS485CTRL_RXDIS BIT(1)
284/* RW. Enable RS-485/EIA-485 Normal Multidrop Mode (NMM) */
285#define ASM9260_BM_RS485CTRL_RS485EN BIT(0)
286
287#define ASM9260_HW_RS485ADRMATCH 0x00a0
288/* Contains the address match value. */
289#define ASM9260_BM_RS485ADRMATCH_MASK (0xff << 0)
290
291#define ASM9260_HW_RS485DLY 0x00b0
292/*
293 * RW. Contains the direction control (RTS or DTR) delay value. This delay time
294 * is in periods of the baud clock.
295 */
296#define ASM9260_BM_RS485DLY_MASK (0xff << 0)
297
298#define ASM9260_HW_AUTOBAUD 0x00c0
299/* WO. Auto-baud time-out interrupt clear bit. */
300#define ASM9260_BM_AUTOBAUD_TO_INT_CLR BIT(9)
301/* WO. End of auto-baud interrupt clear bit. */
302#define ASM9260_BM_AUTOBAUD_EO_INT_CLR BIT(8)
303/* Restart in case of timeout (counter restarts at next UART Rx falling edge) */
304#define ASM9260_BM_AUTOBAUD_AUTORESTART BIT(2)
305/* Auto-baud mode select bit. 0 - Mode 0, 1 - Mode 1. */
306#define ASM9260_BM_AUTOBAUD_MODE BIT(1)
307/*
308 * Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is
309 * automatically cleared after auto-baud completion.
310 */
311#define ASM9260_BM_AUTOBAUD_START BIT(0)
312
313#define ASM9260_HW_CTRL3 0x00d0
314#define ASM9260_BM_CTRL3_OUTCLK_DIV_MASK (0xffff << 16)
315/*
316 * RW. Provide clk over OUTCLK pin. In case of asm9260 it can be configured on
317 * pins 137 and 144.
318 */
319#define ASM9260_BM_CTRL3_MASTERMODE BIT(6)
320/* RW. Baud Rate Mode: 1 - Enable sync mode. 0 - async mode. */
321#define ASM9260_BM_CTRL3_SYNCMODE BIT(4)
322/* RW. 1 - MSB bit send frist; 0 - LSB bit frist. */
323#define ASM9260_BM_CTRL3_MSBF BIT(2)
324/* RW. 1 - sample rate = 8 x Baudrate; 0 - sample rate = 16 x Baudrate. */
325#define ASM9260_BM_CTRL3_BAUD8 BIT(1)
326/* RW. 1 - Set word length to 9bit. 0 - use ASM9260_BM_LCTRL_WLEN */
327#define ASM9260_BM_CTRL3_9BIT BIT(0)
328
329#define ASM9260_HW_ISO7816_CTRL 0x00e0
330/* RW. Enable High Speed mode. */
331#define ASM9260_BM_ISO7816CTRL_HS BIT(12)
332/* Disable Successive Receive NACK */
333#define ASM9260_BM_ISO7816CTRL_DS_NACK BIT(8)
334#define ASM9260_BM_ISO7816CTRL_MAX_ITER_MASK (0xff << 4)
335/* Receive NACK Inhibit */
336#define ASM9260_BM_ISO7816CTRL_INACK BIT(3)
337#define ASM9260_BM_ISO7816CTRL_NEG_DATA BIT(2)
338/* RW. 1 - ISO7816 mode; 0 - USART mode */
339#define ASM9260_BM_ISO7816CTRL_ENABLE BIT(0)
340
341#define ASM9260_HW_ISO7816_ERRCNT 0x00f0
342/* Parity error counter. Will be cleared after reading */
343#define ASM9260_BM_ISO7816_NB_ERRORS_MASK (0xff << 0)
344
345#define ASM9260_HW_ISO7816_STATUS 0x0100
346/* Max number of Repetitions Reached */
347#define ASM9260_BM_ISO7816_STAT_ITERATION BIT(0)
348
349/* End of Alphascale asm9260 defines */
350
351static struct uart_driver auart_driver;
352
353enum mxs_auart_type {
354 IMX23_AUART,
355 IMX28_AUART,
356 ASM9260_AUART,
357};
358
359struct vendor_data {
360 const u16 *reg_offset;
361};
362
363enum {
364 REG_CTRL0,
365 REG_CTRL1,
366 REG_CTRL2,
367 REG_LINECTRL,
368 REG_LINECTRL2,
369 REG_INTR,
370 REG_DATA,
371 REG_STAT,
372 REG_DEBUG,
373 REG_VERSION,
374 REG_AUTOBAUD,
375
376 /* The size of the array - must be last */
377 REG_ARRAY_SIZE,
378};
379
380static const u16 mxs_asm9260_offsets[REG_ARRAY_SIZE] = {
381 [REG_CTRL0] = ASM9260_HW_CTRL0,
382 [REG_CTRL1] = ASM9260_HW_CTRL1,
383 [REG_CTRL2] = ASM9260_HW_CTRL2,
384 [REG_LINECTRL] = ASM9260_HW_LINECTRL,
385 [REG_INTR] = ASM9260_HW_INTR,
386 [REG_DATA] = ASM9260_HW_DATA,
387 [REG_STAT] = ASM9260_HW_STAT,
388 [REG_DEBUG] = ASM9260_HW_DEBUG,
389 [REG_AUTOBAUD] = ASM9260_HW_AUTOBAUD,
390};
391
392static const u16 mxs_stmp37xx_offsets[REG_ARRAY_SIZE] = {
393 [REG_CTRL0] = AUART_CTRL0,
394 [REG_CTRL1] = AUART_CTRL1,
395 [REG_CTRL2] = AUART_CTRL2,
396 [REG_LINECTRL] = AUART_LINECTRL,
397 [REG_LINECTRL2] = AUART_LINECTRL2,
398 [REG_INTR] = AUART_INTR,
399 [REG_DATA] = AUART_DATA,
400 [REG_STAT] = AUART_STAT,
401 [REG_DEBUG] = AUART_DEBUG,
402 [REG_VERSION] = AUART_VERSION,
403 [REG_AUTOBAUD] = AUART_AUTOBAUD,
404};
405
406static const struct vendor_data vendor_alphascale_asm9260 = {
407 .reg_offset = mxs_asm9260_offsets,
408};
409
410static const struct vendor_data vendor_freescale_stmp37xx = {
411 .reg_offset = mxs_stmp37xx_offsets,
412};
413
414struct mxs_auart_port {
415 struct uart_port port;
416
417#define MXS_AUART_DMA_ENABLED 0x2
418#define MXS_AUART_DMA_TX_SYNC 2 /* bit 2 */
419#define MXS_AUART_DMA_RX_READY 3 /* bit 3 */
420#define MXS_AUART_RTSCTS 4 /* bit 4 */
421 unsigned long flags;
422 unsigned int mctrl_prev;
423 enum mxs_auart_type devtype;
424 const struct vendor_data *vendor;
425
426 struct clk *clk;
427 struct clk *clk_ahb;
428 struct device *dev;
429
430 /* for DMA */
431 struct scatterlist tx_sgl;
432 struct dma_chan *tx_dma_chan;
433 void *tx_dma_buf;
434
435 struct scatterlist rx_sgl;
436 struct dma_chan *rx_dma_chan;
437 void *rx_dma_buf;
438
439 struct mctrl_gpios *gpios;
440 int gpio_irq[UART_GPIO_MAX];
441 bool ms_irq_enabled;
442};
443
444static const struct of_device_id mxs_auart_dt_ids[] = {
445 {
446 .compatible = "fsl,imx28-auart",
447 .data = (const void *)IMX28_AUART
448 }, {
449 .compatible = "fsl,imx23-auart",
450 .data = (const void *)IMX23_AUART
451 }, {
452 .compatible = "alphascale,asm9260-auart",
453 .data = (const void *)ASM9260_AUART
454 }, { /* sentinel */ }
455};
456MODULE_DEVICE_TABLE(of, mxs_auart_dt_ids);
457
458static inline int is_imx28_auart(struct mxs_auart_port *s)
459{
460 return s->devtype == IMX28_AUART;
461}
462
463static inline int is_asm9260_auart(struct mxs_auart_port *s)
464{
465 return s->devtype == ASM9260_AUART;
466}
467
468static inline bool auart_dma_enabled(struct mxs_auart_port *s)
469{
470 return s->flags & MXS_AUART_DMA_ENABLED;
471}
472
473static unsigned int mxs_reg_to_offset(const struct mxs_auart_port *uap,
474 unsigned int reg)
475{
476 return uap->vendor->reg_offset[reg];
477}
478
479static unsigned int mxs_read(const struct mxs_auart_port *uap,
480 unsigned int reg)
481{
482 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
483
484 return readl_relaxed(addr);
485}
486
487static void mxs_write(unsigned int val, struct mxs_auart_port *uap,
488 unsigned int reg)
489{
490 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
491
492 writel_relaxed(val, addr);
493}
494
495static void mxs_set(unsigned int val, struct mxs_auart_port *uap,
496 unsigned int reg)
497{
498 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
499
500 writel_relaxed(val, addr + SET_REG);
501}
502
503static void mxs_clr(unsigned int val, struct mxs_auart_port *uap,
504 unsigned int reg)
505{
506 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
507
508 writel_relaxed(val, addr + CLR_REG);
509}
510
511static void mxs_auart_stop_tx(struct uart_port *u);
512
513#define to_auart_port(u) container_of(u, struct mxs_auart_port, port)
514
515static void mxs_auart_tx_chars(struct mxs_auart_port *s);
516
517static void dma_tx_callback(void *param)
518{
519 struct mxs_auart_port *s = param;
520 struct circ_buf *xmit = &s->port.state->xmit;
521
522 dma_unmap_sg(s->dev, &s->tx_sgl, 1, DMA_TO_DEVICE);
523
524 /* clear the bit used to serialize the DMA tx. */
525 clear_bit(MXS_AUART_DMA_TX_SYNC, addr: &s->flags);
526 smp_mb__after_atomic();
527
528 /* wake up the possible processes. */
529 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
530 uart_write_wakeup(port: &s->port);
531
532 mxs_auart_tx_chars(s);
533}
534
535static int mxs_auart_dma_tx(struct mxs_auart_port *s, int size)
536{
537 struct dma_async_tx_descriptor *desc;
538 struct scatterlist *sgl = &s->tx_sgl;
539 struct dma_chan *channel = s->tx_dma_chan;
540 u32 pio;
541
542 /* [1] : send PIO. Note, the first pio word is CTRL1. */
543 pio = AUART_CTRL1_XFER_COUNT(size);
544 desc = dmaengine_prep_slave_sg(chan: channel, sgl: (struct scatterlist *)&pio,
545 sg_len: 1, dir: DMA_TRANS_NONE, flags: 0);
546 if (!desc) {
547 dev_err(s->dev, "step 1 error\n");
548 return -EINVAL;
549 }
550
551 /* [2] : set DMA buffer. */
552 sg_init_one(sgl, s->tx_dma_buf, size);
553 dma_map_sg(s->dev, sgl, 1, DMA_TO_DEVICE);
554 desc = dmaengine_prep_slave_sg(chan: channel, sgl,
555 sg_len: 1, dir: DMA_MEM_TO_DEV, flags: DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
556 if (!desc) {
557 dev_err(s->dev, "step 2 error\n");
558 return -EINVAL;
559 }
560
561 /* [3] : submit the DMA */
562 desc->callback = dma_tx_callback;
563 desc->callback_param = s;
564 dmaengine_submit(desc);
565 dma_async_issue_pending(chan: channel);
566 return 0;
567}
568
569static void mxs_auart_tx_chars(struct mxs_auart_port *s)
570{
571 struct circ_buf *xmit = &s->port.state->xmit;
572 bool pending;
573 u8 ch;
574
575 if (auart_dma_enabled(s)) {
576 u32 i = 0;
577 int size;
578 void *buffer = s->tx_dma_buf;
579
580 if (test_and_set_bit(MXS_AUART_DMA_TX_SYNC, addr: &s->flags))
581 return;
582
583 while (!uart_circ_empty(xmit) && !uart_tx_stopped(port: &s->port)) {
584 size = min_t(u32, UART_XMIT_SIZE - i,
585 CIRC_CNT_TO_END(xmit->head,
586 xmit->tail,
587 UART_XMIT_SIZE));
588 memcpy(buffer + i, xmit->buf + xmit->tail, size);
589 xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1);
590
591 i += size;
592 if (i >= UART_XMIT_SIZE)
593 break;
594 }
595
596 if (uart_tx_stopped(port: &s->port))
597 mxs_auart_stop_tx(u: &s->port);
598
599 if (i) {
600 mxs_auart_dma_tx(s, size: i);
601 } else {
602 clear_bit(MXS_AUART_DMA_TX_SYNC, addr: &s->flags);
603 smp_mb__after_atomic();
604 }
605 return;
606 }
607
608 pending = uart_port_tx(&s->port, ch,
609 !(mxs_read(s, REG_STAT) & AUART_STAT_TXFF),
610 mxs_write(ch, s, REG_DATA));
611 if (pending)
612 mxs_set(AUART_INTR_TXIEN, uap: s, reg: REG_INTR);
613 else
614 mxs_clr(AUART_INTR_TXIEN, uap: s, reg: REG_INTR);
615}
616
617static void mxs_auart_rx_char(struct mxs_auart_port *s)
618{
619 u32 stat;
620 u8 c, flag;
621
622 c = mxs_read(uap: s, reg: REG_DATA);
623 stat = mxs_read(uap: s, reg: REG_STAT);
624
625 flag = TTY_NORMAL;
626 s->port.icount.rx++;
627
628 if (stat & AUART_STAT_BERR) {
629 s->port.icount.brk++;
630 if (uart_handle_break(port: &s->port))
631 goto out;
632 } else if (stat & AUART_STAT_PERR) {
633 s->port.icount.parity++;
634 } else if (stat & AUART_STAT_FERR) {
635 s->port.icount.frame++;
636 }
637
638 /*
639 * Mask off conditions which should be ingored.
640 */
641 stat &= s->port.read_status_mask;
642
643 if (stat & AUART_STAT_BERR) {
644 flag = TTY_BREAK;
645 } else if (stat & AUART_STAT_PERR)
646 flag = TTY_PARITY;
647 else if (stat & AUART_STAT_FERR)
648 flag = TTY_FRAME;
649
650 if (stat & AUART_STAT_OERR)
651 s->port.icount.overrun++;
652
653 if (uart_handle_sysrq_char(port: &s->port, ch: c))
654 goto out;
655
656 uart_insert_char(port: &s->port, status: stat, AUART_STAT_OERR, ch: c, flag);
657out:
658 mxs_write(val: stat, uap: s, reg: REG_STAT);
659}
660
661static void mxs_auart_rx_chars(struct mxs_auart_port *s)
662{
663 u32 stat = 0;
664
665 for (;;) {
666 stat = mxs_read(uap: s, reg: REG_STAT);
667 if (stat & AUART_STAT_RXFE)
668 break;
669 mxs_auart_rx_char(s);
670 }
671
672 mxs_write(val: stat, uap: s, reg: REG_STAT);
673 tty_flip_buffer_push(port: &s->port.state->port);
674}
675
676static int mxs_auart_request_port(struct uart_port *u)
677{
678 return 0;
679}
680
681static int mxs_auart_verify_port(struct uart_port *u,
682 struct serial_struct *ser)
683{
684 if (u->type != PORT_UNKNOWN && u->type != PORT_IMX)
685 return -EINVAL;
686 return 0;
687}
688
689static void mxs_auart_config_port(struct uart_port *u, int flags)
690{
691}
692
693static const char *mxs_auart_type(struct uart_port *u)
694{
695 struct mxs_auart_port *s = to_auart_port(u);
696
697 return dev_name(dev: s->dev);
698}
699
700static void mxs_auart_release_port(struct uart_port *u)
701{
702}
703
704static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
705{
706 struct mxs_auart_port *s = to_auart_port(u);
707
708 u32 ctrl = mxs_read(uap: s, reg: REG_CTRL2);
709
710 ctrl &= ~(AUART_CTRL2_RTSEN | AUART_CTRL2_RTS);
711 if (mctrl & TIOCM_RTS) {
712 if (uart_cts_enabled(uport: u))
713 ctrl |= AUART_CTRL2_RTSEN;
714 else
715 ctrl |= AUART_CTRL2_RTS;
716 }
717
718 mxs_write(val: ctrl, uap: s, reg: REG_CTRL2);
719
720 mctrl_gpio_set(gpios: s->gpios, mctrl);
721}
722
723#define MCTRL_ANY_DELTA (TIOCM_RI | TIOCM_DSR | TIOCM_CD | TIOCM_CTS)
724static u32 mxs_auart_modem_status(struct mxs_auart_port *s, u32 mctrl)
725{
726 u32 mctrl_diff;
727
728 mctrl_diff = mctrl ^ s->mctrl_prev;
729 s->mctrl_prev = mctrl;
730 if (mctrl_diff & MCTRL_ANY_DELTA && s->ms_irq_enabled &&
731 s->port.state != NULL) {
732 if (mctrl_diff & TIOCM_RI)
733 s->port.icount.rng++;
734 if (mctrl_diff & TIOCM_DSR)
735 s->port.icount.dsr++;
736 if (mctrl_diff & TIOCM_CD)
737 uart_handle_dcd_change(uport: &s->port, active: mctrl & TIOCM_CD);
738 if (mctrl_diff & TIOCM_CTS)
739 uart_handle_cts_change(uport: &s->port, active: mctrl & TIOCM_CTS);
740
741 wake_up_interruptible(&s->port.state->port.delta_msr_wait);
742 }
743 return mctrl;
744}
745
746static u32 mxs_auart_get_mctrl(struct uart_port *u)
747{
748 struct mxs_auart_port *s = to_auart_port(u);
749 u32 stat = mxs_read(uap: s, reg: REG_STAT);
750 u32 mctrl = 0;
751
752 if (stat & AUART_STAT_CTS)
753 mctrl |= TIOCM_CTS;
754
755 return mctrl_gpio_get(gpios: s->gpios, mctrl: &mctrl);
756}
757
758/*
759 * Enable modem status interrupts
760 */
761static void mxs_auart_enable_ms(struct uart_port *port)
762{
763 struct mxs_auart_port *s = to_auart_port(port);
764
765 /*
766 * Interrupt should not be enabled twice
767 */
768 if (s->ms_irq_enabled)
769 return;
770
771 s->ms_irq_enabled = true;
772
773 if (s->gpio_irq[UART_GPIO_CTS] >= 0)
774 enable_irq(irq: s->gpio_irq[UART_GPIO_CTS]);
775 /* TODO: enable AUART_INTR_CTSMIEN otherwise */
776
777 if (s->gpio_irq[UART_GPIO_DSR] >= 0)
778 enable_irq(irq: s->gpio_irq[UART_GPIO_DSR]);
779
780 if (s->gpio_irq[UART_GPIO_RI] >= 0)
781 enable_irq(irq: s->gpio_irq[UART_GPIO_RI]);
782
783 if (s->gpio_irq[UART_GPIO_DCD] >= 0)
784 enable_irq(irq: s->gpio_irq[UART_GPIO_DCD]);
785}
786
787/*
788 * Disable modem status interrupts
789 */
790static void mxs_auart_disable_ms(struct uart_port *port)
791{
792 struct mxs_auart_port *s = to_auart_port(port);
793
794 /*
795 * Interrupt should not be disabled twice
796 */
797 if (!s->ms_irq_enabled)
798 return;
799
800 s->ms_irq_enabled = false;
801
802 if (s->gpio_irq[UART_GPIO_CTS] >= 0)
803 disable_irq(irq: s->gpio_irq[UART_GPIO_CTS]);
804 /* TODO: disable AUART_INTR_CTSMIEN otherwise */
805
806 if (s->gpio_irq[UART_GPIO_DSR] >= 0)
807 disable_irq(irq: s->gpio_irq[UART_GPIO_DSR]);
808
809 if (s->gpio_irq[UART_GPIO_RI] >= 0)
810 disable_irq(irq: s->gpio_irq[UART_GPIO_RI]);
811
812 if (s->gpio_irq[UART_GPIO_DCD] >= 0)
813 disable_irq(irq: s->gpio_irq[UART_GPIO_DCD]);
814}
815
816static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s);
817static void dma_rx_callback(void *arg)
818{
819 struct mxs_auart_port *s = (struct mxs_auart_port *) arg;
820 struct tty_port *port = &s->port.state->port;
821 int count;
822 u32 stat;
823
824 dma_unmap_sg(s->dev, &s->rx_sgl, 1, DMA_FROM_DEVICE);
825
826 stat = mxs_read(uap: s, reg: REG_STAT);
827 stat &= ~(AUART_STAT_OERR | AUART_STAT_BERR |
828 AUART_STAT_PERR | AUART_STAT_FERR);
829
830 count = stat & AUART_STAT_RXCOUNT_MASK;
831 tty_insert_flip_string(port, chars: s->rx_dma_buf, size: count);
832
833 mxs_write(val: stat, uap: s, reg: REG_STAT);
834 tty_flip_buffer_push(port);
835
836 /* start the next DMA for RX. */
837 mxs_auart_dma_prep_rx(s);
838}
839
840static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s)
841{
842 struct dma_async_tx_descriptor *desc;
843 struct scatterlist *sgl = &s->rx_sgl;
844 struct dma_chan *channel = s->rx_dma_chan;
845 u32 pio[1];
846
847 /* [1] : send PIO */
848 pio[0] = AUART_CTRL0_RXTO_ENABLE
849 | AUART_CTRL0_RXTIMEOUT(0x80)
850 | AUART_CTRL0_XFER_COUNT(UART_XMIT_SIZE);
851 desc = dmaengine_prep_slave_sg(chan: channel, sgl: (struct scatterlist *)pio,
852 sg_len: 1, dir: DMA_TRANS_NONE, flags: 0);
853 if (!desc) {
854 dev_err(s->dev, "step 1 error\n");
855 return -EINVAL;
856 }
857
858 /* [2] : send DMA request */
859 sg_init_one(sgl, s->rx_dma_buf, UART_XMIT_SIZE);
860 dma_map_sg(s->dev, sgl, 1, DMA_FROM_DEVICE);
861 desc = dmaengine_prep_slave_sg(chan: channel, sgl, sg_len: 1, dir: DMA_DEV_TO_MEM,
862 flags: DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
863 if (!desc) {
864 dev_err(s->dev, "step 2 error\n");
865 return -1;
866 }
867
868 /* [3] : submit the DMA, but do not issue it. */
869 desc->callback = dma_rx_callback;
870 desc->callback_param = s;
871 dmaengine_submit(desc);
872 dma_async_issue_pending(chan: channel);
873 return 0;
874}
875
876static void mxs_auart_dma_exit_channel(struct mxs_auart_port *s)
877{
878 if (s->tx_dma_chan) {
879 dma_release_channel(chan: s->tx_dma_chan);
880 s->tx_dma_chan = NULL;
881 }
882 if (s->rx_dma_chan) {
883 dma_release_channel(chan: s->rx_dma_chan);
884 s->rx_dma_chan = NULL;
885 }
886
887 kfree(objp: s->tx_dma_buf);
888 kfree(objp: s->rx_dma_buf);
889 s->tx_dma_buf = NULL;
890 s->rx_dma_buf = NULL;
891}
892
893static void mxs_auart_dma_exit(struct mxs_auart_port *s)
894{
895
896 mxs_clr(AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE | AUART_CTRL2_DMAONERR,
897 uap: s, reg: REG_CTRL2);
898
899 mxs_auart_dma_exit_channel(s);
900 s->flags &= ~MXS_AUART_DMA_ENABLED;
901 clear_bit(MXS_AUART_DMA_TX_SYNC, addr: &s->flags);
902 clear_bit(MXS_AUART_DMA_RX_READY, addr: &s->flags);
903}
904
905static int mxs_auart_dma_init(struct mxs_auart_port *s)
906{
907 if (auart_dma_enabled(s))
908 return 0;
909
910 /* init for RX */
911 s->rx_dma_chan = dma_request_slave_channel(dev: s->dev, name: "rx");
912 if (!s->rx_dma_chan)
913 goto err_out;
914 s->rx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
915 if (!s->rx_dma_buf)
916 goto err_out;
917
918 /* init for TX */
919 s->tx_dma_chan = dma_request_slave_channel(dev: s->dev, name: "tx");
920 if (!s->tx_dma_chan)
921 goto err_out;
922 s->tx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
923 if (!s->tx_dma_buf)
924 goto err_out;
925
926 /* set the flags */
927 s->flags |= MXS_AUART_DMA_ENABLED;
928 dev_dbg(s->dev, "enabled the DMA support.");
929
930 /* The DMA buffer is now the FIFO the TTY subsystem can use */
931 s->port.fifosize = UART_XMIT_SIZE;
932
933 return 0;
934
935err_out:
936 mxs_auart_dma_exit_channel(s);
937 return -EINVAL;
938
939}
940
941#define RTS_AT_AUART() !mctrl_gpio_to_gpiod(s->gpios, UART_GPIO_RTS)
942#define CTS_AT_AUART() !mctrl_gpio_to_gpiod(s->gpios, UART_GPIO_CTS)
943static void mxs_auart_settermios(struct uart_port *u,
944 struct ktermios *termios,
945 const struct ktermios *old)
946{
947 struct mxs_auart_port *s = to_auart_port(u);
948 u32 ctrl, ctrl2, div;
949 unsigned int cflag, baud, baud_min, baud_max;
950
951 cflag = termios->c_cflag;
952
953 ctrl = AUART_LINECTRL_FEN;
954 ctrl2 = mxs_read(uap: s, reg: REG_CTRL2);
955
956 ctrl |= AUART_LINECTRL_WLEN(tty_get_char_size(cflag));
957
958 /* parity */
959 if (cflag & PARENB) {
960 ctrl |= AUART_LINECTRL_PEN;
961 if ((cflag & PARODD) == 0)
962 ctrl |= AUART_LINECTRL_EPS;
963 if (cflag & CMSPAR)
964 ctrl |= AUART_LINECTRL_SPS;
965 }
966
967 u->read_status_mask = AUART_STAT_OERR;
968
969 if (termios->c_iflag & INPCK)
970 u->read_status_mask |= AUART_STAT_PERR;
971 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
972 u->read_status_mask |= AUART_STAT_BERR;
973
974 /*
975 * Characters to ignore
976 */
977 u->ignore_status_mask = 0;
978 if (termios->c_iflag & IGNPAR)
979 u->ignore_status_mask |= AUART_STAT_PERR;
980 if (termios->c_iflag & IGNBRK) {
981 u->ignore_status_mask |= AUART_STAT_BERR;
982 /*
983 * If we're ignoring parity and break indicators,
984 * ignore overruns too (for real raw support).
985 */
986 if (termios->c_iflag & IGNPAR)
987 u->ignore_status_mask |= AUART_STAT_OERR;
988 }
989
990 /*
991 * ignore all characters if CREAD is not set
992 */
993 if (cflag & CREAD)
994 ctrl2 |= AUART_CTRL2_RXE;
995 else
996 ctrl2 &= ~AUART_CTRL2_RXE;
997
998 /* figure out the stop bits requested */
999 if (cflag & CSTOPB)
1000 ctrl |= AUART_LINECTRL_STP2;
1001
1002 /* figure out the hardware flow control settings */
1003 ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN);
1004 if (cflag & CRTSCTS) {
1005 /*
1006 * The DMA has a bug(see errata:2836) in mx23.
1007 * So we can not implement the DMA for auart in mx23,
1008 * we can only implement the DMA support for auart
1009 * in mx28.
1010 */
1011 if (is_imx28_auart(s)
1012 && test_bit(MXS_AUART_RTSCTS, &s->flags)) {
1013 if (!mxs_auart_dma_init(s))
1014 /* enable DMA tranfer */
1015 ctrl2 |= AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE
1016 | AUART_CTRL2_DMAONERR;
1017 }
1018 /* Even if RTS is GPIO line RTSEN can be enabled because
1019 * the pinctrl configuration decides about RTS pin function */
1020 ctrl2 |= AUART_CTRL2_RTSEN;
1021 if (CTS_AT_AUART())
1022 ctrl2 |= AUART_CTRL2_CTSEN;
1023 }
1024
1025 /* set baud rate */
1026 if (is_asm9260_auart(s)) {
1027 baud = uart_get_baud_rate(port: u, termios, old,
1028 min: u->uartclk * 4 / 0x3FFFFF,
1029 max: u->uartclk / 16);
1030 div = u->uartclk * 4 / baud;
1031 } else {
1032 baud_min = DIV_ROUND_UP(u->uartclk * 32,
1033 AUART_LINECTRL_BAUD_DIV_MAX);
1034 baud_max = u->uartclk * 32 / AUART_LINECTRL_BAUD_DIV_MIN;
1035 baud = uart_get_baud_rate(port: u, termios, old, min: baud_min, max: baud_max);
1036 div = DIV_ROUND_CLOSEST(u->uartclk * 32, baud);
1037 }
1038
1039 ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F);
1040 ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6);
1041 mxs_write(val: ctrl, uap: s, reg: REG_LINECTRL);
1042
1043 mxs_write(val: ctrl2, uap: s, reg: REG_CTRL2);
1044
1045 uart_update_timeout(port: u, cflag: termios->c_cflag, baud);
1046
1047 /* prepare for the DMA RX. */
1048 if (auart_dma_enabled(s) &&
1049 !test_and_set_bit(MXS_AUART_DMA_RX_READY, addr: &s->flags)) {
1050 if (!mxs_auart_dma_prep_rx(s)) {
1051 /* Disable the normal RX interrupt. */
1052 mxs_clr(AUART_INTR_RXIEN | AUART_INTR_RTIEN,
1053 uap: s, reg: REG_INTR);
1054 } else {
1055 mxs_auart_dma_exit(s);
1056 dev_err(s->dev, "We can not start up the DMA.\n");
1057 }
1058 }
1059
1060 /* CTS flow-control and modem-status interrupts */
1061 if (UART_ENABLE_MS(u, termios->c_cflag))
1062 mxs_auart_enable_ms(port: u);
1063 else
1064 mxs_auart_disable_ms(port: u);
1065}
1066
1067static void mxs_auart_set_ldisc(struct uart_port *port,
1068 struct ktermios *termios)
1069{
1070 if (termios->c_line == N_PPS) {
1071 port->flags |= UPF_HARDPPS_CD;
1072 mxs_auart_enable_ms(port);
1073 } else {
1074 port->flags &= ~UPF_HARDPPS_CD;
1075 }
1076}
1077
1078static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
1079{
1080 u32 istat;
1081 struct mxs_auart_port *s = context;
1082 u32 mctrl_temp = s->mctrl_prev;
1083 u32 stat = mxs_read(uap: s, reg: REG_STAT);
1084
1085 istat = mxs_read(uap: s, reg: REG_INTR);
1086
1087 /* ack irq */
1088 mxs_clr(val: istat & (AUART_INTR_RTIS | AUART_INTR_TXIS | AUART_INTR_RXIS
1089 | AUART_INTR_CTSMIS), uap: s, reg: REG_INTR);
1090
1091 /*
1092 * Dealing with GPIO interrupt
1093 */
1094 if (irq == s->gpio_irq[UART_GPIO_CTS] ||
1095 irq == s->gpio_irq[UART_GPIO_DCD] ||
1096 irq == s->gpio_irq[UART_GPIO_DSR] ||
1097 irq == s->gpio_irq[UART_GPIO_RI])
1098 mxs_auart_modem_status(s,
1099 mctrl: mctrl_gpio_get(gpios: s->gpios, mctrl: &mctrl_temp));
1100
1101 if (istat & AUART_INTR_CTSMIS) {
1102 if (CTS_AT_AUART() && s->ms_irq_enabled)
1103 uart_handle_cts_change(uport: &s->port,
1104 active: stat & AUART_STAT_CTS);
1105 mxs_clr(AUART_INTR_CTSMIS, uap: s, reg: REG_INTR);
1106 istat &= ~AUART_INTR_CTSMIS;
1107 }
1108
1109 if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) {
1110 if (!auart_dma_enabled(s))
1111 mxs_auart_rx_chars(s);
1112 istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS);
1113 }
1114
1115 if (istat & AUART_INTR_TXIS) {
1116 mxs_auart_tx_chars(s);
1117 istat &= ~AUART_INTR_TXIS;
1118 }
1119
1120 return IRQ_HANDLED;
1121}
1122
1123static void mxs_auart_reset_deassert(struct mxs_auart_port *s)
1124{
1125 int i;
1126 unsigned int reg;
1127
1128 mxs_clr(AUART_CTRL0_SFTRST, uap: s, reg: REG_CTRL0);
1129
1130 for (i = 0; i < 10000; i++) {
1131 reg = mxs_read(uap: s, reg: REG_CTRL0);
1132 if (!(reg & AUART_CTRL0_SFTRST))
1133 break;
1134 udelay(3);
1135 }
1136 mxs_clr(AUART_CTRL0_CLKGATE, uap: s, reg: REG_CTRL0);
1137}
1138
1139static void mxs_auart_reset_assert(struct mxs_auart_port *s)
1140{
1141 int i;
1142 u32 reg;
1143
1144 reg = mxs_read(uap: s, reg: REG_CTRL0);
1145 /* if already in reset state, keep it untouched */
1146 if (reg & AUART_CTRL0_SFTRST)
1147 return;
1148
1149 mxs_clr(AUART_CTRL0_CLKGATE, uap: s, reg: REG_CTRL0);
1150 mxs_set(AUART_CTRL0_SFTRST, uap: s, reg: REG_CTRL0);
1151
1152 for (i = 0; i < 1000; i++) {
1153 reg = mxs_read(uap: s, reg: REG_CTRL0);
1154 /* reset is finished when the clock is gated */
1155 if (reg & AUART_CTRL0_CLKGATE)
1156 return;
1157 udelay(10);
1158 }
1159
1160 dev_err(s->dev, "Failed to reset the unit.");
1161}
1162
1163static int mxs_auart_startup(struct uart_port *u)
1164{
1165 int ret;
1166 struct mxs_auart_port *s = to_auart_port(u);
1167
1168 ret = clk_prepare_enable(clk: s->clk);
1169 if (ret)
1170 return ret;
1171
1172 if (uart_console(u)) {
1173 mxs_clr(AUART_CTRL0_CLKGATE, uap: s, reg: REG_CTRL0);
1174 } else {
1175 /* reset the unit to a well known state */
1176 mxs_auart_reset_assert(s);
1177 mxs_auart_reset_deassert(s);
1178 }
1179
1180 mxs_set(AUART_CTRL2_UARTEN, uap: s, reg: REG_CTRL2);
1181
1182 mxs_write(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
1183 uap: s, reg: REG_INTR);
1184
1185 /* Reset FIFO size (it could have changed if DMA was enabled) */
1186 u->fifosize = MXS_AUART_FIFO_SIZE;
1187
1188 /*
1189 * Enable fifo so all four bytes of a DMA word are written to
1190 * output (otherwise, only the LSB is written, ie. 1 in 4 bytes)
1191 */
1192 mxs_set(AUART_LINECTRL_FEN, uap: s, reg: REG_LINECTRL);
1193
1194 /* get initial status of modem lines */
1195 mctrl_gpio_get(gpios: s->gpios, mctrl: &s->mctrl_prev);
1196
1197 s->ms_irq_enabled = false;
1198 return 0;
1199}
1200
1201static void mxs_auart_shutdown(struct uart_port *u)
1202{
1203 struct mxs_auart_port *s = to_auart_port(u);
1204
1205 mxs_auart_disable_ms(port: u);
1206
1207 if (auart_dma_enabled(s))
1208 mxs_auart_dma_exit(s);
1209
1210 if (uart_console(u)) {
1211 mxs_clr(AUART_CTRL2_UARTEN, uap: s, reg: REG_CTRL2);
1212
1213 mxs_clr(AUART_INTR_RXIEN | AUART_INTR_RTIEN |
1214 AUART_INTR_CTSMIEN, uap: s, reg: REG_INTR);
1215 mxs_set(AUART_CTRL0_CLKGATE, uap: s, reg: REG_CTRL0);
1216 } else {
1217 mxs_auart_reset_assert(s);
1218 }
1219
1220 clk_disable_unprepare(clk: s->clk);
1221}
1222
1223static unsigned int mxs_auart_tx_empty(struct uart_port *u)
1224{
1225 struct mxs_auart_port *s = to_auart_port(u);
1226
1227 if ((mxs_read(uap: s, reg: REG_STAT) &
1228 (AUART_STAT_TXFE | AUART_STAT_BUSY)) == AUART_STAT_TXFE)
1229 return TIOCSER_TEMT;
1230
1231 return 0;
1232}
1233
1234static void mxs_auart_start_tx(struct uart_port *u)
1235{
1236 struct mxs_auart_port *s = to_auart_port(u);
1237
1238 /* enable transmitter */
1239 mxs_set(AUART_CTRL2_TXE, uap: s, reg: REG_CTRL2);
1240
1241 mxs_auart_tx_chars(s);
1242}
1243
1244static void mxs_auart_stop_tx(struct uart_port *u)
1245{
1246 struct mxs_auart_port *s = to_auart_port(u);
1247
1248 mxs_clr(AUART_CTRL2_TXE, uap: s, reg: REG_CTRL2);
1249}
1250
1251static void mxs_auart_stop_rx(struct uart_port *u)
1252{
1253 struct mxs_auart_port *s = to_auart_port(u);
1254
1255 mxs_clr(AUART_CTRL2_RXE, uap: s, reg: REG_CTRL2);
1256}
1257
1258static void mxs_auart_break_ctl(struct uart_port *u, int ctl)
1259{
1260 struct mxs_auart_port *s = to_auart_port(u);
1261
1262 if (ctl)
1263 mxs_set(AUART_LINECTRL_BRK, uap: s, reg: REG_LINECTRL);
1264 else
1265 mxs_clr(AUART_LINECTRL_BRK, uap: s, reg: REG_LINECTRL);
1266}
1267
1268static const struct uart_ops mxs_auart_ops = {
1269 .tx_empty = mxs_auart_tx_empty,
1270 .start_tx = mxs_auart_start_tx,
1271 .stop_tx = mxs_auart_stop_tx,
1272 .stop_rx = mxs_auart_stop_rx,
1273 .enable_ms = mxs_auart_enable_ms,
1274 .break_ctl = mxs_auart_break_ctl,
1275 .set_mctrl = mxs_auart_set_mctrl,
1276 .get_mctrl = mxs_auart_get_mctrl,
1277 .startup = mxs_auart_startup,
1278 .shutdown = mxs_auart_shutdown,
1279 .set_termios = mxs_auart_settermios,
1280 .set_ldisc = mxs_auart_set_ldisc,
1281 .type = mxs_auart_type,
1282 .release_port = mxs_auart_release_port,
1283 .request_port = mxs_auart_request_port,
1284 .config_port = mxs_auart_config_port,
1285 .verify_port = mxs_auart_verify_port,
1286};
1287
1288static struct mxs_auart_port *auart_port[MXS_AUART_PORTS];
1289
1290#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
1291static void mxs_auart_console_putchar(struct uart_port *port, unsigned char ch)
1292{
1293 struct mxs_auart_port *s = to_auart_port(port);
1294 unsigned int to = 1000;
1295
1296 while (mxs_read(uap: s, reg: REG_STAT) & AUART_STAT_TXFF) {
1297 if (!to--)
1298 break;
1299 udelay(1);
1300 }
1301
1302 mxs_write(val: ch, uap: s, reg: REG_DATA);
1303}
1304
1305static void
1306auart_console_write(struct console *co, const char *str, unsigned int count)
1307{
1308 struct mxs_auart_port *s;
1309 struct uart_port *port;
1310 unsigned int old_ctrl0, old_ctrl2;
1311 unsigned int to = 20000;
1312
1313 if (co->index >= MXS_AUART_PORTS || co->index < 0)
1314 return;
1315
1316 s = auart_port[co->index];
1317 port = &s->port;
1318
1319 clk_enable(clk: s->clk);
1320
1321 /* First save the CR then disable the interrupts */
1322 old_ctrl2 = mxs_read(uap: s, reg: REG_CTRL2);
1323 old_ctrl0 = mxs_read(uap: s, reg: REG_CTRL0);
1324
1325 mxs_clr(AUART_CTRL0_CLKGATE, uap: s, reg: REG_CTRL0);
1326 mxs_set(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE, uap: s, reg: REG_CTRL2);
1327
1328 uart_console_write(port, s: str, count, putchar: mxs_auart_console_putchar);
1329
1330 /* Finally, wait for transmitter to become empty ... */
1331 while (mxs_read(uap: s, reg: REG_STAT) & AUART_STAT_BUSY) {
1332 udelay(1);
1333 if (!to--)
1334 break;
1335 }
1336
1337 /*
1338 * ... and restore the TCR if we waited long enough for the transmitter
1339 * to be idle. This might keep the transmitter enabled although it is
1340 * unused, but that is better than to disable it while it is still
1341 * transmitting.
1342 */
1343 if (!(mxs_read(uap: s, reg: REG_STAT) & AUART_STAT_BUSY)) {
1344 mxs_write(val: old_ctrl0, uap: s, reg: REG_CTRL0);
1345 mxs_write(val: old_ctrl2, uap: s, reg: REG_CTRL2);
1346 }
1347
1348 clk_disable(clk: s->clk);
1349}
1350
1351static void __init
1352auart_console_get_options(struct mxs_auart_port *s, int *baud,
1353 int *parity, int *bits)
1354{
1355 struct uart_port *port = &s->port;
1356 unsigned int lcr_h, quot;
1357
1358 if (!(mxs_read(uap: s, reg: REG_CTRL2) & AUART_CTRL2_UARTEN))
1359 return;
1360
1361 lcr_h = mxs_read(uap: s, reg: REG_LINECTRL);
1362
1363 *parity = 'n';
1364 if (lcr_h & AUART_LINECTRL_PEN) {
1365 if (lcr_h & AUART_LINECTRL_EPS)
1366 *parity = 'e';
1367 else
1368 *parity = 'o';
1369 }
1370
1371 if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(7))
1372 *bits = 7;
1373 else
1374 *bits = 8;
1375
1376 quot = ((mxs_read(uap: s, reg: REG_LINECTRL) & AUART_LINECTRL_BAUD_DIVINT_MASK))
1377 >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6);
1378 quot |= ((mxs_read(uap: s, reg: REG_LINECTRL) & AUART_LINECTRL_BAUD_DIVFRAC_MASK))
1379 >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT;
1380 if (quot == 0)
1381 quot = 1;
1382
1383 *baud = (port->uartclk << 2) / quot;
1384}
1385
1386static int __init
1387auart_console_setup(struct console *co, char *options)
1388{
1389 struct mxs_auart_port *s;
1390 int baud = 9600;
1391 int bits = 8;
1392 int parity = 'n';
1393 int flow = 'n';
1394 int ret;
1395
1396 /*
1397 * Check whether an invalid uart number has been specified, and
1398 * if so, search for the first available port that does have
1399 * console support.
1400 */
1401 if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port))
1402 co->index = 0;
1403 s = auart_port[co->index];
1404 if (!s)
1405 return -ENODEV;
1406
1407 ret = clk_prepare_enable(clk: s->clk);
1408 if (ret)
1409 return ret;
1410
1411 if (options)
1412 uart_parse_options(options, baud: &baud, parity: &parity, bits: &bits, flow: &flow);
1413 else
1414 auart_console_get_options(s, baud: &baud, parity: &parity, bits: &bits);
1415
1416 ret = uart_set_options(port: &s->port, co, baud, parity, bits, flow);
1417
1418 clk_disable_unprepare(clk: s->clk);
1419
1420 return ret;
1421}
1422
1423static struct console auart_console = {
1424 .name = "ttyAPP",
1425 .write = auart_console_write,
1426 .device = uart_console_device,
1427 .setup = auart_console_setup,
1428 .flags = CON_PRINTBUFFER,
1429 .index = -1,
1430 .data = &auart_driver,
1431};
1432#endif
1433
1434static struct uart_driver auart_driver = {
1435 .owner = THIS_MODULE,
1436 .driver_name = "ttyAPP",
1437 .dev_name = "ttyAPP",
1438 .major = 0,
1439 .minor = 0,
1440 .nr = MXS_AUART_PORTS,
1441#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
1442 .cons = &auart_console,
1443#endif
1444};
1445
1446static void mxs_init_regs(struct mxs_auart_port *s)
1447{
1448 if (is_asm9260_auart(s))
1449 s->vendor = &vendor_alphascale_asm9260;
1450 else
1451 s->vendor = &vendor_freescale_stmp37xx;
1452}
1453
1454static int mxs_get_clks(struct mxs_auart_port *s,
1455 struct platform_device *pdev)
1456{
1457 int err;
1458
1459 if (!is_asm9260_auart(s)) {
1460 s->clk = devm_clk_get(dev: &pdev->dev, NULL);
1461 return PTR_ERR_OR_ZERO(ptr: s->clk);
1462 }
1463
1464 s->clk = devm_clk_get(dev: s->dev, id: "mod");
1465 if (IS_ERR(ptr: s->clk)) {
1466 dev_err(s->dev, "Failed to get \"mod\" clk\n");
1467 return PTR_ERR(ptr: s->clk);
1468 }
1469
1470 s->clk_ahb = devm_clk_get(dev: s->dev, id: "ahb");
1471 if (IS_ERR(ptr: s->clk_ahb)) {
1472 dev_err(s->dev, "Failed to get \"ahb\" clk\n");
1473 return PTR_ERR(ptr: s->clk_ahb);
1474 }
1475
1476 err = clk_prepare_enable(clk: s->clk_ahb);
1477 if (err) {
1478 dev_err(s->dev, "Failed to enable ahb_clk!\n");
1479 return err;
1480 }
1481
1482 err = clk_set_rate(clk: s->clk, rate: clk_get_rate(clk: s->clk_ahb));
1483 if (err) {
1484 dev_err(s->dev, "Failed to set rate!\n");
1485 goto disable_clk_ahb;
1486 }
1487
1488 err = clk_prepare_enable(clk: s->clk);
1489 if (err) {
1490 dev_err(s->dev, "Failed to enable clk!\n");
1491 goto disable_clk_ahb;
1492 }
1493
1494 return 0;
1495
1496disable_clk_ahb:
1497 clk_disable_unprepare(clk: s->clk_ahb);
1498 return err;
1499}
1500
1501static int mxs_auart_init_gpios(struct mxs_auart_port *s, struct device *dev)
1502{
1503 enum mctrl_gpio_idx i;
1504 struct gpio_desc *gpiod;
1505
1506 s->gpios = mctrl_gpio_init_noauto(dev, idx: 0);
1507 if (IS_ERR(ptr: s->gpios))
1508 return PTR_ERR(ptr: s->gpios);
1509
1510 /* Block (enabled before) DMA option if RTS or CTS is GPIO line */
1511 if (!RTS_AT_AUART() || !CTS_AT_AUART()) {
1512 if (test_bit(MXS_AUART_RTSCTS, &s->flags))
1513 dev_warn(dev,
1514 "DMA and flow control via gpio may cause some problems. DMA disabled!\n");
1515 clear_bit(MXS_AUART_RTSCTS, addr: &s->flags);
1516 }
1517
1518 for (i = 0; i < UART_GPIO_MAX; i++) {
1519 gpiod = mctrl_gpio_to_gpiod(gpios: s->gpios, gidx: i);
1520 if (gpiod && (gpiod_get_direction(desc: gpiod) == 1))
1521 s->gpio_irq[i] = gpiod_to_irq(desc: gpiod);
1522 else
1523 s->gpio_irq[i] = -EINVAL;
1524 }
1525
1526 return 0;
1527}
1528
1529static void mxs_auart_free_gpio_irq(struct mxs_auart_port *s)
1530{
1531 enum mctrl_gpio_idx i;
1532
1533 for (i = 0; i < UART_GPIO_MAX; i++)
1534 if (s->gpio_irq[i] >= 0)
1535 free_irq(s->gpio_irq[i], s);
1536}
1537
1538static int mxs_auart_request_gpio_irq(struct mxs_auart_port *s)
1539{
1540 int *irq = s->gpio_irq;
1541 enum mctrl_gpio_idx i;
1542 int err = 0;
1543
1544 for (i = 0; (i < UART_GPIO_MAX) && !err; i++) {
1545 if (irq[i] < 0)
1546 continue;
1547
1548 irq_set_status_flags(irq: irq[i], set: IRQ_NOAUTOEN);
1549 err = request_irq(irq: irq[i], handler: mxs_auart_irq_handle,
1550 flags: IRQ_TYPE_EDGE_BOTH, name: dev_name(dev: s->dev), dev: s);
1551 if (err)
1552 dev_err(s->dev, "%s - Can't get %d irq\n",
1553 __func__, irq[i]);
1554 }
1555
1556 /*
1557 * If something went wrong, rollback.
1558 * Be careful: i may be unsigned.
1559 */
1560 while (err && (i-- > 0))
1561 if (irq[i] >= 0)
1562 free_irq(irq[i], s);
1563
1564 return err;
1565}
1566
1567static int mxs_auart_probe(struct platform_device *pdev)
1568{
1569 struct device_node *np = pdev->dev.of_node;
1570 struct mxs_auart_port *s;
1571 u32 version;
1572 int ret, irq;
1573 struct resource *r;
1574
1575 s = devm_kzalloc(dev: &pdev->dev, size: sizeof(*s), GFP_KERNEL);
1576 if (!s)
1577 return -ENOMEM;
1578
1579 s->port.dev = &pdev->dev;
1580 s->dev = &pdev->dev;
1581
1582 ret = of_alias_get_id(np, stem: "serial");
1583 if (ret < 0) {
1584 dev_err(&pdev->dev, "failed to get alias id: %d\n", ret);
1585 return ret;
1586 }
1587 s->port.line = ret;
1588
1589 if (of_property_read_bool(np, propname: "uart-has-rtscts") ||
1590 of_property_read_bool(np, propname: "fsl,uart-has-rtscts") /* deprecated */)
1591 set_bit(MXS_AUART_RTSCTS, addr: &s->flags);
1592
1593 if (s->port.line >= ARRAY_SIZE(auart_port)) {
1594 dev_err(&pdev->dev, "serial%d out of range\n", s->port.line);
1595 return -EINVAL;
1596 }
1597
1598 s->devtype = (enum mxs_auart_type)of_device_get_match_data(dev: &pdev->dev);
1599
1600 ret = mxs_get_clks(s, pdev);
1601 if (ret)
1602 return ret;
1603
1604 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1605 if (!r) {
1606 ret = -ENXIO;
1607 goto out_disable_clks;
1608 }
1609
1610 s->port.mapbase = r->start;
1611 s->port.membase = ioremap(offset: r->start, size: resource_size(res: r));
1612 if (!s->port.membase) {
1613 ret = -ENOMEM;
1614 goto out_disable_clks;
1615 }
1616 s->port.ops = &mxs_auart_ops;
1617 s->port.iotype = UPIO_MEM;
1618 s->port.fifosize = MXS_AUART_FIFO_SIZE;
1619 s->port.uartclk = clk_get_rate(clk: s->clk);
1620 s->port.type = PORT_IMX;
1621 s->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_MXS_AUART_CONSOLE);
1622
1623 mxs_init_regs(s);
1624
1625 s->mctrl_prev = 0;
1626
1627 irq = platform_get_irq(pdev, 0);
1628 if (irq < 0) {
1629 ret = irq;
1630 goto out_iounmap;
1631 }
1632
1633 s->port.irq = irq;
1634 ret = devm_request_irq(dev: &pdev->dev, irq, handler: mxs_auart_irq_handle, irqflags: 0,
1635 devname: dev_name(dev: &pdev->dev), dev_id: s);
1636 if (ret)
1637 goto out_iounmap;
1638
1639 platform_set_drvdata(pdev, data: s);
1640
1641 ret = mxs_auart_init_gpios(s, dev: &pdev->dev);
1642 if (ret) {
1643 dev_err(&pdev->dev, "Failed to initialize GPIOs.\n");
1644 goto out_iounmap;
1645 }
1646
1647 /*
1648 * Get the GPIO lines IRQ
1649 */
1650 ret = mxs_auart_request_gpio_irq(s);
1651 if (ret)
1652 goto out_iounmap;
1653
1654 auart_port[s->port.line] = s;
1655
1656 mxs_auart_reset_deassert(s);
1657
1658 ret = uart_add_one_port(reg: &auart_driver, port: &s->port);
1659 if (ret)
1660 goto out_free_qpio_irq;
1661
1662 /* ASM9260 don't have version reg */
1663 if (is_asm9260_auart(s)) {
1664 dev_info(&pdev->dev, "Found APPUART ASM9260\n");
1665 } else {
1666 version = mxs_read(uap: s, reg: REG_VERSION);
1667 dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n",
1668 (version >> 24) & 0xff,
1669 (version >> 16) & 0xff, version & 0xffff);
1670 }
1671
1672 return 0;
1673
1674out_free_qpio_irq:
1675 mxs_auart_free_gpio_irq(s);
1676 auart_port[pdev->id] = NULL;
1677
1678out_iounmap:
1679 iounmap(addr: s->port.membase);
1680
1681out_disable_clks:
1682 if (is_asm9260_auart(s)) {
1683 clk_disable_unprepare(clk: s->clk);
1684 clk_disable_unprepare(clk: s->clk_ahb);
1685 }
1686 return ret;
1687}
1688
1689static int mxs_auart_remove(struct platform_device *pdev)
1690{
1691 struct mxs_auart_port *s = platform_get_drvdata(pdev);
1692
1693 uart_remove_one_port(reg: &auart_driver, port: &s->port);
1694 auart_port[pdev->id] = NULL;
1695 mxs_auart_free_gpio_irq(s);
1696 iounmap(addr: s->port.membase);
1697 if (is_asm9260_auart(s)) {
1698 clk_disable_unprepare(clk: s->clk);
1699 clk_disable_unprepare(clk: s->clk_ahb);
1700 }
1701
1702 return 0;
1703}
1704
1705static struct platform_driver mxs_auart_driver = {
1706 .probe = mxs_auart_probe,
1707 .remove = mxs_auart_remove,
1708 .driver = {
1709 .name = "mxs-auart",
1710 .of_match_table = mxs_auart_dt_ids,
1711 },
1712};
1713
1714static int __init mxs_auart_init(void)
1715{
1716 int r;
1717
1718 r = uart_register_driver(uart: &auart_driver);
1719 if (r)
1720 goto out;
1721
1722 r = platform_driver_register(&mxs_auart_driver);
1723 if (r)
1724 goto out_err;
1725
1726 return 0;
1727out_err:
1728 uart_unregister_driver(uart: &auart_driver);
1729out:
1730 return r;
1731}
1732
1733static void __exit mxs_auart_exit(void)
1734{
1735 platform_driver_unregister(&mxs_auart_driver);
1736 uart_unregister_driver(uart: &auart_driver);
1737}
1738
1739module_init(mxs_auart_init);
1740module_exit(mxs_auart_exit);
1741MODULE_LICENSE("GPL");
1742MODULE_DESCRIPTION("Freescale MXS application uart driver");
1743MODULE_ALIAS("platform:mxs-auart");
1744

source code of linux/drivers/tty/serial/mxs-auart.c