1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* |
3 | * Driver for PowerMac Z85c30 based ESCC cell found in the |
4 | * "macio" ASICs of various PowerMac models |
5 | * |
6 | * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org) |
7 | * |
8 | * Derived from drivers/macintosh/macserial.c by Paul Mackerras |
9 | * and drivers/serial/sunzilog.c by David S. Miller |
10 | * |
11 | * Hrm... actually, I ripped most of sunzilog (Thanks David !) and |
12 | * adapted special tweaks needed for us. I don't think it's worth |
13 | * merging back those though. The DMA code still has to get in |
14 | * and once done, I expect that driver to remain fairly stable in |
15 | * the long term, unless we change the driver model again... |
16 | * |
17 | * 2004-08-06 Harald Welte <laforge@gnumonks.org> |
18 | * - Enable BREAK interrupt |
19 | * - Add support for sysreq |
20 | * |
21 | * TODO: - Add DMA support |
22 | * - Defer port shutdown to a few seconds after close |
23 | * - maybe put something right into uap->clk_divisor |
24 | */ |
25 | |
26 | #undef DEBUG |
27 | #undef USE_CTRL_O_SYSRQ |
28 | |
29 | #include <linux/module.h> |
30 | #include <linux/tty.h> |
31 | |
32 | #include <linux/tty_flip.h> |
33 | #include <linux/major.h> |
34 | #include <linux/string.h> |
35 | #include <linux/fcntl.h> |
36 | #include <linux/mm.h> |
37 | #include <linux/kernel.h> |
38 | #include <linux/delay.h> |
39 | #include <linux/init.h> |
40 | #include <linux/console.h> |
41 | #include <linux/adb.h> |
42 | #include <linux/pmu.h> |
43 | #include <linux/bitops.h> |
44 | #include <linux/sysrq.h> |
45 | #include <linux/mutex.h> |
46 | #include <linux/of_address.h> |
47 | #include <linux/of_irq.h> |
48 | #include <asm/sections.h> |
49 | #include <linux/io.h> |
50 | #include <asm/irq.h> |
51 | |
52 | #ifdef CONFIG_PPC_PMAC |
53 | #include <asm/machdep.h> |
54 | #include <asm/pmac_feature.h> |
55 | #include <asm/macio.h> |
56 | #else |
57 | #include <linux/platform_device.h> |
58 | #define of_machine_is_compatible(x) (0) |
59 | #endif |
60 | |
61 | #include <linux/serial.h> |
62 | #include <linux/serial_core.h> |
63 | |
64 | #include "pmac_zilog.h" |
65 | |
66 | MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>" ); |
67 | MODULE_DESCRIPTION("Driver for the Mac and PowerMac serial ports." ); |
68 | MODULE_LICENSE("GPL" ); |
69 | |
70 | #ifdef CONFIG_SERIAL_PMACZILOG_TTYS |
71 | #define PMACZILOG_MAJOR TTY_MAJOR |
72 | #define PMACZILOG_MINOR 64 |
73 | #define PMACZILOG_NAME "ttyS" |
74 | #else |
75 | #define PMACZILOG_MAJOR 204 |
76 | #define PMACZILOG_MINOR 192 |
77 | #define PMACZILOG_NAME "ttyPZ" |
78 | #endif |
79 | |
80 | #define pmz_debug(fmt, arg...) pr_debug("ttyPZ%d: " fmt, uap->port.line, ## arg) |
81 | #define pmz_error(fmt, arg...) pr_err("ttyPZ%d: " fmt, uap->port.line, ## arg) |
82 | #define pmz_info(fmt, arg...) pr_info("ttyPZ%d: " fmt, uap->port.line, ## arg) |
83 | |
84 | /* |
85 | * For the sake of early serial console, we can do a pre-probe |
86 | * (optional) of the ports at rather early boot time. |
87 | */ |
88 | static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS]; |
89 | static int pmz_ports_count; |
90 | |
91 | static struct uart_driver pmz_uart_reg = { |
92 | .owner = THIS_MODULE, |
93 | .driver_name = PMACZILOG_NAME, |
94 | .dev_name = PMACZILOG_NAME, |
95 | .major = PMACZILOG_MAJOR, |
96 | .minor = PMACZILOG_MINOR, |
97 | }; |
98 | |
99 | |
100 | /* |
101 | * Load all registers to reprogram the port |
102 | * This function must only be called when the TX is not busy. The UART |
103 | * port lock must be held and local interrupts disabled. |
104 | */ |
105 | static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs) |
106 | { |
107 | int i; |
108 | |
109 | /* Let pending transmits finish. */ |
110 | for (i = 0; i < 1000; i++) { |
111 | unsigned char stat = read_zsreg(port: uap, R1); |
112 | if (stat & ALL_SNT) |
113 | break; |
114 | udelay(100); |
115 | } |
116 | |
117 | ZS_CLEARERR(uap); |
118 | zssync(port: uap); |
119 | ZS_CLEARFIFO(uap); |
120 | zssync(port: uap); |
121 | ZS_CLEARERR(uap); |
122 | |
123 | /* Disable all interrupts. */ |
124 | write_zsreg(port: uap, R1, |
125 | value: regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB)); |
126 | |
127 | /* Set parity, sync config, stop bits, and clock divisor. */ |
128 | write_zsreg(port: uap, R4, value: regs[R4]); |
129 | |
130 | /* Set misc. TX/RX control bits. */ |
131 | write_zsreg(port: uap, R10, value: regs[R10]); |
132 | |
133 | /* Set TX/RX controls sans the enable bits. */ |
134 | write_zsreg(port: uap, R3, value: regs[R3] & ~RxENABLE); |
135 | write_zsreg(port: uap, R5, value: regs[R5] & ~TxENABLE); |
136 | |
137 | /* now set R7 "prime" on ESCC */ |
138 | write_zsreg(port: uap, R15, value: regs[R15] | EN85C30); |
139 | write_zsreg(port: uap, R7, value: regs[R7P]); |
140 | |
141 | /* make sure we use R7 "non-prime" on ESCC */ |
142 | write_zsreg(port: uap, R15, value: regs[R15] & ~EN85C30); |
143 | |
144 | /* Synchronous mode config. */ |
145 | write_zsreg(port: uap, R6, value: regs[R6]); |
146 | write_zsreg(port: uap, R7, value: regs[R7]); |
147 | |
148 | /* Disable baud generator. */ |
149 | write_zsreg(port: uap, R14, value: regs[R14] & ~BRENAB); |
150 | |
151 | /* Clock mode control. */ |
152 | write_zsreg(port: uap, R11, value: regs[R11]); |
153 | |
154 | /* Lower and upper byte of baud rate generator divisor. */ |
155 | write_zsreg(port: uap, R12, value: regs[R12]); |
156 | write_zsreg(port: uap, R13, value: regs[R13]); |
157 | |
158 | /* Now rewrite R14, with BRENAB (if set). */ |
159 | write_zsreg(port: uap, R14, value: regs[R14]); |
160 | |
161 | /* Reset external status interrupts. */ |
162 | write_zsreg(port: uap, R0, RES_EXT_INT); |
163 | write_zsreg(port: uap, R0, RES_EXT_INT); |
164 | |
165 | /* Rewrite R3/R5, this time without enables masked. */ |
166 | write_zsreg(port: uap, R3, value: regs[R3]); |
167 | write_zsreg(port: uap, R5, value: regs[R5]); |
168 | |
169 | /* Rewrite R1, this time without IRQ enabled masked. */ |
170 | write_zsreg(port: uap, R1, value: regs[R1]); |
171 | |
172 | /* Enable interrupts */ |
173 | write_zsreg(port: uap, R9, value: regs[R9]); |
174 | } |
175 | |
176 | /* |
177 | * We do like sunzilog to avoid disrupting pending Tx |
178 | * Reprogram the Zilog channel HW registers with the copies found in the |
179 | * software state struct. If the transmitter is busy, we defer this update |
180 | * until the next TX complete interrupt. Else, we do it right now. |
181 | * |
182 | * The UART port lock must be held and local interrupts disabled. |
183 | */ |
184 | static void pmz_maybe_update_regs(struct uart_pmac_port *uap) |
185 | { |
186 | if (!ZS_REGS_HELD(uap)) { |
187 | if (ZS_TX_ACTIVE(uap)) { |
188 | uap->flags |= PMACZILOG_FLAG_REGS_HELD; |
189 | } else { |
190 | pmz_debug("pmz: maybe_update_regs: updating\n" ); |
191 | pmz_load_zsregs(uap, regs: uap->curregs); |
192 | } |
193 | } |
194 | } |
195 | |
196 | static void pmz_interrupt_control(struct uart_pmac_port *uap, int enable) |
197 | { |
198 | if (enable) { |
199 | uap->curregs[1] |= INT_ALL_Rx | TxINT_ENAB; |
200 | if (!ZS_IS_EXTCLK(uap)) |
201 | uap->curregs[1] |= EXT_INT_ENAB; |
202 | } else { |
203 | uap->curregs[1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); |
204 | } |
205 | write_zsreg(port: uap, R1, value: uap->curregs[1]); |
206 | } |
207 | |
208 | static bool pmz_receive_chars(struct uart_pmac_port *uap) |
209 | __must_hold(&uap->port.lock) |
210 | { |
211 | struct tty_port *port; |
212 | unsigned char ch, r1, drop, flag; |
213 | int loops = 0; |
214 | |
215 | /* Sanity check, make sure the old bug is no longer happening */ |
216 | if (uap->port.state == NULL) { |
217 | WARN_ON(1); |
218 | (void)read_zsdata(port: uap); |
219 | return false; |
220 | } |
221 | port = &uap->port.state->port; |
222 | |
223 | while (1) { |
224 | drop = 0; |
225 | |
226 | r1 = read_zsreg(port: uap, R1); |
227 | ch = read_zsdata(port: uap); |
228 | |
229 | if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) { |
230 | write_zsreg(port: uap, R0, ERR_RES); |
231 | zssync(port: uap); |
232 | } |
233 | |
234 | ch &= uap->parity_mask; |
235 | if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) { |
236 | uap->flags &= ~PMACZILOG_FLAG_BREAK; |
237 | } |
238 | |
239 | #if defined(CONFIG_MAGIC_SYSRQ) && defined(CONFIG_SERIAL_CORE_CONSOLE) |
240 | #ifdef USE_CTRL_O_SYSRQ |
241 | /* Handle the SysRq ^O Hack */ |
242 | if (ch == '\x0f') { |
243 | uap->port.sysrq = jiffies + HZ*5; |
244 | goto next_char; |
245 | } |
246 | #endif /* USE_CTRL_O_SYSRQ */ |
247 | if (uap->port.sysrq) { |
248 | int swallow; |
249 | uart_port_unlock(up: &uap->port); |
250 | swallow = uart_handle_sysrq_char(port: &uap->port, ch); |
251 | uart_port_lock(up: &uap->port); |
252 | if (swallow) |
253 | goto next_char; |
254 | } |
255 | #endif /* CONFIG_MAGIC_SYSRQ && CONFIG_SERIAL_CORE_CONSOLE */ |
256 | |
257 | /* A real serial line, record the character and status. */ |
258 | if (drop) |
259 | goto next_char; |
260 | |
261 | flag = TTY_NORMAL; |
262 | uap->port.icount.rx++; |
263 | |
264 | if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | BRK_ABRT)) { |
265 | if (r1 & BRK_ABRT) { |
266 | pmz_debug("pmz: got break !\n" ); |
267 | r1 &= ~(PAR_ERR | CRC_ERR); |
268 | uap->port.icount.brk++; |
269 | if (uart_handle_break(port: &uap->port)) |
270 | goto next_char; |
271 | } |
272 | else if (r1 & PAR_ERR) |
273 | uap->port.icount.parity++; |
274 | else if (r1 & CRC_ERR) |
275 | uap->port.icount.frame++; |
276 | if (r1 & Rx_OVR) |
277 | uap->port.icount.overrun++; |
278 | r1 &= uap->port.read_status_mask; |
279 | if (r1 & BRK_ABRT) |
280 | flag = TTY_BREAK; |
281 | else if (r1 & PAR_ERR) |
282 | flag = TTY_PARITY; |
283 | else if (r1 & CRC_ERR) |
284 | flag = TTY_FRAME; |
285 | } |
286 | |
287 | if (uap->port.ignore_status_mask == 0xff || |
288 | (r1 & uap->port.ignore_status_mask) == 0) { |
289 | tty_insert_flip_char(port, ch, flag); |
290 | } |
291 | if (r1 & Rx_OVR) |
292 | tty_insert_flip_char(port, ch: 0, TTY_OVERRUN); |
293 | next_char: |
294 | /* We can get stuck in an infinite loop getting char 0 when the |
295 | * line is in a wrong HW state, we break that here. |
296 | * When that happens, I disable the receive side of the driver. |
297 | * Note that what I've been experiencing is a real irq loop where |
298 | * I'm getting flooded regardless of the actual port speed. |
299 | * Something strange is going on with the HW |
300 | */ |
301 | if ((++loops) > 1000) |
302 | goto flood; |
303 | ch = read_zsreg(port: uap, R0); |
304 | if (!(ch & Rx_CH_AV)) |
305 | break; |
306 | } |
307 | |
308 | return true; |
309 | flood: |
310 | pmz_interrupt_control(uap, enable: 0); |
311 | pmz_error("pmz: rx irq flood !\n" ); |
312 | return true; |
313 | } |
314 | |
315 | static void pmz_status_handle(struct uart_pmac_port *uap) |
316 | { |
317 | unsigned char status; |
318 | |
319 | status = read_zsreg(port: uap, R0); |
320 | write_zsreg(port: uap, R0, RES_EXT_INT); |
321 | zssync(port: uap); |
322 | |
323 | if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) { |
324 | if (status & SYNC_HUNT) |
325 | uap->port.icount.dsr++; |
326 | |
327 | /* The Zilog just gives us an interrupt when DCD/CTS/etc. change. |
328 | * But it does not tell us which bit has changed, we have to keep |
329 | * track of this ourselves. |
330 | * The CTS input is inverted for some reason. -- paulus |
331 | */ |
332 | if ((status ^ uap->prev_status) & DCD) |
333 | uart_handle_dcd_change(uport: &uap->port, |
334 | active: (status & DCD)); |
335 | if ((status ^ uap->prev_status) & CTS) |
336 | uart_handle_cts_change(uport: &uap->port, |
337 | active: !(status & CTS)); |
338 | |
339 | wake_up_interruptible(&uap->port.state->port.delta_msr_wait); |
340 | } |
341 | |
342 | if (status & BRK_ABRT) |
343 | uap->flags |= PMACZILOG_FLAG_BREAK; |
344 | |
345 | uap->prev_status = status; |
346 | } |
347 | |
348 | static void pmz_transmit_chars(struct uart_pmac_port *uap) |
349 | { |
350 | struct circ_buf *xmit; |
351 | |
352 | if (ZS_IS_CONS(uap)) { |
353 | unsigned char status = read_zsreg(port: uap, R0); |
354 | |
355 | /* TX still busy? Just wait for the next TX done interrupt. |
356 | * |
357 | * It can occur because of how we do serial console writes. It would |
358 | * be nice to transmit console writes just like we normally would for |
359 | * a TTY line. (ie. buffered and TX interrupt driven). That is not |
360 | * easy because console writes cannot sleep. One solution might be |
361 | * to poll on enough port->xmit space becoming free. -DaveM |
362 | */ |
363 | if (!(status & Tx_BUF_EMP)) |
364 | return; |
365 | } |
366 | |
367 | uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE; |
368 | |
369 | if (ZS_REGS_HELD(uap)) { |
370 | pmz_load_zsregs(uap, regs: uap->curregs); |
371 | uap->flags &= ~PMACZILOG_FLAG_REGS_HELD; |
372 | } |
373 | |
374 | if (ZS_TX_STOPPED(uap)) { |
375 | uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED; |
376 | goto ack_tx_int; |
377 | } |
378 | |
379 | /* Under some circumstances, we see interrupts reported for |
380 | * a closed channel. The interrupt mask in R1 is clear, but |
381 | * R3 still signals the interrupts and we see them when taking |
382 | * an interrupt for the other channel (this could be a qemu |
383 | * bug but since the ESCC doc doesn't specify precsiely whether |
384 | * R3 interrup status bits are masked by R1 interrupt enable |
385 | * bits, better safe than sorry). --BenH. |
386 | */ |
387 | if (!ZS_IS_OPEN(uap)) |
388 | goto ack_tx_int; |
389 | |
390 | if (uap->port.x_char) { |
391 | uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; |
392 | write_zsdata(port: uap, data: uap->port.x_char); |
393 | zssync(port: uap); |
394 | uap->port.icount.tx++; |
395 | uap->port.x_char = 0; |
396 | return; |
397 | } |
398 | |
399 | if (uap->port.state == NULL) |
400 | goto ack_tx_int; |
401 | xmit = &uap->port.state->xmit; |
402 | if (uart_circ_empty(xmit)) { |
403 | uart_write_wakeup(port: &uap->port); |
404 | goto ack_tx_int; |
405 | } |
406 | if (uart_tx_stopped(port: &uap->port)) |
407 | goto ack_tx_int; |
408 | |
409 | uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; |
410 | write_zsdata(port: uap, data: xmit->buf[xmit->tail]); |
411 | zssync(port: uap); |
412 | |
413 | uart_xmit_advance(up: &uap->port, chars: 1); |
414 | |
415 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
416 | uart_write_wakeup(port: &uap->port); |
417 | |
418 | return; |
419 | |
420 | ack_tx_int: |
421 | write_zsreg(port: uap, R0, RES_Tx_P); |
422 | zssync(port: uap); |
423 | } |
424 | |
425 | /* Hrm... we register that twice, fixme later.... */ |
426 | static irqreturn_t pmz_interrupt(int irq, void *dev_id) |
427 | { |
428 | struct uart_pmac_port *uap = dev_id; |
429 | struct uart_pmac_port *uap_a; |
430 | struct uart_pmac_port *uap_b; |
431 | int rc = IRQ_NONE; |
432 | bool push; |
433 | u8 r3; |
434 | |
435 | uap_a = pmz_get_port_A(uap); |
436 | uap_b = uap_a->mate; |
437 | |
438 | uart_port_lock(up: &uap_a->port); |
439 | r3 = read_zsreg(port: uap_a, R3); |
440 | |
441 | /* Channel A */ |
442 | push = false; |
443 | if (r3 & (CHAEXT | CHATxIP | CHARxIP)) { |
444 | if (!ZS_IS_OPEN(uap_a)) { |
445 | pmz_debug("ChanA interrupt while not open !\n" ); |
446 | goto skip_a; |
447 | } |
448 | write_zsreg(port: uap_a, R0, RES_H_IUS); |
449 | zssync(port: uap_a); |
450 | if (r3 & CHAEXT) |
451 | pmz_status_handle(uap: uap_a); |
452 | if (r3 & CHARxIP) |
453 | push = pmz_receive_chars(uap: uap_a); |
454 | if (r3 & CHATxIP) |
455 | pmz_transmit_chars(uap: uap_a); |
456 | rc = IRQ_HANDLED; |
457 | } |
458 | skip_a: |
459 | uart_port_unlock(up: &uap_a->port); |
460 | if (push) |
461 | tty_flip_buffer_push(port: &uap->port.state->port); |
462 | |
463 | if (!uap_b) |
464 | goto out; |
465 | |
466 | uart_port_lock(up: &uap_b->port); |
467 | push = false; |
468 | if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) { |
469 | if (!ZS_IS_OPEN(uap_b)) { |
470 | pmz_debug("ChanB interrupt while not open !\n" ); |
471 | goto skip_b; |
472 | } |
473 | write_zsreg(port: uap_b, R0, RES_H_IUS); |
474 | zssync(port: uap_b); |
475 | if (r3 & CHBEXT) |
476 | pmz_status_handle(uap: uap_b); |
477 | if (r3 & CHBRxIP) |
478 | push = pmz_receive_chars(uap: uap_b); |
479 | if (r3 & CHBTxIP) |
480 | pmz_transmit_chars(uap: uap_b); |
481 | rc = IRQ_HANDLED; |
482 | } |
483 | skip_b: |
484 | uart_port_unlock(up: &uap_b->port); |
485 | if (push) |
486 | tty_flip_buffer_push(port: &uap->port.state->port); |
487 | |
488 | out: |
489 | return rc; |
490 | } |
491 | |
492 | /* |
493 | * Peek the status register, lock not held by caller |
494 | */ |
495 | static inline u8 pmz_peek_status(struct uart_pmac_port *uap) |
496 | { |
497 | unsigned long flags; |
498 | u8 status; |
499 | |
500 | uart_port_lock_irqsave(up: &uap->port, flags: &flags); |
501 | status = read_zsreg(port: uap, R0); |
502 | uart_port_unlock_irqrestore(up: &uap->port, flags); |
503 | |
504 | return status; |
505 | } |
506 | |
507 | /* |
508 | * Check if transmitter is empty |
509 | * The port lock is not held. |
510 | */ |
511 | static unsigned int pmz_tx_empty(struct uart_port *port) |
512 | { |
513 | unsigned char status; |
514 | |
515 | status = pmz_peek_status(to_pmz(port)); |
516 | if (status & Tx_BUF_EMP) |
517 | return TIOCSER_TEMT; |
518 | return 0; |
519 | } |
520 | |
521 | /* |
522 | * Set Modem Control (RTS & DTR) bits |
523 | * The port lock is held and interrupts are disabled. |
524 | * Note: Shall we really filter out RTS on external ports or |
525 | * should that be dealt at higher level only ? |
526 | */ |
527 | static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl) |
528 | { |
529 | struct uart_pmac_port *uap = to_pmz(port); |
530 | unsigned char set_bits, clear_bits; |
531 | |
532 | /* Do nothing for irda for now... */ |
533 | if (ZS_IS_IRDA(uap)) |
534 | return; |
535 | /* We get called during boot with a port not up yet */ |
536 | if (!(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap))) |
537 | return; |
538 | |
539 | set_bits = clear_bits = 0; |
540 | |
541 | if (ZS_IS_INTMODEM(uap)) { |
542 | if (mctrl & TIOCM_RTS) |
543 | set_bits |= RTS; |
544 | else |
545 | clear_bits |= RTS; |
546 | } |
547 | if (mctrl & TIOCM_DTR) |
548 | set_bits |= DTR; |
549 | else |
550 | clear_bits |= DTR; |
551 | |
552 | /* NOTE: Not subject to 'transmitter active' rule. */ |
553 | uap->curregs[R5] |= set_bits; |
554 | uap->curregs[R5] &= ~clear_bits; |
555 | |
556 | write_zsreg(port: uap, R5, value: uap->curregs[R5]); |
557 | pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n" , |
558 | set_bits, clear_bits, uap->curregs[R5]); |
559 | zssync(port: uap); |
560 | } |
561 | |
562 | /* |
563 | * Get Modem Control bits (only the input ones, the core will |
564 | * or that with a cached value of the control ones) |
565 | * The port lock is held and interrupts are disabled. |
566 | */ |
567 | static unsigned int pmz_get_mctrl(struct uart_port *port) |
568 | { |
569 | struct uart_pmac_port *uap = to_pmz(port); |
570 | unsigned char status; |
571 | unsigned int ret; |
572 | |
573 | status = read_zsreg(port: uap, R0); |
574 | |
575 | ret = 0; |
576 | if (status & DCD) |
577 | ret |= TIOCM_CAR; |
578 | if (status & SYNC_HUNT) |
579 | ret |= TIOCM_DSR; |
580 | if (!(status & CTS)) |
581 | ret |= TIOCM_CTS; |
582 | |
583 | return ret; |
584 | } |
585 | |
586 | /* |
587 | * Stop TX side. Dealt like sunzilog at next Tx interrupt, |
588 | * though for DMA, we will have to do a bit more. |
589 | * The port lock is held and interrupts are disabled. |
590 | */ |
591 | static void pmz_stop_tx(struct uart_port *port) |
592 | { |
593 | to_pmz(port)->flags |= PMACZILOG_FLAG_TX_STOPPED; |
594 | } |
595 | |
596 | /* |
597 | * Kick the Tx side. |
598 | * The port lock is held and interrupts are disabled. |
599 | */ |
600 | static void pmz_start_tx(struct uart_port *port) |
601 | { |
602 | struct uart_pmac_port *uap = to_pmz(port); |
603 | unsigned char status; |
604 | |
605 | uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; |
606 | uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED; |
607 | |
608 | status = read_zsreg(port: uap, R0); |
609 | |
610 | /* TX busy? Just wait for the TX done interrupt. */ |
611 | if (!(status & Tx_BUF_EMP)) |
612 | return; |
613 | |
614 | /* Send the first character to jump-start the TX done |
615 | * IRQ sending engine. |
616 | */ |
617 | if (port->x_char) { |
618 | write_zsdata(port: uap, data: port->x_char); |
619 | zssync(port: uap); |
620 | port->icount.tx++; |
621 | port->x_char = 0; |
622 | } else { |
623 | struct circ_buf *xmit = &port->state->xmit; |
624 | |
625 | if (uart_circ_empty(xmit)) |
626 | return; |
627 | write_zsdata(port: uap, data: xmit->buf[xmit->tail]); |
628 | zssync(port: uap); |
629 | uart_xmit_advance(up: port, chars: 1); |
630 | |
631 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
632 | uart_write_wakeup(port: &uap->port); |
633 | } |
634 | } |
635 | |
636 | /* |
637 | * Stop Rx side, basically disable emitting of |
638 | * Rx interrupts on the port. We don't disable the rx |
639 | * side of the chip proper though |
640 | * The port lock is held. |
641 | */ |
642 | static void pmz_stop_rx(struct uart_port *port) |
643 | { |
644 | struct uart_pmac_port *uap = to_pmz(port); |
645 | |
646 | /* Disable all RX interrupts. */ |
647 | uap->curregs[R1] &= ~RxINT_MASK; |
648 | pmz_maybe_update_regs(uap); |
649 | } |
650 | |
651 | /* |
652 | * Enable modem status change interrupts |
653 | * The port lock is held. |
654 | */ |
655 | static void pmz_enable_ms(struct uart_port *port) |
656 | { |
657 | struct uart_pmac_port *uap = to_pmz(port); |
658 | unsigned char new_reg; |
659 | |
660 | if (ZS_IS_IRDA(uap)) |
661 | return; |
662 | new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE); |
663 | if (new_reg != uap->curregs[R15]) { |
664 | uap->curregs[R15] = new_reg; |
665 | |
666 | /* NOTE: Not subject to 'transmitter active' rule. */ |
667 | write_zsreg(port: uap, R15, value: uap->curregs[R15]); |
668 | } |
669 | } |
670 | |
671 | /* |
672 | * Control break state emission |
673 | * The port lock is not held. |
674 | */ |
675 | static void pmz_break_ctl(struct uart_port *port, int break_state) |
676 | { |
677 | struct uart_pmac_port *uap = to_pmz(port); |
678 | unsigned char set_bits, clear_bits, new_reg; |
679 | unsigned long flags; |
680 | |
681 | set_bits = clear_bits = 0; |
682 | |
683 | if (break_state) |
684 | set_bits |= SND_BRK; |
685 | else |
686 | clear_bits |= SND_BRK; |
687 | |
688 | uart_port_lock_irqsave(up: port, flags: &flags); |
689 | |
690 | new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits; |
691 | if (new_reg != uap->curregs[R5]) { |
692 | uap->curregs[R5] = new_reg; |
693 | write_zsreg(port: uap, R5, value: uap->curregs[R5]); |
694 | } |
695 | |
696 | uart_port_unlock_irqrestore(up: port, flags); |
697 | } |
698 | |
699 | #ifdef CONFIG_PPC_PMAC |
700 | |
701 | /* |
702 | * Turn power on or off to the SCC and associated stuff |
703 | * (port drivers, modem, IR port, etc.) |
704 | * Returns the number of milliseconds we should wait before |
705 | * trying to use the port. |
706 | */ |
707 | static int pmz_set_scc_power(struct uart_pmac_port *uap, int state) |
708 | { |
709 | int delay = 0; |
710 | int rc; |
711 | |
712 | if (state) { |
713 | rc = pmac_call_feature( |
714 | PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1); |
715 | pmz_debug("port power on result: %d\n" , rc); |
716 | if (ZS_IS_INTMODEM(uap)) { |
717 | rc = pmac_call_feature( |
718 | PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1); |
719 | delay = 2500; /* wait for 2.5s before using */ |
720 | pmz_debug("modem power result: %d\n" , rc); |
721 | } |
722 | } else { |
723 | /* TODO: Make that depend on a timer, don't power down |
724 | * immediately |
725 | */ |
726 | if (ZS_IS_INTMODEM(uap)) { |
727 | rc = pmac_call_feature( |
728 | PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0); |
729 | pmz_debug("port power off result: %d\n" , rc); |
730 | } |
731 | pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0); |
732 | } |
733 | return delay; |
734 | } |
735 | |
736 | #else |
737 | |
738 | static int pmz_set_scc_power(struct uart_pmac_port *uap, int state) |
739 | { |
740 | return 0; |
741 | } |
742 | |
743 | #endif /* !CONFIG_PPC_PMAC */ |
744 | |
745 | /* |
746 | * FixZeroBug....Works around a bug in the SCC receiving channel. |
747 | * Inspired from Darwin code, 15 Sept. 2000 -DanM |
748 | * |
749 | * The following sequence prevents a problem that is seen with O'Hare ASICs |
750 | * (most versions -- also with some Heathrow and Hydra ASICs) where a zero |
751 | * at the input to the receiver becomes 'stuck' and locks up the receiver. |
752 | * This problem can occur as a result of a zero bit at the receiver input |
753 | * coincident with any of the following events: |
754 | * |
755 | * The SCC is initialized (hardware or software). |
756 | * A framing error is detected. |
757 | * The clocking option changes from synchronous or X1 asynchronous |
758 | * clocking to X16, X32, or X64 asynchronous clocking. |
759 | * The decoding mode is changed among NRZ, NRZI, FM0, or FM1. |
760 | * |
761 | * This workaround attempts to recover from the lockup condition by placing |
762 | * the SCC in synchronous loopback mode with a fast clock before programming |
763 | * any of the asynchronous modes. |
764 | */ |
765 | static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap) |
766 | { |
767 | write_zsreg(port: uap, reg: 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB); |
768 | zssync(port: uap); |
769 | udelay(10); |
770 | write_zsreg(port: uap, reg: 9, value: (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV); |
771 | zssync(port: uap); |
772 | |
773 | write_zsreg(port: uap, reg: 4, X1CLK | MONSYNC); |
774 | write_zsreg(port: uap, reg: 3, Rx8); |
775 | write_zsreg(port: uap, reg: 5, Tx8 | RTS); |
776 | write_zsreg(port: uap, reg: 9, NV); /* Didn't we already do this? */ |
777 | write_zsreg(port: uap, reg: 11, RCBR | TCBR); |
778 | write_zsreg(port: uap, reg: 12, value: 0); |
779 | write_zsreg(port: uap, reg: 13, value: 0); |
780 | write_zsreg(port: uap, reg: 14, value: (LOOPBAK | BRSRC)); |
781 | write_zsreg(port: uap, reg: 14, value: (LOOPBAK | BRSRC | BRENAB)); |
782 | write_zsreg(port: uap, reg: 3, Rx8 | RxENABLE); |
783 | write_zsreg(port: uap, reg: 0, RES_EXT_INT); |
784 | write_zsreg(port: uap, reg: 0, RES_EXT_INT); |
785 | write_zsreg(port: uap, reg: 0, RES_EXT_INT); /* to kill some time */ |
786 | |
787 | /* The channel should be OK now, but it is probably receiving |
788 | * loopback garbage. |
789 | * Switch to asynchronous mode, disable the receiver, |
790 | * and discard everything in the receive buffer. |
791 | */ |
792 | write_zsreg(port: uap, reg: 9, NV); |
793 | write_zsreg(port: uap, reg: 4, X16CLK | SB_MASK); |
794 | write_zsreg(port: uap, reg: 3, Rx8); |
795 | |
796 | while (read_zsreg(port: uap, reg: 0) & Rx_CH_AV) { |
797 | (void)read_zsreg(port: uap, reg: 8); |
798 | write_zsreg(port: uap, reg: 0, RES_EXT_INT); |
799 | write_zsreg(port: uap, reg: 0, ERR_RES); |
800 | } |
801 | } |
802 | |
803 | /* |
804 | * Real startup routine, powers up the hardware and sets up |
805 | * the SCC. Returns a delay in ms where you need to wait before |
806 | * actually using the port, this is typically the internal modem |
807 | * powerup delay. This routine expect the lock to be taken. |
808 | */ |
809 | static int __pmz_startup(struct uart_pmac_port *uap) |
810 | { |
811 | int pwr_delay = 0; |
812 | |
813 | memset(&uap->curregs, 0, sizeof(uap->curregs)); |
814 | |
815 | /* Power up the SCC & underlying hardware (modem/irda) */ |
816 | pwr_delay = pmz_set_scc_power(uap, state: 1); |
817 | |
818 | /* Nice buggy HW ... */ |
819 | pmz_fix_zero_bug_scc(uap); |
820 | |
821 | /* Reset the channel */ |
822 | uap->curregs[R9] = 0; |
823 | write_zsreg(port: uap, reg: 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB); |
824 | zssync(port: uap); |
825 | udelay(10); |
826 | write_zsreg(port: uap, reg: 9, value: 0); |
827 | zssync(port: uap); |
828 | |
829 | /* Clear the interrupt registers */ |
830 | write_zsreg(port: uap, R1, value: 0); |
831 | write_zsreg(port: uap, R0, ERR_RES); |
832 | write_zsreg(port: uap, R0, ERR_RES); |
833 | write_zsreg(port: uap, R0, RES_H_IUS); |
834 | write_zsreg(port: uap, R0, RES_H_IUS); |
835 | |
836 | /* Setup some valid baud rate */ |
837 | uap->curregs[R4] = X16CLK | SB1; |
838 | uap->curregs[R3] = Rx8; |
839 | uap->curregs[R5] = Tx8 | RTS; |
840 | if (!ZS_IS_IRDA(uap)) |
841 | uap->curregs[R5] |= DTR; |
842 | uap->curregs[R12] = 0; |
843 | uap->curregs[R13] = 0; |
844 | uap->curregs[R14] = BRENAB; |
845 | |
846 | /* Clear handshaking, enable BREAK interrupts */ |
847 | uap->curregs[R15] = BRKIE; |
848 | |
849 | /* Master interrupt enable */ |
850 | uap->curregs[R9] |= NV | MIE; |
851 | |
852 | pmz_load_zsregs(uap, regs: uap->curregs); |
853 | |
854 | /* Enable receiver and transmitter. */ |
855 | write_zsreg(port: uap, R3, value: uap->curregs[R3] |= RxENABLE); |
856 | write_zsreg(port: uap, R5, value: uap->curregs[R5] |= TxENABLE); |
857 | |
858 | /* Remember status for DCD/CTS changes */ |
859 | uap->prev_status = read_zsreg(port: uap, R0); |
860 | |
861 | return pwr_delay; |
862 | } |
863 | |
864 | static void pmz_irda_reset(struct uart_pmac_port *uap) |
865 | { |
866 | unsigned long flags; |
867 | |
868 | uart_port_lock_irqsave(up: &uap->port, flags: &flags); |
869 | uap->curregs[R5] |= DTR; |
870 | write_zsreg(port: uap, R5, value: uap->curregs[R5]); |
871 | zssync(port: uap); |
872 | uart_port_unlock_irqrestore(up: &uap->port, flags); |
873 | msleep(msecs: 110); |
874 | |
875 | uart_port_lock_irqsave(up: &uap->port, flags: &flags); |
876 | uap->curregs[R5] &= ~DTR; |
877 | write_zsreg(port: uap, R5, value: uap->curregs[R5]); |
878 | zssync(port: uap); |
879 | uart_port_unlock_irqrestore(up: &uap->port, flags); |
880 | msleep(msecs: 10); |
881 | } |
882 | |
883 | /* |
884 | * This is the "normal" startup routine, using the above one |
885 | * wrapped with the lock and doing a schedule delay |
886 | */ |
887 | static int pmz_startup(struct uart_port *port) |
888 | { |
889 | struct uart_pmac_port *uap = to_pmz(port); |
890 | unsigned long flags; |
891 | int pwr_delay = 0; |
892 | |
893 | uap->flags |= PMACZILOG_FLAG_IS_OPEN; |
894 | |
895 | /* A console is never powered down. Else, power up and |
896 | * initialize the chip |
897 | */ |
898 | if (!ZS_IS_CONS(uap)) { |
899 | uart_port_lock_irqsave(up: port, flags: &flags); |
900 | pwr_delay = __pmz_startup(uap); |
901 | uart_port_unlock_irqrestore(up: port, flags); |
902 | } |
903 | sprintf(buf: uap->irq_name, PMACZILOG_NAME"%d" , uap->port.line); |
904 | if (request_irq(irq: uap->port.irq, handler: pmz_interrupt, IRQF_SHARED, |
905 | name: uap->irq_name, dev: uap)) { |
906 | pmz_error("Unable to register zs interrupt handler.\n" ); |
907 | pmz_set_scc_power(uap, state: 0); |
908 | return -ENXIO; |
909 | } |
910 | |
911 | /* Right now, we deal with delay by blocking here, I'll be |
912 | * smarter later on |
913 | */ |
914 | if (pwr_delay != 0) { |
915 | pmz_debug("pmz: delaying %d ms\n" , pwr_delay); |
916 | msleep(msecs: pwr_delay); |
917 | } |
918 | |
919 | /* IrDA reset is done now */ |
920 | if (ZS_IS_IRDA(uap)) |
921 | pmz_irda_reset(uap); |
922 | |
923 | /* Enable interrupt requests for the channel */ |
924 | uart_port_lock_irqsave(up: port, flags: &flags); |
925 | pmz_interrupt_control(uap, enable: 1); |
926 | uart_port_unlock_irqrestore(up: port, flags); |
927 | |
928 | return 0; |
929 | } |
930 | |
931 | static void pmz_shutdown(struct uart_port *port) |
932 | { |
933 | struct uart_pmac_port *uap = to_pmz(port); |
934 | unsigned long flags; |
935 | |
936 | uart_port_lock_irqsave(up: port, flags: &flags); |
937 | |
938 | /* Disable interrupt requests for the channel */ |
939 | pmz_interrupt_control(uap, enable: 0); |
940 | |
941 | if (!ZS_IS_CONS(uap)) { |
942 | /* Disable receiver and transmitter */ |
943 | uap->curregs[R3] &= ~RxENABLE; |
944 | uap->curregs[R5] &= ~TxENABLE; |
945 | |
946 | /* Disable break assertion */ |
947 | uap->curregs[R5] &= ~SND_BRK; |
948 | pmz_maybe_update_regs(uap); |
949 | } |
950 | |
951 | uart_port_unlock_irqrestore(up: port, flags); |
952 | |
953 | /* Release interrupt handler */ |
954 | free_irq(uap->port.irq, uap); |
955 | |
956 | uart_port_lock_irqsave(up: port, flags: &flags); |
957 | |
958 | uap->flags &= ~PMACZILOG_FLAG_IS_OPEN; |
959 | |
960 | if (!ZS_IS_CONS(uap)) |
961 | pmz_set_scc_power(uap, state: 0); /* Shut the chip down */ |
962 | |
963 | uart_port_unlock_irqrestore(up: port, flags); |
964 | } |
965 | |
966 | /* Shared by TTY driver and serial console setup. The port lock is held |
967 | * and local interrupts are disabled. |
968 | */ |
969 | static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag, |
970 | unsigned int iflag, unsigned long baud) |
971 | { |
972 | int brg; |
973 | |
974 | /* Switch to external clocking for IrDA high clock rates. That |
975 | * code could be re-used for Midi interfaces with different |
976 | * multipliers |
977 | */ |
978 | if (baud >= 115200 && ZS_IS_IRDA(uap)) { |
979 | uap->curregs[R4] = X1CLK; |
980 | uap->curregs[R11] = RCTRxCP | TCTRxCP; |
981 | uap->curregs[R14] = 0; /* BRG off */ |
982 | uap->curregs[R12] = 0; |
983 | uap->curregs[R13] = 0; |
984 | uap->flags |= PMACZILOG_FLAG_IS_EXTCLK; |
985 | } else { |
986 | switch (baud) { |
987 | case ZS_CLOCK/16: /* 230400 */ |
988 | uap->curregs[R4] = X16CLK; |
989 | uap->curregs[R11] = 0; |
990 | uap->curregs[R14] = 0; |
991 | break; |
992 | case ZS_CLOCK/32: /* 115200 */ |
993 | uap->curregs[R4] = X32CLK; |
994 | uap->curregs[R11] = 0; |
995 | uap->curregs[R14] = 0; |
996 | break; |
997 | default: |
998 | uap->curregs[R4] = X16CLK; |
999 | uap->curregs[R11] = TCBR | RCBR; |
1000 | brg = BPS_TO_BRG(baud, ZS_CLOCK / 16); |
1001 | uap->curregs[R12] = (brg & 255); |
1002 | uap->curregs[R13] = ((brg >> 8) & 255); |
1003 | uap->curregs[R14] = BRENAB; |
1004 | } |
1005 | uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK; |
1006 | } |
1007 | |
1008 | /* Character size, stop bits, and parity. */ |
1009 | uap->curregs[3] &= ~RxN_MASK; |
1010 | uap->curregs[5] &= ~TxN_MASK; |
1011 | |
1012 | switch (cflag & CSIZE) { |
1013 | case CS5: |
1014 | uap->curregs[3] |= Rx5; |
1015 | uap->curregs[5] |= Tx5; |
1016 | uap->parity_mask = 0x1f; |
1017 | break; |
1018 | case CS6: |
1019 | uap->curregs[3] |= Rx6; |
1020 | uap->curregs[5] |= Tx6; |
1021 | uap->parity_mask = 0x3f; |
1022 | break; |
1023 | case CS7: |
1024 | uap->curregs[3] |= Rx7; |
1025 | uap->curregs[5] |= Tx7; |
1026 | uap->parity_mask = 0x7f; |
1027 | break; |
1028 | case CS8: |
1029 | default: |
1030 | uap->curregs[3] |= Rx8; |
1031 | uap->curregs[5] |= Tx8; |
1032 | uap->parity_mask = 0xff; |
1033 | break; |
1034 | } |
1035 | uap->curregs[4] &= ~(SB_MASK); |
1036 | if (cflag & CSTOPB) |
1037 | uap->curregs[4] |= SB2; |
1038 | else |
1039 | uap->curregs[4] |= SB1; |
1040 | if (cflag & PARENB) |
1041 | uap->curregs[4] |= PAR_ENAB; |
1042 | else |
1043 | uap->curregs[4] &= ~PAR_ENAB; |
1044 | if (!(cflag & PARODD)) |
1045 | uap->curregs[4] |= PAR_EVEN; |
1046 | else |
1047 | uap->curregs[4] &= ~PAR_EVEN; |
1048 | |
1049 | uap->port.read_status_mask = Rx_OVR; |
1050 | if (iflag & INPCK) |
1051 | uap->port.read_status_mask |= CRC_ERR | PAR_ERR; |
1052 | if (iflag & (IGNBRK | BRKINT | PARMRK)) |
1053 | uap->port.read_status_mask |= BRK_ABRT; |
1054 | |
1055 | uap->port.ignore_status_mask = 0; |
1056 | if (iflag & IGNPAR) |
1057 | uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR; |
1058 | if (iflag & IGNBRK) { |
1059 | uap->port.ignore_status_mask |= BRK_ABRT; |
1060 | if (iflag & IGNPAR) |
1061 | uap->port.ignore_status_mask |= Rx_OVR; |
1062 | } |
1063 | |
1064 | if ((cflag & CREAD) == 0) |
1065 | uap->port.ignore_status_mask = 0xff; |
1066 | } |
1067 | |
1068 | |
1069 | /* |
1070 | * Set the irda codec on the imac to the specified baud rate. |
1071 | */ |
1072 | static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud) |
1073 | { |
1074 | u8 cmdbyte; |
1075 | int t, version; |
1076 | |
1077 | switch (*baud) { |
1078 | /* SIR modes */ |
1079 | case 2400: |
1080 | cmdbyte = 0x53; |
1081 | break; |
1082 | case 4800: |
1083 | cmdbyte = 0x52; |
1084 | break; |
1085 | case 9600: |
1086 | cmdbyte = 0x51; |
1087 | break; |
1088 | case 19200: |
1089 | cmdbyte = 0x50; |
1090 | break; |
1091 | case 38400: |
1092 | cmdbyte = 0x4f; |
1093 | break; |
1094 | case 57600: |
1095 | cmdbyte = 0x4e; |
1096 | break; |
1097 | case 115200: |
1098 | cmdbyte = 0x4d; |
1099 | break; |
1100 | /* The FIR modes aren't really supported at this point, how |
1101 | * do we select the speed ? via the FCR on KeyLargo ? |
1102 | */ |
1103 | case 1152000: |
1104 | cmdbyte = 0; |
1105 | break; |
1106 | case 4000000: |
1107 | cmdbyte = 0; |
1108 | break; |
1109 | default: /* 9600 */ |
1110 | cmdbyte = 0x51; |
1111 | *baud = 9600; |
1112 | break; |
1113 | } |
1114 | |
1115 | /* Wait for transmitter to drain */ |
1116 | t = 10000; |
1117 | while ((read_zsreg(port: uap, R0) & Tx_BUF_EMP) == 0 |
1118 | || (read_zsreg(port: uap, R1) & ALL_SNT) == 0) { |
1119 | if (--t <= 0) { |
1120 | pmz_error("transmitter didn't drain\n" ); |
1121 | return; |
1122 | } |
1123 | udelay(10); |
1124 | } |
1125 | |
1126 | /* Drain the receiver too */ |
1127 | t = 100; |
1128 | (void)read_zsdata(port: uap); |
1129 | (void)read_zsdata(port: uap); |
1130 | (void)read_zsdata(port: uap); |
1131 | mdelay(10); |
1132 | while (read_zsreg(port: uap, R0) & Rx_CH_AV) { |
1133 | read_zsdata(port: uap); |
1134 | mdelay(10); |
1135 | if (--t <= 0) { |
1136 | pmz_error("receiver didn't drain\n" ); |
1137 | return; |
1138 | } |
1139 | } |
1140 | |
1141 | /* Switch to command mode */ |
1142 | uap->curregs[R5] |= DTR; |
1143 | write_zsreg(port: uap, R5, value: uap->curregs[R5]); |
1144 | zssync(port: uap); |
1145 | mdelay(1); |
1146 | |
1147 | /* Switch SCC to 19200 */ |
1148 | pmz_convert_to_zs(uap, CS8, iflag: 0, baud: 19200); |
1149 | pmz_load_zsregs(uap, regs: uap->curregs); |
1150 | mdelay(1); |
1151 | |
1152 | /* Write get_version command byte */ |
1153 | write_zsdata(port: uap, data: 1); |
1154 | t = 5000; |
1155 | while ((read_zsreg(port: uap, R0) & Rx_CH_AV) == 0) { |
1156 | if (--t <= 0) { |
1157 | pmz_error("irda_setup timed out on get_version byte\n" ); |
1158 | goto out; |
1159 | } |
1160 | udelay(10); |
1161 | } |
1162 | version = read_zsdata(port: uap); |
1163 | |
1164 | if (version < 4) { |
1165 | pmz_info("IrDA: dongle version %d not supported\n" , version); |
1166 | goto out; |
1167 | } |
1168 | |
1169 | /* Send speed mode */ |
1170 | write_zsdata(port: uap, data: cmdbyte); |
1171 | t = 5000; |
1172 | while ((read_zsreg(port: uap, R0) & Rx_CH_AV) == 0) { |
1173 | if (--t <= 0) { |
1174 | pmz_error("irda_setup timed out on speed mode byte\n" ); |
1175 | goto out; |
1176 | } |
1177 | udelay(10); |
1178 | } |
1179 | t = read_zsdata(port: uap); |
1180 | if (t != cmdbyte) |
1181 | pmz_error("irda_setup speed mode byte = %x (%x)\n" , t, cmdbyte); |
1182 | |
1183 | pmz_info("IrDA setup for %ld bps, dongle version: %d\n" , |
1184 | *baud, version); |
1185 | |
1186 | (void)read_zsdata(port: uap); |
1187 | (void)read_zsdata(port: uap); |
1188 | (void)read_zsdata(port: uap); |
1189 | |
1190 | out: |
1191 | /* Switch back to data mode */ |
1192 | uap->curregs[R5] &= ~DTR; |
1193 | write_zsreg(port: uap, R5, value: uap->curregs[R5]); |
1194 | zssync(port: uap); |
1195 | |
1196 | (void)read_zsdata(port: uap); |
1197 | (void)read_zsdata(port: uap); |
1198 | (void)read_zsdata(port: uap); |
1199 | } |
1200 | |
1201 | |
1202 | static void __pmz_set_termios(struct uart_port *port, struct ktermios *termios, |
1203 | const struct ktermios *old) |
1204 | { |
1205 | struct uart_pmac_port *uap = to_pmz(port); |
1206 | unsigned long baud; |
1207 | |
1208 | /* XXX Check which revs of machines actually allow 1 and 4Mb speeds |
1209 | * on the IR dongle. Note that the IRTTY driver currently doesn't know |
1210 | * about the FIR mode and high speed modes. So these are unused. For |
1211 | * implementing proper support for these, we should probably add some |
1212 | * DMA as well, at least on the Rx side, which isn't a simple thing |
1213 | * at this point. |
1214 | */ |
1215 | if (ZS_IS_IRDA(uap)) { |
1216 | /* Calc baud rate */ |
1217 | baud = uart_get_baud_rate(port, termios, old, min: 1200, max: 4000000); |
1218 | pmz_debug("pmz: switch IRDA to %ld bauds\n" , baud); |
1219 | /* Cet the irda codec to the right rate */ |
1220 | pmz_irda_setup(uap, baud: &baud); |
1221 | /* Set final baud rate */ |
1222 | pmz_convert_to_zs(uap, cflag: termios->c_cflag, iflag: termios->c_iflag, baud); |
1223 | pmz_load_zsregs(uap, regs: uap->curregs); |
1224 | zssync(port: uap); |
1225 | } else { |
1226 | baud = uart_get_baud_rate(port, termios, old, min: 1200, max: 230400); |
1227 | pmz_convert_to_zs(uap, cflag: termios->c_cflag, iflag: termios->c_iflag, baud); |
1228 | /* Make sure modem status interrupts are correctly configured */ |
1229 | if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) { |
1230 | uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE; |
1231 | uap->flags |= PMACZILOG_FLAG_MODEM_STATUS; |
1232 | } else { |
1233 | uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE); |
1234 | uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS; |
1235 | } |
1236 | |
1237 | /* Load registers to the chip */ |
1238 | pmz_maybe_update_regs(uap); |
1239 | } |
1240 | uart_update_timeout(port, cflag: termios->c_cflag, baud); |
1241 | } |
1242 | |
1243 | /* The port lock is not held. */ |
1244 | static void pmz_set_termios(struct uart_port *port, struct ktermios *termios, |
1245 | const struct ktermios *old) |
1246 | { |
1247 | struct uart_pmac_port *uap = to_pmz(port); |
1248 | unsigned long flags; |
1249 | |
1250 | uart_port_lock_irqsave(up: port, flags: &flags); |
1251 | |
1252 | /* Disable IRQs on the port */ |
1253 | pmz_interrupt_control(uap, enable: 0); |
1254 | |
1255 | /* Setup new port configuration */ |
1256 | __pmz_set_termios(port, termios, old); |
1257 | |
1258 | /* Re-enable IRQs on the port */ |
1259 | if (ZS_IS_OPEN(uap)) |
1260 | pmz_interrupt_control(uap, enable: 1); |
1261 | |
1262 | uart_port_unlock_irqrestore(up: port, flags); |
1263 | } |
1264 | |
1265 | static const char *pmz_type(struct uart_port *port) |
1266 | { |
1267 | struct uart_pmac_port *uap = to_pmz(port); |
1268 | |
1269 | if (ZS_IS_IRDA(uap)) |
1270 | return "Z85c30 ESCC - Infrared port" ; |
1271 | else if (ZS_IS_INTMODEM(uap)) |
1272 | return "Z85c30 ESCC - Internal modem" ; |
1273 | return "Z85c30 ESCC - Serial port" ; |
1274 | } |
1275 | |
1276 | /* We do not request/release mappings of the registers here, this |
1277 | * happens at early serial probe time. |
1278 | */ |
1279 | static void pmz_release_port(struct uart_port *port) |
1280 | { |
1281 | } |
1282 | |
1283 | static int pmz_request_port(struct uart_port *port) |
1284 | { |
1285 | return 0; |
1286 | } |
1287 | |
1288 | /* These do not need to do anything interesting either. */ |
1289 | static void pmz_config_port(struct uart_port *port, int flags) |
1290 | { |
1291 | } |
1292 | |
1293 | /* We do not support letting the user mess with the divisor, IRQ, etc. */ |
1294 | static int pmz_verify_port(struct uart_port *port, struct serial_struct *ser) |
1295 | { |
1296 | return -EINVAL; |
1297 | } |
1298 | |
1299 | #ifdef CONFIG_CONSOLE_POLL |
1300 | |
1301 | static int pmz_poll_get_char(struct uart_port *port) |
1302 | { |
1303 | struct uart_pmac_port *uap = |
1304 | container_of(port, struct uart_pmac_port, port); |
1305 | int tries = 2; |
1306 | |
1307 | while (tries) { |
1308 | if ((read_zsreg(port: uap, R0) & Rx_CH_AV) != 0) |
1309 | return read_zsdata(port: uap); |
1310 | if (tries--) |
1311 | udelay(5); |
1312 | } |
1313 | |
1314 | return NO_POLL_CHAR; |
1315 | } |
1316 | |
1317 | static void pmz_poll_put_char(struct uart_port *port, unsigned char c) |
1318 | { |
1319 | struct uart_pmac_port *uap = |
1320 | container_of(port, struct uart_pmac_port, port); |
1321 | |
1322 | /* Wait for the transmit buffer to empty. */ |
1323 | while ((read_zsreg(port: uap, R0) & Tx_BUF_EMP) == 0) |
1324 | udelay(5); |
1325 | write_zsdata(port: uap, data: c); |
1326 | } |
1327 | |
1328 | #endif /* CONFIG_CONSOLE_POLL */ |
1329 | |
1330 | static const struct uart_ops pmz_pops = { |
1331 | .tx_empty = pmz_tx_empty, |
1332 | .set_mctrl = pmz_set_mctrl, |
1333 | .get_mctrl = pmz_get_mctrl, |
1334 | .stop_tx = pmz_stop_tx, |
1335 | .start_tx = pmz_start_tx, |
1336 | .stop_rx = pmz_stop_rx, |
1337 | .enable_ms = pmz_enable_ms, |
1338 | .break_ctl = pmz_break_ctl, |
1339 | .startup = pmz_startup, |
1340 | .shutdown = pmz_shutdown, |
1341 | .set_termios = pmz_set_termios, |
1342 | .type = pmz_type, |
1343 | .release_port = pmz_release_port, |
1344 | .request_port = pmz_request_port, |
1345 | .config_port = pmz_config_port, |
1346 | .verify_port = pmz_verify_port, |
1347 | #ifdef CONFIG_CONSOLE_POLL |
1348 | .poll_get_char = pmz_poll_get_char, |
1349 | .poll_put_char = pmz_poll_put_char, |
1350 | #endif |
1351 | }; |
1352 | |
1353 | #ifdef CONFIG_PPC_PMAC |
1354 | |
1355 | /* |
1356 | * Setup one port structure after probing, HW is down at this point, |
1357 | * Unlike sunzilog, we don't need to pre-init the spinlock as we don't |
1358 | * register our console before uart_add_one_port() is called |
1359 | */ |
1360 | static int __init pmz_init_port(struct uart_pmac_port *uap) |
1361 | { |
1362 | struct device_node *np = uap->node; |
1363 | const char *conn; |
1364 | const struct slot_names_prop { |
1365 | int count; |
1366 | char name[1]; |
1367 | } *slots; |
1368 | int len; |
1369 | struct resource r_ports; |
1370 | |
1371 | /* |
1372 | * Request & map chip registers |
1373 | */ |
1374 | if (of_address_to_resource(np, 0, &r_ports)) |
1375 | return -ENODEV; |
1376 | uap->port.mapbase = r_ports.start; |
1377 | uap->port.membase = ioremap(uap->port.mapbase, 0x1000); |
1378 | |
1379 | uap->control_reg = uap->port.membase; |
1380 | uap->data_reg = uap->control_reg + 0x10; |
1381 | |
1382 | /* |
1383 | * Detect port type |
1384 | */ |
1385 | if (of_device_is_compatible(np, "cobalt" )) |
1386 | uap->flags |= PMACZILOG_FLAG_IS_INTMODEM; |
1387 | conn = of_get_property(np, "AAPL,connector" , &len); |
1388 | if (conn && (strcmp(conn, "infrared" ) == 0)) |
1389 | uap->flags |= PMACZILOG_FLAG_IS_IRDA; |
1390 | uap->port_type = PMAC_SCC_ASYNC; |
1391 | /* 1999 Powerbook G3 has slot-names property instead */ |
1392 | slots = of_get_property(np, "slot-names" , &len); |
1393 | if (slots && slots->count > 0) { |
1394 | if (strcmp(slots->name, "IrDA" ) == 0) |
1395 | uap->flags |= PMACZILOG_FLAG_IS_IRDA; |
1396 | else if (strcmp(slots->name, "Modem" ) == 0) |
1397 | uap->flags |= PMACZILOG_FLAG_IS_INTMODEM; |
1398 | } |
1399 | if (ZS_IS_IRDA(uap)) |
1400 | uap->port_type = PMAC_SCC_IRDA; |
1401 | if (ZS_IS_INTMODEM(uap)) { |
1402 | struct device_node* i2c_modem = |
1403 | of_find_node_by_name(NULL, "i2c-modem" ); |
1404 | if (i2c_modem) { |
1405 | const char* mid = |
1406 | of_get_property(i2c_modem, "modem-id" , NULL); |
1407 | if (mid) switch(*mid) { |
1408 | case 0x04 : |
1409 | case 0x05 : |
1410 | case 0x07 : |
1411 | case 0x08 : |
1412 | case 0x0b : |
1413 | case 0x0c : |
1414 | uap->port_type = PMAC_SCC_I2S1; |
1415 | } |
1416 | printk(KERN_INFO "pmac_zilog: i2c-modem detected, id: %d\n" , |
1417 | mid ? (*mid) : 0); |
1418 | of_node_put(i2c_modem); |
1419 | } else { |
1420 | printk(KERN_INFO "pmac_zilog: serial modem detected\n" ); |
1421 | } |
1422 | } |
1423 | |
1424 | /* |
1425 | * Init remaining bits of "port" structure |
1426 | */ |
1427 | uap->port.iotype = UPIO_MEM; |
1428 | uap->port.irq = irq_of_parse_and_map(np, 0); |
1429 | uap->port.uartclk = ZS_CLOCK; |
1430 | uap->port.fifosize = 1; |
1431 | uap->port.ops = &pmz_pops; |
1432 | uap->port.type = PORT_PMAC_ZILOG; |
1433 | uap->port.flags = 0; |
1434 | |
1435 | /* |
1436 | * Fixup for the port on Gatwick for which the device-tree has |
1437 | * missing interrupts. Normally, the macio_dev would contain |
1438 | * fixed up interrupt info, but we use the device-tree directly |
1439 | * here due to early probing so we need the fixup too. |
1440 | */ |
1441 | if (uap->port.irq == 0 && |
1442 | np->parent && np->parent->parent && |
1443 | of_device_is_compatible(np->parent->parent, "gatwick" )) { |
1444 | /* IRQs on gatwick are offset by 64 */ |
1445 | uap->port.irq = irq_create_mapping(NULL, 64 + 15); |
1446 | } |
1447 | |
1448 | /* Setup some valid baud rate information in the register |
1449 | * shadows so we don't write crap there before baud rate is |
1450 | * first initialized. |
1451 | */ |
1452 | pmz_convert_to_zs(uap, CS8, 0, 9600); |
1453 | |
1454 | return 0; |
1455 | } |
1456 | |
1457 | /* |
1458 | * Get rid of a port on module removal |
1459 | */ |
1460 | static void pmz_dispose_port(struct uart_pmac_port *uap) |
1461 | { |
1462 | struct device_node *np; |
1463 | |
1464 | np = uap->node; |
1465 | iounmap(uap->control_reg); |
1466 | uap->node = NULL; |
1467 | of_node_put(np); |
1468 | memset(uap, 0, sizeof(struct uart_pmac_port)); |
1469 | } |
1470 | |
1471 | /* |
1472 | * Called upon match with an escc node in the device-tree. |
1473 | */ |
1474 | static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match) |
1475 | { |
1476 | struct uart_pmac_port *uap; |
1477 | int i; |
1478 | |
1479 | /* Iterate the pmz_ports array to find a matching entry |
1480 | */ |
1481 | for (i = 0; i < MAX_ZS_PORTS; i++) |
1482 | if (pmz_ports[i].node == mdev->ofdev.dev.of_node) |
1483 | break; |
1484 | if (i >= MAX_ZS_PORTS) |
1485 | return -ENODEV; |
1486 | |
1487 | |
1488 | uap = &pmz_ports[i]; |
1489 | uap->dev = mdev; |
1490 | uap->port.dev = &mdev->ofdev.dev; |
1491 | dev_set_drvdata(&mdev->ofdev.dev, uap); |
1492 | |
1493 | /* We still activate the port even when failing to request resources |
1494 | * to work around bugs in ancient Apple device-trees |
1495 | */ |
1496 | if (macio_request_resources(uap->dev, "pmac_zilog" )) |
1497 | printk(KERN_WARNING "%pOFn: Failed to request resource" |
1498 | ", port still active\n" , |
1499 | uap->node); |
1500 | else |
1501 | uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED; |
1502 | |
1503 | return uart_add_one_port(&pmz_uart_reg, &uap->port); |
1504 | } |
1505 | |
1506 | /* |
1507 | * That one should not be called, macio isn't really a hotswap device, |
1508 | * we don't expect one of those serial ports to go away... |
1509 | */ |
1510 | static int pmz_detach(struct macio_dev *mdev) |
1511 | { |
1512 | struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); |
1513 | |
1514 | if (!uap) |
1515 | return -ENODEV; |
1516 | |
1517 | uart_remove_one_port(&pmz_uart_reg, &uap->port); |
1518 | |
1519 | if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) { |
1520 | macio_release_resources(uap->dev); |
1521 | uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED; |
1522 | } |
1523 | dev_set_drvdata(&mdev->ofdev.dev, NULL); |
1524 | uap->dev = NULL; |
1525 | uap->port.dev = NULL; |
1526 | |
1527 | return 0; |
1528 | } |
1529 | |
1530 | |
1531 | static int pmz_suspend(struct macio_dev *mdev, pm_message_t pm_state) |
1532 | { |
1533 | struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); |
1534 | |
1535 | if (uap == NULL) { |
1536 | printk("HRM... pmz_suspend with NULL uap\n" ); |
1537 | return 0; |
1538 | } |
1539 | |
1540 | uart_suspend_port(&pmz_uart_reg, &uap->port); |
1541 | |
1542 | return 0; |
1543 | } |
1544 | |
1545 | |
1546 | static int pmz_resume(struct macio_dev *mdev) |
1547 | { |
1548 | struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); |
1549 | |
1550 | if (uap == NULL) |
1551 | return 0; |
1552 | |
1553 | uart_resume_port(&pmz_uart_reg, &uap->port); |
1554 | |
1555 | return 0; |
1556 | } |
1557 | |
1558 | /* |
1559 | * Probe all ports in the system and build the ports array, we register |
1560 | * with the serial layer later, so we get a proper struct device which |
1561 | * allows the tty to attach properly. This is later than it used to be |
1562 | * but the tty layer really wants it that way. |
1563 | */ |
1564 | static int __init pmz_probe(void) |
1565 | { |
1566 | struct device_node *node_p, *node_a, *node_b, *np; |
1567 | int count = 0; |
1568 | int rc; |
1569 | |
1570 | /* |
1571 | * Find all escc chips in the system |
1572 | */ |
1573 | for_each_node_by_name(node_p, "escc" ) { |
1574 | /* |
1575 | * First get channel A/B node pointers |
1576 | * |
1577 | * TODO: Add routines with proper locking to do that... |
1578 | */ |
1579 | node_a = node_b = NULL; |
1580 | for_each_child_of_node(node_p, np) { |
1581 | if (of_node_name_prefix(np, "ch-a" )) |
1582 | node_a = of_node_get(np); |
1583 | else if (of_node_name_prefix(np, "ch-b" )) |
1584 | node_b = of_node_get(np); |
1585 | } |
1586 | if (!node_a && !node_b) { |
1587 | of_node_put(node_a); |
1588 | of_node_put(node_b); |
1589 | printk(KERN_ERR "pmac_zilog: missing node %c for escc %pOF\n" , |
1590 | (!node_a) ? 'a' : 'b', node_p); |
1591 | continue; |
1592 | } |
1593 | |
1594 | /* |
1595 | * Fill basic fields in the port structures |
1596 | */ |
1597 | if (node_b != NULL) { |
1598 | pmz_ports[count].mate = &pmz_ports[count+1]; |
1599 | pmz_ports[count+1].mate = &pmz_ports[count]; |
1600 | } |
1601 | pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A; |
1602 | pmz_ports[count].node = node_a; |
1603 | pmz_ports[count+1].node = node_b; |
1604 | pmz_ports[count].port.line = count; |
1605 | pmz_ports[count+1].port.line = count+1; |
1606 | |
1607 | /* |
1608 | * Setup the ports for real |
1609 | */ |
1610 | rc = pmz_init_port(&pmz_ports[count]); |
1611 | if (rc == 0 && node_b != NULL) |
1612 | rc = pmz_init_port(&pmz_ports[count+1]); |
1613 | if (rc != 0) { |
1614 | of_node_put(node_a); |
1615 | of_node_put(node_b); |
1616 | memset(&pmz_ports[count], 0, sizeof(struct uart_pmac_port)); |
1617 | memset(&pmz_ports[count+1], 0, sizeof(struct uart_pmac_port)); |
1618 | continue; |
1619 | } |
1620 | count += 2; |
1621 | } |
1622 | pmz_ports_count = count; |
1623 | |
1624 | return 0; |
1625 | } |
1626 | |
1627 | #else |
1628 | |
1629 | /* On PCI PowerMacs, pmz_probe() does an explicit search of the OpenFirmware |
1630 | * tree to obtain the device_nodes needed to start the console before the |
1631 | * macio driver. On Macs without OpenFirmware, global platform_devices take |
1632 | * the place of those device_nodes. |
1633 | */ |
1634 | extern struct platform_device scc_a_pdev, scc_b_pdev; |
1635 | |
1636 | static int __init pmz_init_port(struct uart_pmac_port *uap) |
1637 | { |
1638 | struct resource *r_ports; |
1639 | int irq; |
1640 | |
1641 | r_ports = platform_get_resource(uap->pdev, IORESOURCE_MEM, 0); |
1642 | if (!r_ports) |
1643 | return -ENODEV; |
1644 | |
1645 | irq = platform_get_irq(uap->pdev, 0); |
1646 | if (irq < 0) |
1647 | return irq; |
1648 | |
1649 | uap->port.mapbase = r_ports->start; |
1650 | uap->port.membase = (unsigned char __iomem *) r_ports->start; |
1651 | uap->port.iotype = UPIO_MEM; |
1652 | uap->port.irq = irq; |
1653 | uap->port.uartclk = ZS_CLOCK; |
1654 | uap->port.fifosize = 1; |
1655 | uap->port.ops = &pmz_pops; |
1656 | uap->port.type = PORT_PMAC_ZILOG; |
1657 | uap->port.flags = 0; |
1658 | |
1659 | uap->control_reg = uap->port.membase; |
1660 | uap->data_reg = uap->control_reg + 4; |
1661 | uap->port_type = 0; |
1662 | uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PMACZILOG_CONSOLE); |
1663 | |
1664 | pmz_convert_to_zs(uap, CS8, iflag: 0, baud: 9600); |
1665 | |
1666 | return 0; |
1667 | } |
1668 | |
1669 | static int __init pmz_probe(void) |
1670 | { |
1671 | int err; |
1672 | |
1673 | pmz_ports_count = 0; |
1674 | |
1675 | pmz_ports[0].port.line = 0; |
1676 | pmz_ports[0].flags = PMACZILOG_FLAG_IS_CHANNEL_A; |
1677 | pmz_ports[0].pdev = &scc_a_pdev; |
1678 | err = pmz_init_port(uap: &pmz_ports[0]); |
1679 | if (err) |
1680 | return err; |
1681 | pmz_ports_count++; |
1682 | |
1683 | pmz_ports[0].mate = &pmz_ports[1]; |
1684 | pmz_ports[1].mate = &pmz_ports[0]; |
1685 | pmz_ports[1].port.line = 1; |
1686 | pmz_ports[1].flags = 0; |
1687 | pmz_ports[1].pdev = &scc_b_pdev; |
1688 | err = pmz_init_port(uap: &pmz_ports[1]); |
1689 | if (err) |
1690 | return err; |
1691 | pmz_ports_count++; |
1692 | |
1693 | return 0; |
1694 | } |
1695 | |
1696 | static void pmz_dispose_port(struct uart_pmac_port *uap) |
1697 | { |
1698 | memset(uap, 0, sizeof(struct uart_pmac_port)); |
1699 | } |
1700 | |
1701 | static int __init pmz_attach(struct platform_device *pdev) |
1702 | { |
1703 | struct uart_pmac_port *uap; |
1704 | int i; |
1705 | |
1706 | /* Iterate the pmz_ports array to find a matching entry */ |
1707 | for (i = 0; i < pmz_ports_count; i++) |
1708 | if (pmz_ports[i].pdev == pdev) |
1709 | break; |
1710 | if (i >= pmz_ports_count) |
1711 | return -ENODEV; |
1712 | |
1713 | uap = &pmz_ports[i]; |
1714 | uap->port.dev = &pdev->dev; |
1715 | platform_set_drvdata(pdev, data: uap); |
1716 | |
1717 | return uart_add_one_port(reg: &pmz_uart_reg, port: &uap->port); |
1718 | } |
1719 | |
1720 | static int __exit pmz_detach(struct platform_device *pdev) |
1721 | { |
1722 | struct uart_pmac_port *uap = platform_get_drvdata(pdev); |
1723 | |
1724 | if (!uap) |
1725 | return -ENODEV; |
1726 | |
1727 | uart_remove_one_port(reg: &pmz_uart_reg, port: &uap->port); |
1728 | |
1729 | uap->port.dev = NULL; |
1730 | |
1731 | return 0; |
1732 | } |
1733 | |
1734 | #endif /* !CONFIG_PPC_PMAC */ |
1735 | |
1736 | #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE |
1737 | |
1738 | static void pmz_console_write(struct console *con, const char *s, unsigned int count); |
1739 | static int __init pmz_console_setup(struct console *co, char *options); |
1740 | |
1741 | static struct console pmz_console = { |
1742 | .name = PMACZILOG_NAME, |
1743 | .write = pmz_console_write, |
1744 | .device = uart_console_device, |
1745 | .setup = pmz_console_setup, |
1746 | .flags = CON_PRINTBUFFER, |
1747 | .index = -1, |
1748 | .data = &pmz_uart_reg, |
1749 | }; |
1750 | |
1751 | #define PMACZILOG_CONSOLE &pmz_console |
1752 | #else /* CONFIG_SERIAL_PMACZILOG_CONSOLE */ |
1753 | #define PMACZILOG_CONSOLE (NULL) |
1754 | #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */ |
1755 | |
1756 | /* |
1757 | * Register the driver, console driver and ports with the serial |
1758 | * core |
1759 | */ |
1760 | static int __init pmz_register(void) |
1761 | { |
1762 | pmz_uart_reg.nr = pmz_ports_count; |
1763 | pmz_uart_reg.cons = PMACZILOG_CONSOLE; |
1764 | |
1765 | /* |
1766 | * Register this driver with the serial core |
1767 | */ |
1768 | return uart_register_driver(uart: &pmz_uart_reg); |
1769 | } |
1770 | |
1771 | #ifdef CONFIG_PPC_PMAC |
1772 | |
1773 | static const struct of_device_id pmz_match[] = |
1774 | { |
1775 | { |
1776 | .name = "ch-a" , |
1777 | }, |
1778 | { |
1779 | .name = "ch-b" , |
1780 | }, |
1781 | {}, |
1782 | }; |
1783 | MODULE_DEVICE_TABLE (of, pmz_match); |
1784 | |
1785 | static struct macio_driver pmz_driver = { |
1786 | .driver = { |
1787 | .name = "pmac_zilog" , |
1788 | .owner = THIS_MODULE, |
1789 | .of_match_table = pmz_match, |
1790 | }, |
1791 | .probe = pmz_attach, |
1792 | .remove = pmz_detach, |
1793 | .suspend = pmz_suspend, |
1794 | .resume = pmz_resume, |
1795 | }; |
1796 | |
1797 | #else |
1798 | |
1799 | static struct platform_driver pmz_driver = { |
1800 | .remove = __exit_p(pmz_detach), |
1801 | .driver = { |
1802 | .name = "scc" , |
1803 | }, |
1804 | }; |
1805 | |
1806 | #endif /* !CONFIG_PPC_PMAC */ |
1807 | |
1808 | static int __init init_pmz(void) |
1809 | { |
1810 | int rc, i; |
1811 | |
1812 | /* |
1813 | * First, we need to do a direct OF-based probe pass. We |
1814 | * do that because we want serial console up before the |
1815 | * macio stuffs calls us back, and since that makes it |
1816 | * easier to pass the proper number of channels to |
1817 | * uart_register_driver() |
1818 | */ |
1819 | if (pmz_ports_count == 0) |
1820 | pmz_probe(); |
1821 | |
1822 | /* |
1823 | * Bail early if no port found |
1824 | */ |
1825 | if (pmz_ports_count == 0) |
1826 | return -ENODEV; |
1827 | |
1828 | /* |
1829 | * Now we register with the serial layer |
1830 | */ |
1831 | rc = pmz_register(); |
1832 | if (rc) { |
1833 | printk(KERN_ERR |
1834 | "pmac_zilog: Error registering serial device, disabling pmac_zilog.\n" |
1835 | "pmac_zilog: Did another serial driver already claim the minors?\n" ); |
1836 | /* effectively "pmz_unprobe()" */ |
1837 | for (i=0; i < pmz_ports_count; i++) |
1838 | pmz_dispose_port(uap: &pmz_ports[i]); |
1839 | return rc; |
1840 | } |
1841 | |
1842 | /* |
1843 | * Then we register the macio driver itself |
1844 | */ |
1845 | #ifdef CONFIG_PPC_PMAC |
1846 | return macio_register_driver(&pmz_driver); |
1847 | #else |
1848 | return platform_driver_probe(&pmz_driver, pmz_attach); |
1849 | #endif |
1850 | } |
1851 | |
1852 | static void __exit exit_pmz(void) |
1853 | { |
1854 | int i; |
1855 | |
1856 | #ifdef CONFIG_PPC_PMAC |
1857 | /* Get rid of macio-driver (detach from macio) */ |
1858 | macio_unregister_driver(&pmz_driver); |
1859 | #else |
1860 | platform_driver_unregister(&pmz_driver); |
1861 | #endif |
1862 | |
1863 | for (i = 0; i < pmz_ports_count; i++) { |
1864 | struct uart_pmac_port *uport = &pmz_ports[i]; |
1865 | #ifdef CONFIG_PPC_PMAC |
1866 | if (uport->node != NULL) |
1867 | pmz_dispose_port(uport); |
1868 | #else |
1869 | if (uport->pdev != NULL) |
1870 | pmz_dispose_port(uap: uport); |
1871 | #endif |
1872 | } |
1873 | /* Unregister UART driver */ |
1874 | uart_unregister_driver(uart: &pmz_uart_reg); |
1875 | } |
1876 | |
1877 | #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE |
1878 | |
1879 | static void pmz_console_putchar(struct uart_port *port, unsigned char ch) |
1880 | { |
1881 | struct uart_pmac_port *uap = |
1882 | container_of(port, struct uart_pmac_port, port); |
1883 | |
1884 | /* Wait for the transmit buffer to empty. */ |
1885 | while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0) |
1886 | udelay(5); |
1887 | write_zsdata(uap, ch); |
1888 | } |
1889 | |
1890 | /* |
1891 | * Print a string to the serial port trying not to disturb |
1892 | * any possible real use of the port... |
1893 | */ |
1894 | static void pmz_console_write(struct console *con, const char *s, unsigned int count) |
1895 | { |
1896 | struct uart_pmac_port *uap = &pmz_ports[con->index]; |
1897 | unsigned long flags; |
1898 | |
1899 | uart_port_lock_irqsave(&uap->port, &flags); |
1900 | |
1901 | /* Turn of interrupts and enable the transmitter. */ |
1902 | write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB); |
1903 | write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR); |
1904 | |
1905 | uart_console_write(&uap->port, s, count, pmz_console_putchar); |
1906 | |
1907 | /* Restore the values in the registers. */ |
1908 | write_zsreg(uap, R1, uap->curregs[1]); |
1909 | /* Don't disable the transmitter. */ |
1910 | |
1911 | uart_port_unlock_irqrestore(&uap->port, flags); |
1912 | } |
1913 | |
1914 | /* |
1915 | * Setup the serial console |
1916 | */ |
1917 | static int __init pmz_console_setup(struct console *co, char *options) |
1918 | { |
1919 | struct uart_pmac_port *uap; |
1920 | struct uart_port *port; |
1921 | int baud = 38400; |
1922 | int bits = 8; |
1923 | int parity = 'n'; |
1924 | int flow = 'n'; |
1925 | unsigned long pwr_delay; |
1926 | |
1927 | /* |
1928 | * XServe's default to 57600 bps |
1929 | */ |
1930 | if (of_machine_is_compatible("RackMac1,1" ) |
1931 | || of_machine_is_compatible("RackMac1,2" ) |
1932 | || of_machine_is_compatible("MacRISC4" )) |
1933 | baud = 57600; |
1934 | |
1935 | /* |
1936 | * Check whether an invalid uart number has been specified, and |
1937 | * if so, search for the first available port that does have |
1938 | * console support. |
1939 | */ |
1940 | if (co->index >= pmz_ports_count) |
1941 | co->index = 0; |
1942 | uap = &pmz_ports[co->index]; |
1943 | #ifdef CONFIG_PPC_PMAC |
1944 | if (uap->node == NULL) |
1945 | return -ENODEV; |
1946 | #else |
1947 | if (uap->pdev == NULL) |
1948 | return -ENODEV; |
1949 | #endif |
1950 | port = &uap->port; |
1951 | |
1952 | /* |
1953 | * Mark port as beeing a console |
1954 | */ |
1955 | uap->flags |= PMACZILOG_FLAG_IS_CONS; |
1956 | |
1957 | /* |
1958 | * Temporary fix for uart layer who didn't setup the spinlock yet |
1959 | */ |
1960 | spin_lock_init(&port->lock); |
1961 | |
1962 | /* |
1963 | * Enable the hardware |
1964 | */ |
1965 | pwr_delay = __pmz_startup(uap); |
1966 | if (pwr_delay) |
1967 | mdelay(pwr_delay); |
1968 | |
1969 | if (options) |
1970 | uart_parse_options(options, &baud, &parity, &bits, &flow); |
1971 | |
1972 | return uart_set_options(port, co, baud, parity, bits, flow); |
1973 | } |
1974 | |
1975 | static int __init pmz_console_init(void) |
1976 | { |
1977 | /* Probe ports */ |
1978 | pmz_probe(); |
1979 | |
1980 | if (pmz_ports_count == 0) |
1981 | return -ENODEV; |
1982 | |
1983 | /* TODO: Autoprobe console based on OF */ |
1984 | /* pmz_console.index = i; */ |
1985 | register_console(&pmz_console); |
1986 | |
1987 | return 0; |
1988 | |
1989 | } |
1990 | console_initcall(pmz_console_init); |
1991 | #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */ |
1992 | |
1993 | module_init(init_pmz); |
1994 | module_exit(exit_pmz); |
1995 | |