1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* |
3 | * Based on drivers/serial/8250.c by Russell King. |
4 | * |
5 | * Author: Nicolas Pitre |
6 | * Created: Feb 20, 2003 |
7 | * Copyright: (C) 2003 Monta Vista Software, Inc. |
8 | * |
9 | * Note 1: This driver is made separate from the already too overloaded |
10 | * 8250.c because it needs some kirks of its own and that'll make it |
11 | * easier to add DMA support. |
12 | * |
13 | * Note 2: I'm too sick of device allocation policies for serial ports. |
14 | * If someone else wants to request an "official" allocation of major/minor |
15 | * for this driver please be my guest. And don't forget that new hardware |
16 | * to come from Intel might have more than 3 or 4 of those UARTs. Let's |
17 | * hope for a better port registration and dynamic device allocation scheme |
18 | * with the serial core maintainer satisfaction to appear soon. |
19 | */ |
20 | |
21 | |
22 | #include <linux/ioport.h> |
23 | #include <linux/init.h> |
24 | #include <linux/console.h> |
25 | #include <linux/sysrq.h> |
26 | #include <linux/serial.h> |
27 | #include <linux/serial_reg.h> |
28 | #include <linux/circ_buf.h> |
29 | #include <linux/delay.h> |
30 | #include <linux/interrupt.h> |
31 | #include <linux/of.h> |
32 | #include <linux/platform_device.h> |
33 | #include <linux/tty.h> |
34 | #include <linux/tty_flip.h> |
35 | #include <linux/serial_core.h> |
36 | #include <linux/clk.h> |
37 | #include <linux/io.h> |
38 | #include <linux/slab.h> |
39 | |
40 | #define PXA_NAME_LEN 8 |
41 | |
42 | struct uart_pxa_port { |
43 | struct uart_port port; |
44 | unsigned char ier; |
45 | unsigned char lcr; |
46 | unsigned char mcr; |
47 | unsigned int lsr_break_flag; |
48 | struct clk *clk; |
49 | char name[PXA_NAME_LEN]; |
50 | }; |
51 | |
52 | static inline unsigned int serial_in(struct uart_pxa_port *up, int offset) |
53 | { |
54 | offset <<= 2; |
55 | return readl(addr: up->port.membase + offset); |
56 | } |
57 | |
58 | static inline void serial_out(struct uart_pxa_port *up, int offset, int value) |
59 | { |
60 | offset <<= 2; |
61 | writel(val: value, addr: up->port.membase + offset); |
62 | } |
63 | |
64 | static void serial_pxa_enable_ms(struct uart_port *port) |
65 | { |
66 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; |
67 | |
68 | up->ier |= UART_IER_MSI; |
69 | serial_out(up, UART_IER, value: up->ier); |
70 | } |
71 | |
72 | static void serial_pxa_stop_tx(struct uart_port *port) |
73 | { |
74 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; |
75 | |
76 | if (up->ier & UART_IER_THRI) { |
77 | up->ier &= ~UART_IER_THRI; |
78 | serial_out(up, UART_IER, value: up->ier); |
79 | } |
80 | } |
81 | |
82 | static void serial_pxa_stop_rx(struct uart_port *port) |
83 | { |
84 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; |
85 | |
86 | up->ier &= ~UART_IER_RLSI; |
87 | up->port.read_status_mask &= ~UART_LSR_DR; |
88 | serial_out(up, UART_IER, value: up->ier); |
89 | } |
90 | |
91 | static inline void receive_chars(struct uart_pxa_port *up, int *status) |
92 | { |
93 | u8 ch, flag; |
94 | int max_count = 256; |
95 | |
96 | do { |
97 | /* work around Errata #20 according to |
98 | * Intel(R) PXA27x Processor Family |
99 | * Specification Update (May 2005) |
100 | * |
101 | * Step 2 |
102 | * Disable the Reciever Time Out Interrupt via IER[RTOEI] |
103 | */ |
104 | up->ier &= ~UART_IER_RTOIE; |
105 | serial_out(up, UART_IER, value: up->ier); |
106 | |
107 | ch = serial_in(up, UART_RX); |
108 | flag = TTY_NORMAL; |
109 | up->port.icount.rx++; |
110 | |
111 | if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE | |
112 | UART_LSR_FE | UART_LSR_OE))) { |
113 | /* |
114 | * For statistics only |
115 | */ |
116 | if (*status & UART_LSR_BI) { |
117 | *status &= ~(UART_LSR_FE | UART_LSR_PE); |
118 | up->port.icount.brk++; |
119 | /* |
120 | * We do the SysRQ and SAK checking |
121 | * here because otherwise the break |
122 | * may get masked by ignore_status_mask |
123 | * or read_status_mask. |
124 | */ |
125 | if (uart_handle_break(port: &up->port)) |
126 | goto ignore_char; |
127 | } else if (*status & UART_LSR_PE) |
128 | up->port.icount.parity++; |
129 | else if (*status & UART_LSR_FE) |
130 | up->port.icount.frame++; |
131 | if (*status & UART_LSR_OE) |
132 | up->port.icount.overrun++; |
133 | |
134 | /* |
135 | * Mask off conditions which should be ignored. |
136 | */ |
137 | *status &= up->port.read_status_mask; |
138 | |
139 | #ifdef CONFIG_SERIAL_PXA_CONSOLE |
140 | if (up->port.line == up->port.cons->index) { |
141 | /* Recover the break flag from console xmit */ |
142 | *status |= up->lsr_break_flag; |
143 | up->lsr_break_flag = 0; |
144 | } |
145 | #endif |
146 | if (*status & UART_LSR_BI) { |
147 | flag = TTY_BREAK; |
148 | } else if (*status & UART_LSR_PE) |
149 | flag = TTY_PARITY; |
150 | else if (*status & UART_LSR_FE) |
151 | flag = TTY_FRAME; |
152 | } |
153 | |
154 | if (uart_handle_sysrq_char(port: &up->port, ch)) |
155 | goto ignore_char; |
156 | |
157 | uart_insert_char(port: &up->port, status: *status, UART_LSR_OE, ch, flag); |
158 | |
159 | ignore_char: |
160 | *status = serial_in(up, UART_LSR); |
161 | } while ((*status & UART_LSR_DR) && (max_count-- > 0)); |
162 | tty_flip_buffer_push(port: &up->port.state->port); |
163 | |
164 | /* work around Errata #20 according to |
165 | * Intel(R) PXA27x Processor Family |
166 | * Specification Update (May 2005) |
167 | * |
168 | * Step 6: |
169 | * No more data in FIFO: Re-enable RTO interrupt via IER[RTOIE] |
170 | */ |
171 | up->ier |= UART_IER_RTOIE; |
172 | serial_out(up, UART_IER, value: up->ier); |
173 | } |
174 | |
175 | static void transmit_chars(struct uart_pxa_port *up) |
176 | { |
177 | u8 ch; |
178 | |
179 | uart_port_tx_limited(&up->port, ch, up->port.fifosize / 2, |
180 | true, |
181 | serial_out(up, UART_TX, ch), |
182 | ({})); |
183 | } |
184 | |
185 | static void serial_pxa_start_tx(struct uart_port *port) |
186 | { |
187 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; |
188 | |
189 | if (!(up->ier & UART_IER_THRI)) { |
190 | up->ier |= UART_IER_THRI; |
191 | serial_out(up, UART_IER, value: up->ier); |
192 | } |
193 | } |
194 | |
195 | /* should hold up->port.lock */ |
196 | static inline void check_modem_status(struct uart_pxa_port *up) |
197 | { |
198 | int status; |
199 | |
200 | status = serial_in(up, UART_MSR); |
201 | |
202 | if ((status & UART_MSR_ANY_DELTA) == 0) |
203 | return; |
204 | |
205 | if (status & UART_MSR_TERI) |
206 | up->port.icount.rng++; |
207 | if (status & UART_MSR_DDSR) |
208 | up->port.icount.dsr++; |
209 | if (status & UART_MSR_DDCD) |
210 | uart_handle_dcd_change(uport: &up->port, active: status & UART_MSR_DCD); |
211 | if (status & UART_MSR_DCTS) |
212 | uart_handle_cts_change(uport: &up->port, active: status & UART_MSR_CTS); |
213 | |
214 | wake_up_interruptible(&up->port.state->port.delta_msr_wait); |
215 | } |
216 | |
217 | /* |
218 | * This handles the interrupt from one port. |
219 | */ |
220 | static inline irqreturn_t serial_pxa_irq(int irq, void *dev_id) |
221 | { |
222 | struct uart_pxa_port *up = dev_id; |
223 | unsigned int iir, lsr; |
224 | |
225 | iir = serial_in(up, UART_IIR); |
226 | if (iir & UART_IIR_NO_INT) |
227 | return IRQ_NONE; |
228 | uart_port_lock(up: &up->port); |
229 | lsr = serial_in(up, UART_LSR); |
230 | if (lsr & UART_LSR_DR) |
231 | receive_chars(up, status: &lsr); |
232 | check_modem_status(up); |
233 | if (lsr & UART_LSR_THRE) |
234 | transmit_chars(up); |
235 | uart_port_unlock(up: &up->port); |
236 | return IRQ_HANDLED; |
237 | } |
238 | |
239 | static unsigned int serial_pxa_tx_empty(struct uart_port *port) |
240 | { |
241 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; |
242 | unsigned long flags; |
243 | unsigned int ret; |
244 | |
245 | uart_port_lock_irqsave(up: &up->port, flags: &flags); |
246 | ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; |
247 | uart_port_unlock_irqrestore(up: &up->port, flags); |
248 | |
249 | return ret; |
250 | } |
251 | |
252 | static unsigned int serial_pxa_get_mctrl(struct uart_port *port) |
253 | { |
254 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; |
255 | unsigned char status; |
256 | unsigned int ret; |
257 | |
258 | status = serial_in(up, UART_MSR); |
259 | |
260 | ret = 0; |
261 | if (status & UART_MSR_DCD) |
262 | ret |= TIOCM_CAR; |
263 | if (status & UART_MSR_RI) |
264 | ret |= TIOCM_RNG; |
265 | if (status & UART_MSR_DSR) |
266 | ret |= TIOCM_DSR; |
267 | if (status & UART_MSR_CTS) |
268 | ret |= TIOCM_CTS; |
269 | return ret; |
270 | } |
271 | |
272 | static void serial_pxa_set_mctrl(struct uart_port *port, unsigned int mctrl) |
273 | { |
274 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; |
275 | unsigned char mcr = 0; |
276 | |
277 | if (mctrl & TIOCM_RTS) |
278 | mcr |= UART_MCR_RTS; |
279 | if (mctrl & TIOCM_DTR) |
280 | mcr |= UART_MCR_DTR; |
281 | if (mctrl & TIOCM_OUT1) |
282 | mcr |= UART_MCR_OUT1; |
283 | if (mctrl & TIOCM_OUT2) |
284 | mcr |= UART_MCR_OUT2; |
285 | if (mctrl & TIOCM_LOOP) |
286 | mcr |= UART_MCR_LOOP; |
287 | |
288 | mcr |= up->mcr; |
289 | |
290 | serial_out(up, UART_MCR, value: mcr); |
291 | } |
292 | |
293 | static void serial_pxa_break_ctl(struct uart_port *port, int break_state) |
294 | { |
295 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; |
296 | unsigned long flags; |
297 | |
298 | uart_port_lock_irqsave(up: &up->port, flags: &flags); |
299 | if (break_state == -1) |
300 | up->lcr |= UART_LCR_SBC; |
301 | else |
302 | up->lcr &= ~UART_LCR_SBC; |
303 | serial_out(up, UART_LCR, value: up->lcr); |
304 | uart_port_unlock_irqrestore(up: &up->port, flags); |
305 | } |
306 | |
307 | static int serial_pxa_startup(struct uart_port *port) |
308 | { |
309 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; |
310 | unsigned long flags; |
311 | int retval; |
312 | |
313 | if (port->line == 3) /* HWUART */ |
314 | up->mcr |= UART_MCR_AFE; |
315 | else |
316 | up->mcr = 0; |
317 | |
318 | up->port.uartclk = clk_get_rate(clk: up->clk); |
319 | |
320 | /* |
321 | * Allocate the IRQ |
322 | */ |
323 | retval = request_irq(irq: up->port.irq, handler: serial_pxa_irq, flags: 0, name: up->name, dev: up); |
324 | if (retval) |
325 | return retval; |
326 | |
327 | /* |
328 | * Clear the FIFO buffers and disable them. |
329 | * (they will be reenabled in set_termios()) |
330 | */ |
331 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); |
332 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | |
333 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); |
334 | serial_out(up, UART_FCR, value: 0); |
335 | |
336 | /* |
337 | * Clear the interrupt registers. |
338 | */ |
339 | (void) serial_in(up, UART_LSR); |
340 | (void) serial_in(up, UART_RX); |
341 | (void) serial_in(up, UART_IIR); |
342 | (void) serial_in(up, UART_MSR); |
343 | |
344 | /* |
345 | * Now, initialize the UART |
346 | */ |
347 | serial_out(up, UART_LCR, UART_LCR_WLEN8); |
348 | |
349 | uart_port_lock_irqsave(up: &up->port, flags: &flags); |
350 | up->port.mctrl |= TIOCM_OUT2; |
351 | serial_pxa_set_mctrl(port: &up->port, mctrl: up->port.mctrl); |
352 | uart_port_unlock_irqrestore(up: &up->port, flags); |
353 | |
354 | /* |
355 | * Finally, enable interrupts. Note: Modem status interrupts |
356 | * are set via set_termios(), which will be occurring imminently |
357 | * anyway, so we don't enable them here. |
358 | */ |
359 | up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE | UART_IER_UUE; |
360 | serial_out(up, UART_IER, value: up->ier); |
361 | |
362 | /* |
363 | * And clear the interrupt registers again for luck. |
364 | */ |
365 | (void) serial_in(up, UART_LSR); |
366 | (void) serial_in(up, UART_RX); |
367 | (void) serial_in(up, UART_IIR); |
368 | (void) serial_in(up, UART_MSR); |
369 | |
370 | return 0; |
371 | } |
372 | |
373 | static void serial_pxa_shutdown(struct uart_port *port) |
374 | { |
375 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; |
376 | unsigned long flags; |
377 | |
378 | free_irq(up->port.irq, up); |
379 | |
380 | /* |
381 | * Disable interrupts from this port |
382 | */ |
383 | up->ier = 0; |
384 | serial_out(up, UART_IER, value: 0); |
385 | |
386 | uart_port_lock_irqsave(up: &up->port, flags: &flags); |
387 | up->port.mctrl &= ~TIOCM_OUT2; |
388 | serial_pxa_set_mctrl(port: &up->port, mctrl: up->port.mctrl); |
389 | uart_port_unlock_irqrestore(up: &up->port, flags); |
390 | |
391 | /* |
392 | * Disable break condition and FIFOs |
393 | */ |
394 | serial_out(up, UART_LCR, value: serial_in(up, UART_LCR) & ~UART_LCR_SBC); |
395 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | |
396 | UART_FCR_CLEAR_RCVR | |
397 | UART_FCR_CLEAR_XMIT); |
398 | serial_out(up, UART_FCR, value: 0); |
399 | } |
400 | |
401 | static void |
402 | serial_pxa_set_termios(struct uart_port *port, struct ktermios *termios, |
403 | const struct ktermios *old) |
404 | { |
405 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; |
406 | unsigned char cval, fcr = 0; |
407 | unsigned long flags; |
408 | unsigned int baud, quot; |
409 | unsigned int dll; |
410 | |
411 | cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag)); |
412 | |
413 | if (termios->c_cflag & CSTOPB) |
414 | cval |= UART_LCR_STOP; |
415 | if (termios->c_cflag & PARENB) |
416 | cval |= UART_LCR_PARITY; |
417 | if (!(termios->c_cflag & PARODD)) |
418 | cval |= UART_LCR_EPAR; |
419 | |
420 | /* |
421 | * Ask the core to calculate the divisor for us. |
422 | */ |
423 | baud = uart_get_baud_rate(port, termios, old, min: 0, max: port->uartclk/16); |
424 | quot = uart_get_divisor(port, baud); |
425 | |
426 | if ((up->port.uartclk / quot) < (2400 * 16)) |
427 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR1; |
428 | else if ((up->port.uartclk / quot) < (230400 * 16)) |
429 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR8; |
430 | else |
431 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR32; |
432 | |
433 | /* |
434 | * Ok, we're now changing the port state. Do it with |
435 | * interrupts disabled. |
436 | */ |
437 | uart_port_lock_irqsave(up: &up->port, flags: &flags); |
438 | |
439 | /* |
440 | * Ensure the port will be enabled. |
441 | * This is required especially for serial console. |
442 | */ |
443 | up->ier |= UART_IER_UUE; |
444 | |
445 | /* |
446 | * Update the per-port timeout. |
447 | */ |
448 | uart_update_timeout(port, cflag: termios->c_cflag, baud); |
449 | |
450 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; |
451 | if (termios->c_iflag & INPCK) |
452 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; |
453 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
454 | up->port.read_status_mask |= UART_LSR_BI; |
455 | |
456 | /* |
457 | * Characters to ignore |
458 | */ |
459 | up->port.ignore_status_mask = 0; |
460 | if (termios->c_iflag & IGNPAR) |
461 | up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; |
462 | if (termios->c_iflag & IGNBRK) { |
463 | up->port.ignore_status_mask |= UART_LSR_BI; |
464 | /* |
465 | * If we're ignoring parity and break indicators, |
466 | * ignore overruns too (for real raw support). |
467 | */ |
468 | if (termios->c_iflag & IGNPAR) |
469 | up->port.ignore_status_mask |= UART_LSR_OE; |
470 | } |
471 | |
472 | /* |
473 | * ignore all characters if CREAD is not set |
474 | */ |
475 | if ((termios->c_cflag & CREAD) == 0) |
476 | up->port.ignore_status_mask |= UART_LSR_DR; |
477 | |
478 | /* |
479 | * CTS flow control flag and modem status interrupts |
480 | */ |
481 | up->ier &= ~UART_IER_MSI; |
482 | if (UART_ENABLE_MS(&up->port, termios->c_cflag)) |
483 | up->ier |= UART_IER_MSI; |
484 | |
485 | serial_out(up, UART_IER, value: up->ier); |
486 | |
487 | if (termios->c_cflag & CRTSCTS) |
488 | up->mcr |= UART_MCR_AFE; |
489 | else |
490 | up->mcr &= ~UART_MCR_AFE; |
491 | |
492 | serial_out(up, UART_LCR, value: cval | UART_LCR_DLAB); /* set DLAB */ |
493 | serial_out(up, UART_DLL, value: quot & 0xff); /* LS of divisor */ |
494 | |
495 | /* |
496 | * work around Errata #75 according to Intel(R) PXA27x Processor Family |
497 | * Specification Update (Nov 2005) |
498 | */ |
499 | dll = serial_in(up, UART_DLL); |
500 | WARN_ON(dll != (quot & 0xff)); |
501 | |
502 | serial_out(up, UART_DLM, value: quot >> 8); /* MS of divisor */ |
503 | serial_out(up, UART_LCR, value: cval); /* reset DLAB */ |
504 | up->lcr = cval; /* Save LCR */ |
505 | serial_pxa_set_mctrl(port: &up->port, mctrl: up->port.mctrl); |
506 | serial_out(up, UART_FCR, value: fcr); |
507 | uart_port_unlock_irqrestore(up: &up->port, flags); |
508 | } |
509 | |
510 | static void |
511 | serial_pxa_pm(struct uart_port *port, unsigned int state, |
512 | unsigned int oldstate) |
513 | { |
514 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; |
515 | |
516 | if (!state) |
517 | clk_prepare_enable(clk: up->clk); |
518 | else |
519 | clk_disable_unprepare(clk: up->clk); |
520 | } |
521 | |
522 | static void serial_pxa_release_port(struct uart_port *port) |
523 | { |
524 | } |
525 | |
526 | static int serial_pxa_request_port(struct uart_port *port) |
527 | { |
528 | return 0; |
529 | } |
530 | |
531 | static void serial_pxa_config_port(struct uart_port *port, int flags) |
532 | { |
533 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; |
534 | up->port.type = PORT_PXA; |
535 | } |
536 | |
537 | static int |
538 | serial_pxa_verify_port(struct uart_port *port, struct serial_struct *ser) |
539 | { |
540 | /* we don't want the core code to modify any port params */ |
541 | return -EINVAL; |
542 | } |
543 | |
544 | static const char * |
545 | serial_pxa_type(struct uart_port *port) |
546 | { |
547 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; |
548 | return up->name; |
549 | } |
550 | |
551 | static struct uart_pxa_port *serial_pxa_ports[4]; |
552 | static struct uart_driver serial_pxa_reg; |
553 | |
554 | #ifdef CONFIG_SERIAL_PXA_CONSOLE |
555 | |
556 | /* |
557 | * Wait for transmitter & holding register to empty |
558 | */ |
559 | static void wait_for_xmitr(struct uart_pxa_port *up) |
560 | { |
561 | unsigned int status, tmout = 10000; |
562 | |
563 | /* Wait up to 10ms for the character(s) to be sent. */ |
564 | do { |
565 | status = serial_in(up, UART_LSR); |
566 | |
567 | if (status & UART_LSR_BI) |
568 | up->lsr_break_flag = UART_LSR_BI; |
569 | |
570 | if (--tmout == 0) |
571 | break; |
572 | udelay(1); |
573 | } while (!uart_lsr_tx_empty(status)); |
574 | |
575 | /* Wait up to 1s for flow control if necessary */ |
576 | if (up->port.flags & UPF_CONS_FLOW) { |
577 | tmout = 1000000; |
578 | while (--tmout && |
579 | ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0)) |
580 | udelay(1); |
581 | } |
582 | } |
583 | |
584 | static void serial_pxa_console_putchar(struct uart_port *port, unsigned char ch) |
585 | { |
586 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; |
587 | |
588 | wait_for_xmitr(up); |
589 | serial_out(up, UART_TX, ch); |
590 | } |
591 | |
592 | /* |
593 | * Print a string to the serial port trying not to disturb |
594 | * any possible real use of the port... |
595 | * |
596 | * The console_lock must be held when we get here. |
597 | */ |
598 | static void |
599 | serial_pxa_console_write(struct console *co, const char *s, unsigned int count) |
600 | { |
601 | struct uart_pxa_port *up = serial_pxa_ports[co->index]; |
602 | unsigned int ier; |
603 | unsigned long flags; |
604 | int locked = 1; |
605 | |
606 | clk_enable(up->clk); |
607 | local_irq_save(flags); |
608 | if (up->port.sysrq) |
609 | locked = 0; |
610 | else if (oops_in_progress) |
611 | locked = uart_port_trylock(&up->port); |
612 | else |
613 | uart_port_lock(&up->port); |
614 | |
615 | /* |
616 | * First save the IER then disable the interrupts |
617 | */ |
618 | ier = serial_in(up, UART_IER); |
619 | serial_out(up, UART_IER, UART_IER_UUE); |
620 | |
621 | uart_console_write(&up->port, s, count, serial_pxa_console_putchar); |
622 | |
623 | /* |
624 | * Finally, wait for transmitter to become empty |
625 | * and restore the IER |
626 | */ |
627 | wait_for_xmitr(up); |
628 | serial_out(up, UART_IER, ier); |
629 | |
630 | if (locked) |
631 | uart_port_unlock(&up->port); |
632 | local_irq_restore(flags); |
633 | clk_disable(up->clk); |
634 | |
635 | } |
636 | |
637 | #ifdef CONFIG_CONSOLE_POLL |
638 | /* |
639 | * Console polling routines for writing and reading from the uart while |
640 | * in an interrupt or debug context. |
641 | */ |
642 | |
643 | static int serial_pxa_get_poll_char(struct uart_port *port) |
644 | { |
645 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; |
646 | unsigned char lsr = serial_in(up, UART_LSR); |
647 | |
648 | while (!(lsr & UART_LSR_DR)) |
649 | lsr = serial_in(up, UART_LSR); |
650 | |
651 | return serial_in(up, UART_RX); |
652 | } |
653 | |
654 | |
655 | static void serial_pxa_put_poll_char(struct uart_port *port, |
656 | unsigned char c) |
657 | { |
658 | unsigned int ier; |
659 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; |
660 | |
661 | /* |
662 | * First save the IER then disable the interrupts |
663 | */ |
664 | ier = serial_in(up, UART_IER); |
665 | serial_out(up, UART_IER, UART_IER_UUE); |
666 | |
667 | wait_for_xmitr(up); |
668 | /* |
669 | * Send the character out. |
670 | */ |
671 | serial_out(up, UART_TX, c); |
672 | |
673 | /* |
674 | * Finally, wait for transmitter to become empty |
675 | * and restore the IER |
676 | */ |
677 | wait_for_xmitr(up); |
678 | serial_out(up, UART_IER, ier); |
679 | } |
680 | |
681 | #endif /* CONFIG_CONSOLE_POLL */ |
682 | |
683 | static int __init |
684 | serial_pxa_console_setup(struct console *co, char *options) |
685 | { |
686 | struct uart_pxa_port *up; |
687 | int baud = 9600; |
688 | int bits = 8; |
689 | int parity = 'n'; |
690 | int flow = 'n'; |
691 | |
692 | if (co->index == -1 || co->index >= serial_pxa_reg.nr) |
693 | co->index = 0; |
694 | up = serial_pxa_ports[co->index]; |
695 | if (!up) |
696 | return -ENODEV; |
697 | |
698 | if (options) |
699 | uart_parse_options(options, &baud, &parity, &bits, &flow); |
700 | |
701 | return uart_set_options(&up->port, co, baud, parity, bits, flow); |
702 | } |
703 | |
704 | static struct console serial_pxa_console = { |
705 | .name = "ttyS" , |
706 | .write = serial_pxa_console_write, |
707 | .device = uart_console_device, |
708 | .setup = serial_pxa_console_setup, |
709 | .flags = CON_PRINTBUFFER, |
710 | .index = -1, |
711 | .data = &serial_pxa_reg, |
712 | }; |
713 | |
714 | #define PXA_CONSOLE &serial_pxa_console |
715 | #else |
716 | #define PXA_CONSOLE NULL |
717 | #endif |
718 | |
719 | static const struct uart_ops serial_pxa_pops = { |
720 | .tx_empty = serial_pxa_tx_empty, |
721 | .set_mctrl = serial_pxa_set_mctrl, |
722 | .get_mctrl = serial_pxa_get_mctrl, |
723 | .stop_tx = serial_pxa_stop_tx, |
724 | .start_tx = serial_pxa_start_tx, |
725 | .stop_rx = serial_pxa_stop_rx, |
726 | .enable_ms = serial_pxa_enable_ms, |
727 | .break_ctl = serial_pxa_break_ctl, |
728 | .startup = serial_pxa_startup, |
729 | .shutdown = serial_pxa_shutdown, |
730 | .set_termios = serial_pxa_set_termios, |
731 | .pm = serial_pxa_pm, |
732 | .type = serial_pxa_type, |
733 | .release_port = serial_pxa_release_port, |
734 | .request_port = serial_pxa_request_port, |
735 | .config_port = serial_pxa_config_port, |
736 | .verify_port = serial_pxa_verify_port, |
737 | #if defined(CONFIG_CONSOLE_POLL) && defined(CONFIG_SERIAL_PXA_CONSOLE) |
738 | .poll_get_char = serial_pxa_get_poll_char, |
739 | .poll_put_char = serial_pxa_put_poll_char, |
740 | #endif |
741 | }; |
742 | |
743 | static struct uart_driver serial_pxa_reg = { |
744 | .owner = THIS_MODULE, |
745 | .driver_name = "PXA serial" , |
746 | .dev_name = "ttyS" , |
747 | .major = TTY_MAJOR, |
748 | .minor = 64, |
749 | .nr = 4, |
750 | .cons = PXA_CONSOLE, |
751 | }; |
752 | |
753 | #ifdef CONFIG_PM |
754 | static int serial_pxa_suspend(struct device *dev) |
755 | { |
756 | struct uart_pxa_port *sport = dev_get_drvdata(dev); |
757 | |
758 | if (sport) |
759 | uart_suspend_port(reg: &serial_pxa_reg, port: &sport->port); |
760 | |
761 | return 0; |
762 | } |
763 | |
764 | static int serial_pxa_resume(struct device *dev) |
765 | { |
766 | struct uart_pxa_port *sport = dev_get_drvdata(dev); |
767 | |
768 | if (sport) |
769 | uart_resume_port(reg: &serial_pxa_reg, port: &sport->port); |
770 | |
771 | return 0; |
772 | } |
773 | |
774 | static const struct dev_pm_ops serial_pxa_pm_ops = { |
775 | .suspend = serial_pxa_suspend, |
776 | .resume = serial_pxa_resume, |
777 | }; |
778 | #endif |
779 | |
780 | static const struct of_device_id serial_pxa_dt_ids[] = { |
781 | { .compatible = "mrvl,pxa-uart" , }, |
782 | { .compatible = "mrvl,mmp-uart" , }, |
783 | {} |
784 | }; |
785 | |
786 | static int serial_pxa_probe_dt(struct platform_device *pdev, |
787 | struct uart_pxa_port *sport) |
788 | { |
789 | struct device_node *np = pdev->dev.of_node; |
790 | int ret; |
791 | |
792 | if (!np) |
793 | return 1; |
794 | |
795 | ret = of_alias_get_id(np, stem: "serial" ); |
796 | if (ret < 0) { |
797 | dev_err(&pdev->dev, "failed to get alias id, errno %d\n" , ret); |
798 | return ret; |
799 | } |
800 | sport->port.line = ret; |
801 | return 0; |
802 | } |
803 | |
804 | static int serial_pxa_probe(struct platform_device *dev) |
805 | { |
806 | struct uart_pxa_port *sport; |
807 | struct resource *mmres; |
808 | int ret; |
809 | int irq; |
810 | |
811 | mmres = platform_get_resource(dev, IORESOURCE_MEM, 0); |
812 | if (!mmres) |
813 | return -ENODEV; |
814 | |
815 | irq = platform_get_irq(dev, 0); |
816 | if (irq < 0) |
817 | return irq; |
818 | |
819 | sport = kzalloc(size: sizeof(struct uart_pxa_port), GFP_KERNEL); |
820 | if (!sport) |
821 | return -ENOMEM; |
822 | |
823 | sport->clk = clk_get(dev: &dev->dev, NULL); |
824 | if (IS_ERR(ptr: sport->clk)) { |
825 | ret = PTR_ERR(ptr: sport->clk); |
826 | goto err_free; |
827 | } |
828 | |
829 | ret = clk_prepare(clk: sport->clk); |
830 | if (ret) { |
831 | clk_put(clk: sport->clk); |
832 | goto err_free; |
833 | } |
834 | |
835 | sport->port.type = PORT_PXA; |
836 | sport->port.iotype = UPIO_MEM; |
837 | sport->port.mapbase = mmres->start; |
838 | sport->port.irq = irq; |
839 | sport->port.fifosize = 64; |
840 | sport->port.ops = &serial_pxa_pops; |
841 | sport->port.dev = &dev->dev; |
842 | sport->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF; |
843 | sport->port.uartclk = clk_get_rate(clk: sport->clk); |
844 | sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PXA_CONSOLE); |
845 | |
846 | ret = serial_pxa_probe_dt(pdev: dev, sport); |
847 | if (ret > 0) |
848 | sport->port.line = dev->id; |
849 | else if (ret < 0) |
850 | goto err_clk; |
851 | if (sport->port.line >= ARRAY_SIZE(serial_pxa_ports)) { |
852 | dev_err(&dev->dev, "serial%d out of range\n" , sport->port.line); |
853 | ret = -EINVAL; |
854 | goto err_clk; |
855 | } |
856 | snprintf(buf: sport->name, PXA_NAME_LEN - 1, fmt: "UART%d" , sport->port.line + 1); |
857 | |
858 | sport->port.membase = ioremap(offset: mmres->start, size: resource_size(res: mmres)); |
859 | if (!sport->port.membase) { |
860 | ret = -ENOMEM; |
861 | goto err_clk; |
862 | } |
863 | |
864 | serial_pxa_ports[sport->port.line] = sport; |
865 | |
866 | uart_add_one_port(reg: &serial_pxa_reg, port: &sport->port); |
867 | platform_set_drvdata(pdev: dev, data: sport); |
868 | |
869 | return 0; |
870 | |
871 | err_clk: |
872 | clk_unprepare(clk: sport->clk); |
873 | clk_put(clk: sport->clk); |
874 | err_free: |
875 | kfree(objp: sport); |
876 | return ret; |
877 | } |
878 | |
879 | static struct platform_driver serial_pxa_driver = { |
880 | .probe = serial_pxa_probe, |
881 | |
882 | .driver = { |
883 | .name = "pxa2xx-uart" , |
884 | #ifdef CONFIG_PM |
885 | .pm = &serial_pxa_pm_ops, |
886 | #endif |
887 | .suppress_bind_attrs = true, |
888 | .of_match_table = serial_pxa_dt_ids, |
889 | }, |
890 | }; |
891 | |
892 | |
893 | /* 8250 driver for PXA serial ports should be used */ |
894 | static int __init serial_pxa_init(void) |
895 | { |
896 | int ret; |
897 | |
898 | ret = uart_register_driver(uart: &serial_pxa_reg); |
899 | if (ret != 0) |
900 | return ret; |
901 | |
902 | ret = platform_driver_register(&serial_pxa_driver); |
903 | if (ret != 0) |
904 | uart_unregister_driver(uart: &serial_pxa_reg); |
905 | |
906 | return ret; |
907 | } |
908 | device_initcall(serial_pxa_init); |
909 | |