1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Driver for Comtrol RocketPort EXPRESS/INFINITY cards |
4 | * |
5 | * Copyright (C) 2012 Kevin Cernekee <cernekee@gmail.com> |
6 | * |
7 | * Inspired by, and loosely based on: |
8 | * |
9 | * ar933x_uart.c |
10 | * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> |
11 | * |
12 | * rocketport_infinity_express-linux-1.20.tar.gz |
13 | * Copyright (C) 2004-2011 Comtrol, Inc. |
14 | */ |
15 | |
16 | #include <linux/bitops.h> |
17 | #include <linux/compiler.h> |
18 | #include <linux/completion.h> |
19 | #include <linux/console.h> |
20 | #include <linux/delay.h> |
21 | #include <linux/firmware.h> |
22 | #include <linux/init.h> |
23 | #include <linux/io.h> |
24 | #include <linux/ioport.h> |
25 | #include <linux/irq.h> |
26 | #include <linux/kernel.h> |
27 | #include <linux/log2.h> |
28 | #include <linux/module.h> |
29 | #include <linux/pci.h> |
30 | #include <linux/serial.h> |
31 | #include <linux/serial_core.h> |
32 | #include <linux/slab.h> |
33 | #include <linux/sysrq.h> |
34 | #include <linux/tty.h> |
35 | #include <linux/tty_flip.h> |
36 | #include <linux/types.h> |
37 | |
38 | #define DRV_NAME "rp2" |
39 | |
40 | #define RP2_FW_NAME "rp2.fw" |
41 | #define RP2_UCODE_BYTES 0x3f |
42 | |
43 | #define PORTS_PER_ASIC 16 |
44 | #define ALL_PORTS_MASK (BIT(PORTS_PER_ASIC) - 1) |
45 | |
46 | #define UART_CLOCK 44236800 |
47 | #define DEFAULT_BAUD_DIV (UART_CLOCK / (9600 * 16)) |
48 | #define FIFO_SIZE 512 |
49 | |
50 | /* BAR0 registers */ |
51 | #define RP2_FPGA_CTL0 0x110 |
52 | #define RP2_FPGA_CTL1 0x11c |
53 | #define RP2_IRQ_MASK 0x1ec |
54 | #define RP2_IRQ_MASK_EN_m BIT(0) |
55 | #define RP2_IRQ_STATUS 0x1f0 |
56 | |
57 | /* BAR1 registers */ |
58 | #define RP2_ASIC_SPACING 0x1000 |
59 | #define RP2_ASIC_OFFSET(i) ((i) << ilog2(RP2_ASIC_SPACING)) |
60 | |
61 | #define RP2_PORT_BASE 0x000 |
62 | #define RP2_PORT_SPACING 0x040 |
63 | |
64 | #define RP2_UCODE_BASE 0x400 |
65 | #define RP2_UCODE_SPACING 0x80 |
66 | |
67 | #define RP2_CLK_PRESCALER 0xc00 |
68 | #define RP2_CH_IRQ_STAT 0xc04 |
69 | #define RP2_CH_IRQ_MASK 0xc08 |
70 | #define RP2_ASIC_IRQ 0xd00 |
71 | #define RP2_ASIC_IRQ_EN_m BIT(20) |
72 | #define RP2_GLOBAL_CMD 0xd0c |
73 | #define RP2_ASIC_CFG 0xd04 |
74 | |
75 | /* port registers */ |
76 | #define RP2_DATA_DWORD 0x000 |
77 | |
78 | #define RP2_DATA_BYTE 0x008 |
79 | #define RP2_DATA_BYTE_ERR_PARITY_m BIT(8) |
80 | #define RP2_DATA_BYTE_ERR_OVERRUN_m BIT(9) |
81 | #define RP2_DATA_BYTE_ERR_FRAMING_m BIT(10) |
82 | #define RP2_DATA_BYTE_BREAK_m BIT(11) |
83 | |
84 | /* This lets uart_insert_char() drop bytes received on a !CREAD port */ |
85 | #define RP2_DUMMY_READ BIT(16) |
86 | |
87 | #define RP2_DATA_BYTE_EXCEPTION_MASK (RP2_DATA_BYTE_ERR_PARITY_m | \ |
88 | RP2_DATA_BYTE_ERR_OVERRUN_m | \ |
89 | RP2_DATA_BYTE_ERR_FRAMING_m | \ |
90 | RP2_DATA_BYTE_BREAK_m) |
91 | |
92 | #define RP2_RX_FIFO_COUNT 0x00c |
93 | #define RP2_TX_FIFO_COUNT 0x00e |
94 | |
95 | #define RP2_CHAN_STAT 0x010 |
96 | #define RP2_CHAN_STAT_RXDATA_m BIT(0) |
97 | #define RP2_CHAN_STAT_DCD_m BIT(3) |
98 | #define RP2_CHAN_STAT_DSR_m BIT(4) |
99 | #define RP2_CHAN_STAT_CTS_m BIT(5) |
100 | #define RP2_CHAN_STAT_RI_m BIT(6) |
101 | #define RP2_CHAN_STAT_OVERRUN_m BIT(13) |
102 | #define RP2_CHAN_STAT_DSR_CHANGED_m BIT(16) |
103 | #define RP2_CHAN_STAT_CTS_CHANGED_m BIT(17) |
104 | #define RP2_CHAN_STAT_CD_CHANGED_m BIT(18) |
105 | #define RP2_CHAN_STAT_RI_CHANGED_m BIT(22) |
106 | #define RP2_CHAN_STAT_TXEMPTY_m BIT(25) |
107 | |
108 | #define RP2_CHAN_STAT_MS_CHANGED_MASK (RP2_CHAN_STAT_DSR_CHANGED_m | \ |
109 | RP2_CHAN_STAT_CTS_CHANGED_m | \ |
110 | RP2_CHAN_STAT_CD_CHANGED_m | \ |
111 | RP2_CHAN_STAT_RI_CHANGED_m) |
112 | |
113 | #define RP2_TXRX_CTL 0x014 |
114 | #define RP2_TXRX_CTL_MSRIRQ_m BIT(0) |
115 | #define RP2_TXRX_CTL_RXIRQ_m BIT(2) |
116 | #define RP2_TXRX_CTL_RX_TRIG_s 3 |
117 | #define RP2_TXRX_CTL_RX_TRIG_m (0x3 << RP2_TXRX_CTL_RX_TRIG_s) |
118 | #define RP2_TXRX_CTL_RX_TRIG_1 (0x1 << RP2_TXRX_CTL_RX_TRIG_s) |
119 | #define RP2_TXRX_CTL_RX_TRIG_256 (0x2 << RP2_TXRX_CTL_RX_TRIG_s) |
120 | #define RP2_TXRX_CTL_RX_TRIG_448 (0x3 << RP2_TXRX_CTL_RX_TRIG_s) |
121 | #define RP2_TXRX_CTL_RX_EN_m BIT(5) |
122 | #define RP2_TXRX_CTL_RTSFLOW_m BIT(6) |
123 | #define RP2_TXRX_CTL_DTRFLOW_m BIT(7) |
124 | #define RP2_TXRX_CTL_TX_TRIG_s 16 |
125 | #define RP2_TXRX_CTL_TX_TRIG_m (0x3 << RP2_TXRX_CTL_RX_TRIG_s) |
126 | #define RP2_TXRX_CTL_DSRFLOW_m BIT(18) |
127 | #define RP2_TXRX_CTL_TXIRQ_m BIT(19) |
128 | #define RP2_TXRX_CTL_CTSFLOW_m BIT(23) |
129 | #define RP2_TXRX_CTL_TX_EN_m BIT(24) |
130 | #define RP2_TXRX_CTL_RTS_m BIT(25) |
131 | #define RP2_TXRX_CTL_DTR_m BIT(26) |
132 | #define RP2_TXRX_CTL_LOOP_m BIT(27) |
133 | #define RP2_TXRX_CTL_BREAK_m BIT(28) |
134 | #define RP2_TXRX_CTL_CMSPAR_m BIT(29) |
135 | #define RP2_TXRX_CTL_nPARODD_m BIT(30) |
136 | #define RP2_TXRX_CTL_PARENB_m BIT(31) |
137 | |
138 | #define RP2_UART_CTL 0x018 |
139 | #define RP2_UART_CTL_MODE_s 0 |
140 | #define RP2_UART_CTL_MODE_m (0x7 << RP2_UART_CTL_MODE_s) |
141 | #define RP2_UART_CTL_MODE_rs232 (0x1 << RP2_UART_CTL_MODE_s) |
142 | #define RP2_UART_CTL_FLUSH_RX_m BIT(3) |
143 | #define RP2_UART_CTL_FLUSH_TX_m BIT(4) |
144 | #define RP2_UART_CTL_RESET_CH_m BIT(5) |
145 | #define RP2_UART_CTL_XMIT_EN_m BIT(6) |
146 | #define RP2_UART_CTL_DATABITS_s 8 |
147 | #define RP2_UART_CTL_DATABITS_m (0x3 << RP2_UART_CTL_DATABITS_s) |
148 | #define RP2_UART_CTL_DATABITS_8 (0x3 << RP2_UART_CTL_DATABITS_s) |
149 | #define RP2_UART_CTL_DATABITS_7 (0x2 << RP2_UART_CTL_DATABITS_s) |
150 | #define RP2_UART_CTL_DATABITS_6 (0x1 << RP2_UART_CTL_DATABITS_s) |
151 | #define RP2_UART_CTL_DATABITS_5 (0x0 << RP2_UART_CTL_DATABITS_s) |
152 | #define RP2_UART_CTL_STOPBITS_m BIT(10) |
153 | |
154 | #define RP2_BAUD 0x01c |
155 | |
156 | /* ucode registers */ |
157 | #define RP2_TX_SWFLOW 0x02 |
158 | #define RP2_TX_SWFLOW_ena 0x81 |
159 | #define RP2_TX_SWFLOW_dis 0x9d |
160 | |
161 | #define RP2_RX_SWFLOW 0x0c |
162 | #define RP2_RX_SWFLOW_ena 0x81 |
163 | #define RP2_RX_SWFLOW_dis 0x8d |
164 | |
165 | #define RP2_RX_FIFO 0x37 |
166 | #define RP2_RX_FIFO_ena 0x08 |
167 | #define RP2_RX_FIFO_dis 0x81 |
168 | |
169 | static struct uart_driver rp2_uart_driver = { |
170 | .owner = THIS_MODULE, |
171 | .driver_name = DRV_NAME, |
172 | .dev_name = "ttyRP" , |
173 | .nr = CONFIG_SERIAL_RP2_NR_UARTS, |
174 | }; |
175 | |
176 | struct rp2_card; |
177 | |
178 | struct rp2_uart_port { |
179 | struct uart_port port; |
180 | int idx; |
181 | int ignore_rx; |
182 | struct rp2_card *card; |
183 | void __iomem *asic_base; |
184 | void __iomem *base; |
185 | void __iomem *ucode; |
186 | }; |
187 | |
188 | struct rp2_card { |
189 | struct pci_dev *pdev; |
190 | struct rp2_uart_port *ports; |
191 | int n_ports; |
192 | int initialized_ports; |
193 | int minor_start; |
194 | int smpte; |
195 | void __iomem *bar0; |
196 | void __iomem *bar1; |
197 | spinlock_t card_lock; |
198 | }; |
199 | |
200 | #define RP_ID(prod) PCI_VDEVICE(RP, (prod)) |
201 | #define RP_CAP(ports, smpte) (((ports) << 8) | ((smpte) << 0)) |
202 | |
203 | static inline void rp2_decode_cap(const struct pci_device_id *id, |
204 | int *ports, int *smpte) |
205 | { |
206 | *ports = id->driver_data >> 8; |
207 | *smpte = id->driver_data & 0xff; |
208 | } |
209 | |
210 | static DEFINE_SPINLOCK(rp2_minor_lock); |
211 | static int rp2_minor_next; |
212 | |
213 | static int rp2_alloc_ports(int n_ports) |
214 | { |
215 | int ret = -ENOSPC; |
216 | |
217 | spin_lock(lock: &rp2_minor_lock); |
218 | if (rp2_minor_next + n_ports <= CONFIG_SERIAL_RP2_NR_UARTS) { |
219 | /* sorry, no support for hot unplugging individual cards */ |
220 | ret = rp2_minor_next; |
221 | rp2_minor_next += n_ports; |
222 | } |
223 | spin_unlock(lock: &rp2_minor_lock); |
224 | |
225 | return ret; |
226 | } |
227 | |
228 | static inline struct rp2_uart_port *port_to_up(struct uart_port *port) |
229 | { |
230 | return container_of(port, struct rp2_uart_port, port); |
231 | } |
232 | |
233 | static void rp2_rmw(struct rp2_uart_port *up, int reg, |
234 | u32 clr_bits, u32 set_bits) |
235 | { |
236 | u32 tmp = readl(addr: up->base + reg); |
237 | tmp &= ~clr_bits; |
238 | tmp |= set_bits; |
239 | writel(val: tmp, addr: up->base + reg); |
240 | } |
241 | |
242 | static void rp2_rmw_clr(struct rp2_uart_port *up, int reg, u32 val) |
243 | { |
244 | rp2_rmw(up, reg, clr_bits: val, set_bits: 0); |
245 | } |
246 | |
247 | static void rp2_rmw_set(struct rp2_uart_port *up, int reg, u32 val) |
248 | { |
249 | rp2_rmw(up, reg, clr_bits: 0, set_bits: val); |
250 | } |
251 | |
252 | static void rp2_mask_ch_irq(struct rp2_uart_port *up, int ch_num, |
253 | int is_enabled) |
254 | { |
255 | unsigned long flags, irq_mask; |
256 | |
257 | spin_lock_irqsave(&up->card->card_lock, flags); |
258 | |
259 | irq_mask = readl(addr: up->asic_base + RP2_CH_IRQ_MASK); |
260 | if (is_enabled) |
261 | irq_mask &= ~BIT(ch_num); |
262 | else |
263 | irq_mask |= BIT(ch_num); |
264 | writel(val: irq_mask, addr: up->asic_base + RP2_CH_IRQ_MASK); |
265 | |
266 | spin_unlock_irqrestore(lock: &up->card->card_lock, flags); |
267 | } |
268 | |
269 | static unsigned int rp2_uart_tx_empty(struct uart_port *port) |
270 | { |
271 | struct rp2_uart_port *up = port_to_up(port); |
272 | unsigned long tx_fifo_bytes, flags; |
273 | |
274 | /* |
275 | * This should probably check the transmitter, not the FIFO. |
276 | * But the TXEMPTY bit doesn't seem to work unless the TX IRQ is |
277 | * enabled. |
278 | */ |
279 | uart_port_lock_irqsave(up: &up->port, flags: &flags); |
280 | tx_fifo_bytes = readw(addr: up->base + RP2_TX_FIFO_COUNT); |
281 | uart_port_unlock_irqrestore(up: &up->port, flags); |
282 | |
283 | return tx_fifo_bytes ? 0 : TIOCSER_TEMT; |
284 | } |
285 | |
286 | static unsigned int rp2_uart_get_mctrl(struct uart_port *port) |
287 | { |
288 | struct rp2_uart_port *up = port_to_up(port); |
289 | u32 status; |
290 | |
291 | status = readl(addr: up->base + RP2_CHAN_STAT); |
292 | return ((status & RP2_CHAN_STAT_DCD_m) ? TIOCM_CAR : 0) | |
293 | ((status & RP2_CHAN_STAT_DSR_m) ? TIOCM_DSR : 0) | |
294 | ((status & RP2_CHAN_STAT_CTS_m) ? TIOCM_CTS : 0) | |
295 | ((status & RP2_CHAN_STAT_RI_m) ? TIOCM_RI : 0); |
296 | } |
297 | |
298 | static void rp2_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) |
299 | { |
300 | rp2_rmw(up: port_to_up(port), RP2_TXRX_CTL, |
301 | RP2_TXRX_CTL_DTR_m | RP2_TXRX_CTL_RTS_m | RP2_TXRX_CTL_LOOP_m, |
302 | set_bits: ((mctrl & TIOCM_DTR) ? RP2_TXRX_CTL_DTR_m : 0) | |
303 | ((mctrl & TIOCM_RTS) ? RP2_TXRX_CTL_RTS_m : 0) | |
304 | ((mctrl & TIOCM_LOOP) ? RP2_TXRX_CTL_LOOP_m : 0)); |
305 | } |
306 | |
307 | static void rp2_uart_start_tx(struct uart_port *port) |
308 | { |
309 | rp2_rmw_set(up: port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_TXIRQ_m); |
310 | } |
311 | |
312 | static void rp2_uart_stop_tx(struct uart_port *port) |
313 | { |
314 | rp2_rmw_clr(up: port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_TXIRQ_m); |
315 | } |
316 | |
317 | static void rp2_uart_stop_rx(struct uart_port *port) |
318 | { |
319 | rp2_rmw_clr(up: port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_RXIRQ_m); |
320 | } |
321 | |
322 | static void rp2_uart_break_ctl(struct uart_port *port, int break_state) |
323 | { |
324 | unsigned long flags; |
325 | |
326 | uart_port_lock_irqsave(up: port, flags: &flags); |
327 | rp2_rmw(up: port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_BREAK_m, |
328 | set_bits: break_state ? RP2_TXRX_CTL_BREAK_m : 0); |
329 | uart_port_unlock_irqrestore(up: port, flags); |
330 | } |
331 | |
332 | static void rp2_uart_enable_ms(struct uart_port *port) |
333 | { |
334 | rp2_rmw_set(up: port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_MSRIRQ_m); |
335 | } |
336 | |
337 | static void __rp2_uart_set_termios(struct rp2_uart_port *up, |
338 | unsigned long cfl, |
339 | unsigned long ifl, |
340 | unsigned int baud_div) |
341 | { |
342 | /* baud rate divisor (calculated elsewhere). 0 = divide-by-1 */ |
343 | writew(val: baud_div - 1, addr: up->base + RP2_BAUD); |
344 | |
345 | /* data bits and stop bits */ |
346 | rp2_rmw(up, RP2_UART_CTL, |
347 | RP2_UART_CTL_STOPBITS_m | RP2_UART_CTL_DATABITS_m, |
348 | set_bits: ((cfl & CSTOPB) ? RP2_UART_CTL_STOPBITS_m : 0) | |
349 | (((cfl & CSIZE) == CS8) ? RP2_UART_CTL_DATABITS_8 : 0) | |
350 | (((cfl & CSIZE) == CS7) ? RP2_UART_CTL_DATABITS_7 : 0) | |
351 | (((cfl & CSIZE) == CS6) ? RP2_UART_CTL_DATABITS_6 : 0) | |
352 | (((cfl & CSIZE) == CS5) ? RP2_UART_CTL_DATABITS_5 : 0)); |
353 | |
354 | /* parity and hardware flow control */ |
355 | rp2_rmw(up, RP2_TXRX_CTL, |
356 | RP2_TXRX_CTL_PARENB_m | RP2_TXRX_CTL_nPARODD_m | |
357 | RP2_TXRX_CTL_CMSPAR_m | RP2_TXRX_CTL_DTRFLOW_m | |
358 | RP2_TXRX_CTL_DSRFLOW_m | RP2_TXRX_CTL_RTSFLOW_m | |
359 | RP2_TXRX_CTL_CTSFLOW_m, |
360 | set_bits: ((cfl & PARENB) ? RP2_TXRX_CTL_PARENB_m : 0) | |
361 | ((cfl & PARODD) ? 0 : RP2_TXRX_CTL_nPARODD_m) | |
362 | ((cfl & CMSPAR) ? RP2_TXRX_CTL_CMSPAR_m : 0) | |
363 | ((cfl & CRTSCTS) ? (RP2_TXRX_CTL_RTSFLOW_m | |
364 | RP2_TXRX_CTL_CTSFLOW_m) : 0)); |
365 | |
366 | /* XON/XOFF software flow control */ |
367 | writeb(val: (ifl & IXON) ? RP2_TX_SWFLOW_ena : RP2_TX_SWFLOW_dis, |
368 | addr: up->ucode + RP2_TX_SWFLOW); |
369 | writeb(val: (ifl & IXOFF) ? RP2_RX_SWFLOW_ena : RP2_RX_SWFLOW_dis, |
370 | addr: up->ucode + RP2_RX_SWFLOW); |
371 | } |
372 | |
373 | static void rp2_uart_set_termios(struct uart_port *port, struct ktermios *new, |
374 | const struct ktermios *old) |
375 | { |
376 | struct rp2_uart_port *up = port_to_up(port); |
377 | unsigned long flags; |
378 | unsigned int baud, baud_div; |
379 | |
380 | baud = uart_get_baud_rate(port, termios: new, old, min: 0, max: port->uartclk / 16); |
381 | baud_div = uart_get_divisor(port, baud); |
382 | |
383 | if (tty_termios_baud_rate(termios: new)) |
384 | tty_termios_encode_baud_rate(termios: new, ibaud: baud, obaud: baud); |
385 | |
386 | uart_port_lock_irqsave(up: port, flags: &flags); |
387 | |
388 | /* ignore all characters if CREAD is not set */ |
389 | port->ignore_status_mask = (new->c_cflag & CREAD) ? 0 : RP2_DUMMY_READ; |
390 | |
391 | __rp2_uart_set_termios(up, cfl: new->c_cflag, ifl: new->c_iflag, baud_div); |
392 | uart_update_timeout(port, cflag: new->c_cflag, baud); |
393 | |
394 | uart_port_unlock_irqrestore(up: port, flags); |
395 | } |
396 | |
397 | static void rp2_rx_chars(struct rp2_uart_port *up) |
398 | { |
399 | u16 bytes = readw(addr: up->base + RP2_RX_FIFO_COUNT); |
400 | struct tty_port *port = &up->port.state->port; |
401 | |
402 | for (; bytes != 0; bytes--) { |
403 | u32 byte = readw(addr: up->base + RP2_DATA_BYTE) | RP2_DUMMY_READ; |
404 | u8 ch = byte & 0xff; |
405 | |
406 | if (likely(!(byte & RP2_DATA_BYTE_EXCEPTION_MASK))) { |
407 | if (!uart_handle_sysrq_char(port: &up->port, ch)) |
408 | uart_insert_char(port: &up->port, status: byte, overrun: 0, ch, |
409 | TTY_NORMAL); |
410 | } else { |
411 | u8 flag = TTY_NORMAL; |
412 | |
413 | if (byte & RP2_DATA_BYTE_BREAK_m) |
414 | flag = TTY_BREAK; |
415 | else if (byte & RP2_DATA_BYTE_ERR_FRAMING_m) |
416 | flag = TTY_FRAME; |
417 | else if (byte & RP2_DATA_BYTE_ERR_PARITY_m) |
418 | flag = TTY_PARITY; |
419 | uart_insert_char(port: &up->port, status: byte, |
420 | RP2_DATA_BYTE_ERR_OVERRUN_m, ch, flag); |
421 | } |
422 | up->port.icount.rx++; |
423 | } |
424 | |
425 | tty_flip_buffer_push(port); |
426 | } |
427 | |
428 | static void rp2_tx_chars(struct rp2_uart_port *up) |
429 | { |
430 | u8 ch; |
431 | |
432 | uart_port_tx_limited(&up->port, ch, |
433 | FIFO_SIZE - readw(up->base + RP2_TX_FIFO_COUNT), |
434 | true, |
435 | writeb(ch, up->base + RP2_DATA_BYTE), |
436 | ({})); |
437 | } |
438 | |
439 | static void rp2_ch_interrupt(struct rp2_uart_port *up) |
440 | { |
441 | u32 status; |
442 | |
443 | uart_port_lock(up: &up->port); |
444 | |
445 | /* |
446 | * The IRQ status bits are clear-on-write. Other status bits in |
447 | * this register aren't, so it's harmless to write to them. |
448 | */ |
449 | status = readl(addr: up->base + RP2_CHAN_STAT); |
450 | writel(val: status, addr: up->base + RP2_CHAN_STAT); |
451 | |
452 | if (status & RP2_CHAN_STAT_RXDATA_m) |
453 | rp2_rx_chars(up); |
454 | if (status & RP2_CHAN_STAT_TXEMPTY_m) |
455 | rp2_tx_chars(up); |
456 | if (status & RP2_CHAN_STAT_MS_CHANGED_MASK) |
457 | wake_up_interruptible(&up->port.state->port.delta_msr_wait); |
458 | |
459 | uart_port_unlock(up: &up->port); |
460 | } |
461 | |
462 | static int rp2_asic_interrupt(struct rp2_card *card, unsigned int asic_id) |
463 | { |
464 | void __iomem *base = card->bar1 + RP2_ASIC_OFFSET(asic_id); |
465 | int ch, handled = 0; |
466 | unsigned long status = readl(addr: base + RP2_CH_IRQ_STAT) & |
467 | ~readl(addr: base + RP2_CH_IRQ_MASK); |
468 | |
469 | for_each_set_bit(ch, &status, PORTS_PER_ASIC) { |
470 | rp2_ch_interrupt(up: &card->ports[ch]); |
471 | handled++; |
472 | } |
473 | return handled; |
474 | } |
475 | |
476 | static irqreturn_t rp2_uart_interrupt(int irq, void *dev_id) |
477 | { |
478 | struct rp2_card *card = dev_id; |
479 | int handled; |
480 | |
481 | handled = rp2_asic_interrupt(card, asic_id: 0); |
482 | if (card->n_ports >= PORTS_PER_ASIC) |
483 | handled += rp2_asic_interrupt(card, asic_id: 1); |
484 | |
485 | return handled ? IRQ_HANDLED : IRQ_NONE; |
486 | } |
487 | |
488 | static inline void rp2_flush_fifos(struct rp2_uart_port *up) |
489 | { |
490 | rp2_rmw_set(up, RP2_UART_CTL, |
491 | RP2_UART_CTL_FLUSH_RX_m | RP2_UART_CTL_FLUSH_TX_m); |
492 | readl(addr: up->base + RP2_UART_CTL); |
493 | udelay(10); |
494 | rp2_rmw_clr(up, RP2_UART_CTL, |
495 | RP2_UART_CTL_FLUSH_RX_m | RP2_UART_CTL_FLUSH_TX_m); |
496 | } |
497 | |
498 | static int rp2_uart_startup(struct uart_port *port) |
499 | { |
500 | struct rp2_uart_port *up = port_to_up(port); |
501 | |
502 | rp2_flush_fifos(up); |
503 | rp2_rmw(up, RP2_TXRX_CTL, RP2_TXRX_CTL_MSRIRQ_m, RP2_TXRX_CTL_RXIRQ_m); |
504 | rp2_rmw(up, RP2_TXRX_CTL, RP2_TXRX_CTL_RX_TRIG_m, |
505 | RP2_TXRX_CTL_RX_TRIG_1); |
506 | rp2_rmw(up, RP2_CHAN_STAT, clr_bits: 0, set_bits: 0); |
507 | rp2_mask_ch_irq(up, ch_num: up->idx, is_enabled: 1); |
508 | |
509 | return 0; |
510 | } |
511 | |
512 | static void rp2_uart_shutdown(struct uart_port *port) |
513 | { |
514 | struct rp2_uart_port *up = port_to_up(port); |
515 | unsigned long flags; |
516 | |
517 | rp2_uart_break_ctl(port, break_state: 0); |
518 | |
519 | uart_port_lock_irqsave(up: port, flags: &flags); |
520 | rp2_mask_ch_irq(up, ch_num: up->idx, is_enabled: 0); |
521 | rp2_rmw(up, RP2_CHAN_STAT, clr_bits: 0, set_bits: 0); |
522 | uart_port_unlock_irqrestore(up: port, flags); |
523 | } |
524 | |
525 | static const char *rp2_uart_type(struct uart_port *port) |
526 | { |
527 | return (port->type == PORT_RP2) ? "RocketPort 2 UART" : NULL; |
528 | } |
529 | |
530 | static void rp2_uart_release_port(struct uart_port *port) |
531 | { |
532 | /* Nothing to release ... */ |
533 | } |
534 | |
535 | static int rp2_uart_request_port(struct uart_port *port) |
536 | { |
537 | /* UARTs always present */ |
538 | return 0; |
539 | } |
540 | |
541 | static void rp2_uart_config_port(struct uart_port *port, int flags) |
542 | { |
543 | if (flags & UART_CONFIG_TYPE) |
544 | port->type = PORT_RP2; |
545 | } |
546 | |
547 | static int rp2_uart_verify_port(struct uart_port *port, |
548 | struct serial_struct *ser) |
549 | { |
550 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_RP2) |
551 | return -EINVAL; |
552 | |
553 | return 0; |
554 | } |
555 | |
556 | static const struct uart_ops rp2_uart_ops = { |
557 | .tx_empty = rp2_uart_tx_empty, |
558 | .set_mctrl = rp2_uart_set_mctrl, |
559 | .get_mctrl = rp2_uart_get_mctrl, |
560 | .stop_tx = rp2_uart_stop_tx, |
561 | .start_tx = rp2_uart_start_tx, |
562 | .stop_rx = rp2_uart_stop_rx, |
563 | .enable_ms = rp2_uart_enable_ms, |
564 | .break_ctl = rp2_uart_break_ctl, |
565 | .startup = rp2_uart_startup, |
566 | .shutdown = rp2_uart_shutdown, |
567 | .set_termios = rp2_uart_set_termios, |
568 | .type = rp2_uart_type, |
569 | .release_port = rp2_uart_release_port, |
570 | .request_port = rp2_uart_request_port, |
571 | .config_port = rp2_uart_config_port, |
572 | .verify_port = rp2_uart_verify_port, |
573 | }; |
574 | |
575 | static void rp2_reset_asic(struct rp2_card *card, unsigned int asic_id) |
576 | { |
577 | void __iomem *base = card->bar1 + RP2_ASIC_OFFSET(asic_id); |
578 | u32 clk_cfg; |
579 | |
580 | writew(val: 1, addr: base + RP2_GLOBAL_CMD); |
581 | readw(addr: base + RP2_GLOBAL_CMD); |
582 | msleep(msecs: 100); |
583 | writel(val: 0, addr: base + RP2_CLK_PRESCALER); |
584 | |
585 | /* TDM clock configuration */ |
586 | clk_cfg = readw(addr: base + RP2_ASIC_CFG); |
587 | clk_cfg = (clk_cfg & ~BIT(8)) | BIT(9); |
588 | writew(val: clk_cfg, addr: base + RP2_ASIC_CFG); |
589 | |
590 | /* IRQ routing */ |
591 | writel(ALL_PORTS_MASK, addr: base + RP2_CH_IRQ_MASK); |
592 | writel(RP2_ASIC_IRQ_EN_m, addr: base + RP2_ASIC_IRQ); |
593 | } |
594 | |
595 | static void rp2_init_card(struct rp2_card *card) |
596 | { |
597 | writel(val: 4, addr: card->bar0 + RP2_FPGA_CTL0); |
598 | writel(val: 0, addr: card->bar0 + RP2_FPGA_CTL1); |
599 | |
600 | rp2_reset_asic(card, asic_id: 0); |
601 | if (card->n_ports >= PORTS_PER_ASIC) |
602 | rp2_reset_asic(card, asic_id: 1); |
603 | |
604 | writel(RP2_IRQ_MASK_EN_m, addr: card->bar0 + RP2_IRQ_MASK); |
605 | } |
606 | |
607 | static void rp2_init_port(struct rp2_uart_port *up, const struct firmware *fw) |
608 | { |
609 | int i; |
610 | |
611 | writel(RP2_UART_CTL_RESET_CH_m, addr: up->base + RP2_UART_CTL); |
612 | readl(addr: up->base + RP2_UART_CTL); |
613 | udelay(1); |
614 | |
615 | writel(val: 0, addr: up->base + RP2_TXRX_CTL); |
616 | writel(val: 0, addr: up->base + RP2_UART_CTL); |
617 | readl(addr: up->base + RP2_UART_CTL); |
618 | udelay(1); |
619 | |
620 | rp2_flush_fifos(up); |
621 | |
622 | for (i = 0; i < min_t(int, fw->size, RP2_UCODE_BYTES); i++) |
623 | writeb(val: fw->data[i], addr: up->ucode + i); |
624 | |
625 | __rp2_uart_set_termios(up, CS8 | CREAD | CLOCAL, ifl: 0, DEFAULT_BAUD_DIV); |
626 | rp2_uart_set_mctrl(port: &up->port, mctrl: 0); |
627 | |
628 | writeb(RP2_RX_FIFO_ena, addr: up->ucode + RP2_RX_FIFO); |
629 | rp2_rmw(up, RP2_UART_CTL, RP2_UART_CTL_MODE_m, |
630 | RP2_UART_CTL_XMIT_EN_m | RP2_UART_CTL_MODE_rs232); |
631 | rp2_rmw_set(up, RP2_TXRX_CTL, |
632 | RP2_TXRX_CTL_TX_EN_m | RP2_TXRX_CTL_RX_EN_m); |
633 | } |
634 | |
635 | static void rp2_remove_ports(struct rp2_card *card) |
636 | { |
637 | int i; |
638 | |
639 | for (i = 0; i < card->initialized_ports; i++) |
640 | uart_remove_one_port(reg: &rp2_uart_driver, port: &card->ports[i].port); |
641 | card->initialized_ports = 0; |
642 | } |
643 | |
644 | static int rp2_load_firmware(struct rp2_card *card, const struct firmware *fw) |
645 | { |
646 | resource_size_t phys_base; |
647 | int i, rc = 0; |
648 | |
649 | phys_base = pci_resource_start(card->pdev, 1); |
650 | |
651 | for (i = 0; i < card->n_ports; i++) { |
652 | struct rp2_uart_port *rp = &card->ports[i]; |
653 | struct uart_port *p; |
654 | int j = (unsigned)i % PORTS_PER_ASIC; |
655 | |
656 | rp->asic_base = card->bar1; |
657 | rp->base = card->bar1 + RP2_PORT_BASE + j*RP2_PORT_SPACING; |
658 | rp->ucode = card->bar1 + RP2_UCODE_BASE + j*RP2_UCODE_SPACING; |
659 | rp->card = card; |
660 | rp->idx = j; |
661 | |
662 | p = &rp->port; |
663 | p->line = card->minor_start + i; |
664 | p->dev = &card->pdev->dev; |
665 | p->type = PORT_RP2; |
666 | p->iotype = UPIO_MEM32; |
667 | p->uartclk = UART_CLOCK; |
668 | p->regshift = 2; |
669 | p->fifosize = FIFO_SIZE; |
670 | p->ops = &rp2_uart_ops; |
671 | p->irq = card->pdev->irq; |
672 | p->membase = rp->base; |
673 | p->mapbase = phys_base + RP2_PORT_BASE + j*RP2_PORT_SPACING; |
674 | |
675 | if (i >= PORTS_PER_ASIC) { |
676 | rp->asic_base += RP2_ASIC_SPACING; |
677 | rp->base += RP2_ASIC_SPACING; |
678 | rp->ucode += RP2_ASIC_SPACING; |
679 | p->mapbase += RP2_ASIC_SPACING; |
680 | } |
681 | |
682 | rp2_init_port(up: rp, fw); |
683 | rc = uart_add_one_port(reg: &rp2_uart_driver, port: p); |
684 | if (rc) { |
685 | dev_err(&card->pdev->dev, |
686 | "error registering port %d: %d\n" , i, rc); |
687 | rp2_remove_ports(card); |
688 | break; |
689 | } |
690 | card->initialized_ports++; |
691 | } |
692 | |
693 | return rc; |
694 | } |
695 | |
696 | static int rp2_probe(struct pci_dev *pdev, |
697 | const struct pci_device_id *id) |
698 | { |
699 | const struct firmware *fw; |
700 | struct rp2_card *card; |
701 | struct rp2_uart_port *ports; |
702 | void __iomem * const *bars; |
703 | int rc; |
704 | |
705 | card = devm_kzalloc(dev: &pdev->dev, size: sizeof(*card), GFP_KERNEL); |
706 | if (!card) |
707 | return -ENOMEM; |
708 | pci_set_drvdata(pdev, data: card); |
709 | spin_lock_init(&card->card_lock); |
710 | |
711 | rc = pcim_enable_device(pdev); |
712 | if (rc) |
713 | return rc; |
714 | |
715 | rc = pcim_iomap_regions_request_all(pdev, mask: 0x03, DRV_NAME); |
716 | if (rc) |
717 | return rc; |
718 | |
719 | bars = pcim_iomap_table(pdev); |
720 | card->bar0 = bars[0]; |
721 | card->bar1 = bars[1]; |
722 | card->pdev = pdev; |
723 | |
724 | rp2_decode_cap(id, ports: &card->n_ports, smpte: &card->smpte); |
725 | dev_info(&pdev->dev, "found new card with %d ports\n" , card->n_ports); |
726 | |
727 | card->minor_start = rp2_alloc_ports(n_ports: card->n_ports); |
728 | if (card->minor_start < 0) { |
729 | dev_err(&pdev->dev, |
730 | "too many ports (try increasing CONFIG_SERIAL_RP2_NR_UARTS)\n" ); |
731 | return -EINVAL; |
732 | } |
733 | |
734 | rp2_init_card(card); |
735 | |
736 | ports = devm_kcalloc(dev: &pdev->dev, n: card->n_ports, size: sizeof(*ports), |
737 | GFP_KERNEL); |
738 | if (!ports) |
739 | return -ENOMEM; |
740 | card->ports = ports; |
741 | |
742 | rc = request_firmware(fw: &fw, RP2_FW_NAME, device: &pdev->dev); |
743 | if (rc < 0) { |
744 | dev_err(&pdev->dev, "cannot find '%s' firmware image\n" , |
745 | RP2_FW_NAME); |
746 | return rc; |
747 | } |
748 | |
749 | rc = rp2_load_firmware(card, fw); |
750 | |
751 | release_firmware(fw); |
752 | if (rc < 0) |
753 | return rc; |
754 | |
755 | rc = devm_request_irq(dev: &pdev->dev, irq: pdev->irq, handler: rp2_uart_interrupt, |
756 | IRQF_SHARED, DRV_NAME, dev_id: card); |
757 | if (rc) |
758 | return rc; |
759 | |
760 | return 0; |
761 | } |
762 | |
763 | static void rp2_remove(struct pci_dev *pdev) |
764 | { |
765 | struct rp2_card *card = pci_get_drvdata(pdev); |
766 | |
767 | rp2_remove_ports(card); |
768 | } |
769 | |
770 | static const struct pci_device_id rp2_pci_tbl[] = { |
771 | |
772 | /* RocketPort INFINITY cards */ |
773 | |
774 | { RP_ID(0x0040), RP_CAP(8, 0) }, /* INF Octa, RJ45, selectable */ |
775 | { RP_ID(0x0041), RP_CAP(32, 0) }, /* INF 32, ext interface */ |
776 | { RP_ID(0x0042), RP_CAP(8, 0) }, /* INF Octa, ext interface */ |
777 | { RP_ID(0x0043), RP_CAP(16, 0) }, /* INF 16, ext interface */ |
778 | { RP_ID(0x0044), RP_CAP(4, 0) }, /* INF Quad, DB, selectable */ |
779 | { RP_ID(0x0045), RP_CAP(8, 0) }, /* INF Octa, DB, selectable */ |
780 | { RP_ID(0x0046), RP_CAP(4, 0) }, /* INF Quad, ext interface */ |
781 | { RP_ID(0x0047), RP_CAP(4, 0) }, /* INF Quad, RJ45 */ |
782 | { RP_ID(0x004a), RP_CAP(4, 0) }, /* INF Plus, Quad */ |
783 | { RP_ID(0x004b), RP_CAP(8, 0) }, /* INF Plus, Octa */ |
784 | { RP_ID(0x004c), RP_CAP(8, 0) }, /* INF III, Octa */ |
785 | { RP_ID(0x004d), RP_CAP(4, 0) }, /* INF III, Quad */ |
786 | { RP_ID(0x004e), RP_CAP(2, 0) }, /* INF Plus, 2, RS232 */ |
787 | { RP_ID(0x004f), RP_CAP(2, 1) }, /* INF Plus, 2, SMPTE */ |
788 | { RP_ID(0x0050), RP_CAP(4, 0) }, /* INF Plus, Quad, RJ45 */ |
789 | { RP_ID(0x0051), RP_CAP(8, 0) }, /* INF Plus, Octa, RJ45 */ |
790 | { RP_ID(0x0052), RP_CAP(8, 1) }, /* INF Octa, SMPTE */ |
791 | |
792 | /* RocketPort EXPRESS cards */ |
793 | |
794 | { RP_ID(0x0060), RP_CAP(8, 0) }, /* EXP Octa, RJ45, selectable */ |
795 | { RP_ID(0x0061), RP_CAP(32, 0) }, /* EXP 32, ext interface */ |
796 | { RP_ID(0x0062), RP_CAP(8, 0) }, /* EXP Octa, ext interface */ |
797 | { RP_ID(0x0063), RP_CAP(16, 0) }, /* EXP 16, ext interface */ |
798 | { RP_ID(0x0064), RP_CAP(4, 0) }, /* EXP Quad, DB, selectable */ |
799 | { RP_ID(0x0065), RP_CAP(8, 0) }, /* EXP Octa, DB, selectable */ |
800 | { RP_ID(0x0066), RP_CAP(4, 0) }, /* EXP Quad, ext interface */ |
801 | { RP_ID(0x0067), RP_CAP(4, 0) }, /* EXP Quad, RJ45 */ |
802 | { RP_ID(0x0068), RP_CAP(8, 0) }, /* EXP Octa, RJ11 */ |
803 | { RP_ID(0x0072), RP_CAP(8, 1) }, /* EXP Octa, SMPTE */ |
804 | { } |
805 | }; |
806 | MODULE_DEVICE_TABLE(pci, rp2_pci_tbl); |
807 | |
808 | static struct pci_driver rp2_pci_driver = { |
809 | .name = DRV_NAME, |
810 | .id_table = rp2_pci_tbl, |
811 | .probe = rp2_probe, |
812 | .remove = rp2_remove, |
813 | }; |
814 | |
815 | static int __init rp2_uart_init(void) |
816 | { |
817 | int rc; |
818 | |
819 | rc = uart_register_driver(uart: &rp2_uart_driver); |
820 | if (rc) |
821 | return rc; |
822 | |
823 | rc = pci_register_driver(&rp2_pci_driver); |
824 | if (rc) { |
825 | uart_unregister_driver(uart: &rp2_uart_driver); |
826 | return rc; |
827 | } |
828 | |
829 | return 0; |
830 | } |
831 | |
832 | static void __exit rp2_uart_exit(void) |
833 | { |
834 | pci_unregister_driver(dev: &rp2_pci_driver); |
835 | uart_unregister_driver(uart: &rp2_uart_driver); |
836 | } |
837 | |
838 | module_init(rp2_uart_init); |
839 | module_exit(rp2_uart_exit); |
840 | |
841 | MODULE_DESCRIPTION("Comtrol RocketPort EXPRESS/INFINITY driver" ); |
842 | MODULE_AUTHOR("Kevin Cernekee <cernekee@gmail.com>" ); |
843 | MODULE_LICENSE("GPL v2" ); |
844 | MODULE_FIRMWARE(RP2_FW_NAME); |
845 | |