1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * Copyright (C) Maxime Coquelin 2015 |
4 | * Copyright (C) STMicroelectronics SA 2017 |
5 | * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com> |
6 | * Gerald Baeza <gerald_baeza@yahoo.fr> |
7 | */ |
8 | |
9 | #define DRIVER_NAME "stm32-usart" |
10 | |
11 | struct stm32_usart_offsets { |
12 | u8 cr1; |
13 | u8 cr2; |
14 | u8 cr3; |
15 | u8 brr; |
16 | u8 gtpr; |
17 | u8 rtor; |
18 | u8 rqr; |
19 | u8 isr; |
20 | u8 icr; |
21 | u8 rdr; |
22 | u8 tdr; |
23 | }; |
24 | |
25 | struct stm32_usart_config { |
26 | u8 uart_enable_bit; /* USART_CR1_UE */ |
27 | bool has_7bits_data; |
28 | bool has_swap; |
29 | bool has_wakeup; |
30 | bool has_fifo; |
31 | int fifosize; |
32 | }; |
33 | |
34 | struct stm32_usart_info { |
35 | struct stm32_usart_offsets ofs; |
36 | struct stm32_usart_config cfg; |
37 | }; |
38 | |
39 | #define UNDEF_REG 0xff |
40 | |
41 | /* USART_SR (F4) / USART_ISR (F7) */ |
42 | #define USART_SR_PE BIT(0) |
43 | #define USART_SR_FE BIT(1) |
44 | #define USART_SR_NE BIT(2) /* F7 (NF for F4) */ |
45 | #define USART_SR_ORE BIT(3) |
46 | #define USART_SR_IDLE BIT(4) |
47 | #define USART_SR_RXNE BIT(5) |
48 | #define USART_SR_TC BIT(6) |
49 | #define USART_SR_TXE BIT(7) |
50 | #define USART_SR_CTSIF BIT(9) |
51 | #define USART_SR_CTS BIT(10) /* F7 */ |
52 | #define USART_SR_RTOF BIT(11) /* F7 */ |
53 | #define USART_SR_EOBF BIT(12) /* F7 */ |
54 | #define USART_SR_ABRE BIT(14) /* F7 */ |
55 | #define USART_SR_ABRF BIT(15) /* F7 */ |
56 | #define USART_SR_BUSY BIT(16) /* F7 */ |
57 | #define USART_SR_CMF BIT(17) /* F7 */ |
58 | #define USART_SR_SBKF BIT(18) /* F7 */ |
59 | #define USART_SR_WUF BIT(20) /* H7 */ |
60 | #define USART_SR_TEACK BIT(21) /* F7 */ |
61 | #define USART_SR_ERR_MASK (USART_SR_ORE | USART_SR_NE | USART_SR_FE |\ |
62 | USART_SR_PE) |
63 | /* Dummy bits */ |
64 | #define USART_SR_DUMMY_RX BIT(16) |
65 | |
66 | /* USART_DR */ |
67 | #define USART_DR_MASK GENMASK(8, 0) |
68 | |
69 | /* USART_BRR */ |
70 | #define USART_BRR_DIV_F_MASK GENMASK(3, 0) |
71 | #define USART_BRR_DIV_M_MASK GENMASK(15, 4) |
72 | #define USART_BRR_DIV_M_SHIFT 4 |
73 | #define USART_BRR_04_R_SHIFT 1 |
74 | |
75 | /* USART_CR1 */ |
76 | #define USART_CR1_SBK BIT(0) |
77 | #define USART_CR1_RWU BIT(1) /* F4 */ |
78 | #define USART_CR1_UESM BIT(1) /* H7 */ |
79 | #define USART_CR1_RE BIT(2) |
80 | #define USART_CR1_TE BIT(3) |
81 | #define USART_CR1_IDLEIE BIT(4) |
82 | #define USART_CR1_RXNEIE BIT(5) |
83 | #define USART_CR1_TCIE BIT(6) |
84 | #define USART_CR1_TXEIE BIT(7) |
85 | #define USART_CR1_PEIE BIT(8) |
86 | #define USART_CR1_PS BIT(9) |
87 | #define USART_CR1_PCE BIT(10) |
88 | #define USART_CR1_WAKE BIT(11) |
89 | #define USART_CR1_M0 BIT(12) /* F7 (CR1_M for F4) */ |
90 | #define USART_CR1_MME BIT(13) /* F7 */ |
91 | #define USART_CR1_CMIE BIT(14) /* F7 */ |
92 | #define USART_CR1_OVER8 BIT(15) |
93 | #define USART_CR1_DEDT_MASK GENMASK(20, 16) /* F7 */ |
94 | #define USART_CR1_DEAT_MASK GENMASK(25, 21) /* F7 */ |
95 | #define USART_CR1_RTOIE BIT(26) /* F7 */ |
96 | #define USART_CR1_EOBIE BIT(27) /* F7 */ |
97 | #define USART_CR1_M1 BIT(28) /* F7 */ |
98 | #define USART_CR1_IE_MASK (GENMASK(8, 4) | BIT(14) | BIT(26) | BIT(27)) |
99 | #define USART_CR1_FIFOEN BIT(29) /* H7 */ |
100 | #define USART_CR1_DEAT_SHIFT 21 |
101 | #define USART_CR1_DEDT_SHIFT 16 |
102 | |
103 | /* USART_CR2 */ |
104 | #define USART_CR2_ADD_MASK GENMASK(3, 0) /* F4 */ |
105 | #define USART_CR2_ADDM7 BIT(4) /* F7 */ |
106 | #define USART_CR2_LBCL BIT(8) |
107 | #define USART_CR2_CPHA BIT(9) |
108 | #define USART_CR2_CPOL BIT(10) |
109 | #define USART_CR2_CLKEN BIT(11) |
110 | #define USART_CR2_STOP_2B BIT(13) |
111 | #define USART_CR2_STOP_MASK GENMASK(13, 12) |
112 | #define USART_CR2_LINEN BIT(14) |
113 | #define USART_CR2_SWAP BIT(15) /* F7 */ |
114 | #define USART_CR2_RXINV BIT(16) /* F7 */ |
115 | #define USART_CR2_TXINV BIT(17) /* F7 */ |
116 | #define USART_CR2_DATAINV BIT(18) /* F7 */ |
117 | #define USART_CR2_MSBFIRST BIT(19) /* F7 */ |
118 | #define USART_CR2_ABREN BIT(20) /* F7 */ |
119 | #define USART_CR2_ABRMOD_MASK GENMASK(22, 21) /* F7 */ |
120 | #define USART_CR2_RTOEN BIT(23) /* F7 */ |
121 | #define USART_CR2_ADD_F7_MASK GENMASK(31, 24) /* F7 */ |
122 | |
123 | /* USART_CR3 */ |
124 | #define USART_CR3_EIE BIT(0) |
125 | #define USART_CR3_IREN BIT(1) |
126 | #define USART_CR3_IRLP BIT(2) |
127 | #define USART_CR3_HDSEL BIT(3) |
128 | #define USART_CR3_NACK BIT(4) |
129 | #define USART_CR3_SCEN BIT(5) |
130 | #define USART_CR3_DMAR BIT(6) |
131 | #define USART_CR3_DMAT BIT(7) |
132 | #define USART_CR3_RTSE BIT(8) |
133 | #define USART_CR3_CTSE BIT(9) |
134 | #define USART_CR3_CTSIE BIT(10) |
135 | #define USART_CR3_ONEBIT BIT(11) |
136 | #define USART_CR3_OVRDIS BIT(12) /* F7 */ |
137 | #define USART_CR3_DDRE BIT(13) /* F7 */ |
138 | #define USART_CR3_DEM BIT(14) /* F7 */ |
139 | #define USART_CR3_DEP BIT(15) /* F7 */ |
140 | #define USART_CR3_SCARCNT_MASK GENMASK(19, 17) /* F7 */ |
141 | #define USART_CR3_WUS_MASK GENMASK(21, 20) /* H7 */ |
142 | #define USART_CR3_WUS_START_BIT BIT(21) /* H7 */ |
143 | #define USART_CR3_WUFIE BIT(22) /* H7 */ |
144 | #define USART_CR3_TXFTIE BIT(23) /* H7 */ |
145 | #define USART_CR3_TCBGTIE BIT(24) /* H7 */ |
146 | #define USART_CR3_RXFTCFG_MASK GENMASK(27, 25) /* H7 */ |
147 | #define USART_CR3_RXFTCFG_SHIFT 25 /* H7 */ |
148 | #define USART_CR3_RXFTIE BIT(28) /* H7 */ |
149 | #define USART_CR3_TXFTCFG_MASK GENMASK(31, 29) /* H7 */ |
150 | #define USART_CR3_TXFTCFG_SHIFT 29 /* H7 */ |
151 | |
152 | /* USART_GTPR */ |
153 | #define USART_GTPR_PSC_MASK GENMASK(7, 0) |
154 | #define USART_GTPR_GT_MASK GENMASK(15, 8) |
155 | |
156 | /* USART_RTOR */ |
157 | #define USART_RTOR_RTO_MASK GENMASK(23, 0) /* F7 */ |
158 | #define USART_RTOR_BLEN_MASK GENMASK(31, 24) /* F7 */ |
159 | |
160 | /* USART_RQR */ |
161 | #define USART_RQR_ABRRQ BIT(0) /* F7 */ |
162 | #define USART_RQR_SBKRQ BIT(1) /* F7 */ |
163 | #define USART_RQR_MMRQ BIT(2) /* F7 */ |
164 | #define USART_RQR_RXFRQ BIT(3) /* F7 */ |
165 | #define USART_RQR_TXFRQ BIT(4) /* F7 */ |
166 | |
167 | /* USART_ICR */ |
168 | #define USART_ICR_PECF BIT(0) /* F7 */ |
169 | #define USART_ICR_FECF BIT(1) /* F7 */ |
170 | #define USART_ICR_ORECF BIT(3) /* F7 */ |
171 | #define USART_ICR_IDLECF BIT(4) /* F7 */ |
172 | #define USART_ICR_TCCF BIT(6) /* F7 */ |
173 | #define USART_ICR_CTSCF BIT(9) /* F7 */ |
174 | #define USART_ICR_RTOCF BIT(11) /* F7 */ |
175 | #define USART_ICR_EOBCF BIT(12) /* F7 */ |
176 | #define USART_ICR_CMCF BIT(17) /* F7 */ |
177 | #define USART_ICR_WUCF BIT(20) /* H7 */ |
178 | |
179 | #define STM32_SERIAL_NAME "ttySTM" |
180 | #define STM32_MAX_PORTS 8 |
181 | |
182 | #define RX_BUF_L 4096 /* dma rx buffer length */ |
183 | #define RX_BUF_P (RX_BUF_L / 2) /* dma rx buffer period */ |
184 | #define TX_BUF_L RX_BUF_L /* dma tx buffer length */ |
185 | |
186 | #define STM32_USART_TIMEOUT_USEC USEC_PER_SEC /* 1s timeout in µs */ |
187 | |
188 | struct stm32_port { |
189 | struct uart_port port; |
190 | struct clk *clk; |
191 | const struct stm32_usart_info *info; |
192 | struct dma_chan *rx_ch; /* dma rx channel */ |
193 | dma_addr_t rx_dma_buf; /* dma rx buffer bus address */ |
194 | unsigned char *rx_buf; /* dma rx buffer cpu address */ |
195 | struct dma_chan *tx_ch; /* dma tx channel */ |
196 | dma_addr_t tx_dma_buf; /* dma tx buffer bus address */ |
197 | unsigned char *tx_buf; /* dma tx buffer cpu address */ |
198 | u32 cr1_irq; /* USART_CR1_RXNEIE or RTOIE */ |
199 | u32 cr3_irq; /* USART_CR3_RXFTIE */ |
200 | int last_res; |
201 | bool tx_dma_busy; /* dma tx transaction in progress */ |
202 | bool rx_dma_busy; /* dma rx transaction in progress */ |
203 | bool throttled; /* port throttled */ |
204 | bool hw_flow_control; |
205 | bool swap; /* swap RX & TX pins */ |
206 | bool fifoen; |
207 | int rxftcfg; /* RX FIFO threshold CFG */ |
208 | int txftcfg; /* TX FIFO threshold CFG */ |
209 | bool wakeup_src; |
210 | int rdr_mask; /* receive data register mask */ |
211 | struct mctrl_gpios *gpios; /* modem control gpios */ |
212 | struct dma_tx_state rx_dma_state; |
213 | }; |
214 | |
215 | static struct stm32_port stm32_ports[STM32_MAX_PORTS]; |
216 | static struct uart_driver stm32_usart_driver; |
217 | |