1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * ci.h - common structures, functions, and macros of the ChipIdea driver |
4 | * |
5 | * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. |
6 | * |
7 | * Author: David Lopo |
8 | */ |
9 | |
10 | #ifndef __DRIVERS_USB_CHIPIDEA_CI_H |
11 | #define __DRIVERS_USB_CHIPIDEA_CI_H |
12 | |
13 | #include <linux/list.h> |
14 | #include <linux/irqreturn.h> |
15 | #include <linux/usb.h> |
16 | #include <linux/usb/gadget.h> |
17 | #include <linux/usb/otg-fsm.h> |
18 | #include <linux/usb/otg.h> |
19 | #include <linux/usb/role.h> |
20 | #include <linux/ulpi/interface.h> |
21 | |
22 | /****************************************************************************** |
23 | * DEFINE |
24 | *****************************************************************************/ |
25 | #define TD_PAGE_COUNT 5 |
26 | #define CI_HDRC_PAGE_SIZE 4096ul /* page size for TD's */ |
27 | #define ENDPT_MAX 32 |
28 | #define CI_MAX_BUF_SIZE (TD_PAGE_COUNT * CI_HDRC_PAGE_SIZE) |
29 | |
30 | /****************************************************************************** |
31 | * REGISTERS |
32 | *****************************************************************************/ |
33 | /* Identification Registers */ |
34 | #define ID_ID 0x0 |
35 | #define ID_HWGENERAL 0x4 |
36 | #define ID_HWHOST 0x8 |
37 | #define ID_HWDEVICE 0xc |
38 | #define ID_HWTXBUF 0x10 |
39 | #define ID_HWRXBUF 0x14 |
40 | #define ID_SBUSCFG 0x90 |
41 | |
42 | /* register indices */ |
43 | enum ci_hw_regs { |
44 | CAP_CAPLENGTH, |
45 | CAP_HCCPARAMS, |
46 | CAP_DCCPARAMS, |
47 | CAP_TESTMODE, |
48 | CAP_LAST = CAP_TESTMODE, |
49 | OP_USBCMD, |
50 | OP_USBSTS, |
51 | OP_USBINTR, |
52 | OP_FRINDEX, |
53 | OP_DEVICEADDR, |
54 | OP_ENDPTLISTADDR, |
55 | OP_TTCTRL, |
56 | OP_BURSTSIZE, |
57 | OP_ULPI_VIEWPORT, |
58 | OP_PORTSC, |
59 | OP_DEVLC, |
60 | OP_OTGSC, |
61 | OP_USBMODE, |
62 | OP_ENDPTSETUPSTAT, |
63 | OP_ENDPTPRIME, |
64 | OP_ENDPTFLUSH, |
65 | OP_ENDPTSTAT, |
66 | OP_ENDPTCOMPLETE, |
67 | OP_ENDPTCTRL, |
68 | /* endptctrl1..15 follow */ |
69 | OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2, |
70 | }; |
71 | |
72 | /****************************************************************************** |
73 | * STRUCTURES |
74 | *****************************************************************************/ |
75 | /** |
76 | * struct ci_hw_ep - endpoint representation |
77 | * @ep: endpoint structure for gadget drivers |
78 | * @dir: endpoint direction (TX/RX) |
79 | * @num: endpoint number |
80 | * @type: endpoint type |
81 | * @name: string description of the endpoint |
82 | * @qh: queue head for this endpoint |
83 | * @wedge: is the endpoint wedged |
84 | * @ci: pointer to the controller |
85 | * @lock: pointer to controller's spinlock |
86 | * @td_pool: pointer to controller's TD pool |
87 | */ |
88 | struct ci_hw_ep { |
89 | struct usb_ep ep; |
90 | u8 dir; |
91 | u8 num; |
92 | u8 type; |
93 | char name[16]; |
94 | struct { |
95 | struct list_head queue; |
96 | struct ci_hw_qh *ptr; |
97 | dma_addr_t dma; |
98 | } qh; |
99 | int wedge; |
100 | |
101 | /* global resources */ |
102 | struct ci_hdrc *ci; |
103 | spinlock_t *lock; |
104 | struct dma_pool *td_pool; |
105 | struct td_node *pending_td; |
106 | }; |
107 | |
108 | enum ci_role { |
109 | CI_ROLE_HOST = 0, |
110 | CI_ROLE_GADGET, |
111 | CI_ROLE_END, |
112 | }; |
113 | |
114 | enum ci_revision { |
115 | CI_REVISION_1X = 10, /* Revision 1.x */ |
116 | CI_REVISION_20 = 20, /* Revision 2.0 */ |
117 | CI_REVISION_21, /* Revision 2.1 */ |
118 | CI_REVISION_22, /* Revision 2.2 */ |
119 | CI_REVISION_23, /* Revision 2.3 */ |
120 | CI_REVISION_24, /* Revision 2.4 */ |
121 | CI_REVISION_25, /* Revision 2.5 */ |
122 | CI_REVISION_25_PLUS, /* Revision above than 2.5 */ |
123 | CI_REVISION_UNKNOWN = 99, /* Unknown Revision */ |
124 | }; |
125 | |
126 | /** |
127 | * struct ci_role_driver - host/gadget role driver |
128 | * @start: start this role |
129 | * @stop: stop this role |
130 | * @suspend: system suspend handler for this role |
131 | * @resume: system resume handler for this role |
132 | * @irq: irq handler for this role |
133 | * @name: role name string (host/gadget) |
134 | */ |
135 | struct ci_role_driver { |
136 | int (*start)(struct ci_hdrc *); |
137 | void (*stop)(struct ci_hdrc *); |
138 | void (*suspend)(struct ci_hdrc *ci); |
139 | void (*resume)(struct ci_hdrc *ci, bool power_lost); |
140 | irqreturn_t (*irq)(struct ci_hdrc *); |
141 | const char *name; |
142 | }; |
143 | |
144 | /** |
145 | * struct hw_bank - hardware register mapping representation |
146 | * @lpm: set if the device is LPM capable |
147 | * @phys: physical address of the controller's registers |
148 | * @abs: absolute address of the beginning of register window |
149 | * @cap: capability registers |
150 | * @op: operational registers |
151 | * @size: size of the register window |
152 | * @regmap: register lookup table |
153 | */ |
154 | struct hw_bank { |
155 | unsigned lpm; |
156 | resource_size_t phys; |
157 | void __iomem *abs; |
158 | void __iomem *cap; |
159 | void __iomem *op; |
160 | size_t size; |
161 | void __iomem *regmap[OP_LAST + 1]; |
162 | }; |
163 | |
164 | /** |
165 | * struct ci_hdrc - chipidea device representation |
166 | * @dev: pointer to parent device |
167 | * @lock: access synchronization |
168 | * @hw_bank: hardware register mapping |
169 | * @irq: IRQ number |
170 | * @roles: array of supported roles for this controller |
171 | * @role: current role |
172 | * @is_otg: if the device is otg-capable |
173 | * @fsm: otg finite state machine |
174 | * @otg_fsm_hrtimer: hrtimer for otg fsm timers |
175 | * @hr_timeouts: time out list for active otg fsm timers |
176 | * @enabled_otg_timer_bits: bits of enabled otg timers |
177 | * @next_otg_timer: next nearest enabled timer to be expired |
178 | * @work: work for role changing |
179 | * @wq: workqueue thread |
180 | * @qh_pool: allocation pool for queue heads |
181 | * @td_pool: allocation pool for transfer descriptors |
182 | * @gadget: device side representation for peripheral controller |
183 | * @driver: gadget driver |
184 | * @resume_state: save the state of gadget suspend from |
185 | * @hw_ep_max: total number of endpoints supported by hardware |
186 | * @ci_hw_ep: array of endpoints |
187 | * @ep0_dir: ep0 direction |
188 | * @ep0out: pointer to ep0 OUT endpoint |
189 | * @ep0in: pointer to ep0 IN endpoint |
190 | * @status: ep0 status request |
191 | * @setaddr: if we should set the address on status completion |
192 | * @address: usb address received from the host |
193 | * @remote_wakeup: host-enabled remote wakeup |
194 | * @suspended: suspended by host |
195 | * @test_mode: the selected test mode |
196 | * @platdata: platform specific information supplied by parent device |
197 | * @vbus_active: is VBUS active |
198 | * @ulpi: pointer to ULPI device, if any |
199 | * @ulpi_ops: ULPI read/write ops for this device |
200 | * @phy: pointer to PHY, if any |
201 | * @usb_phy: pointer to USB PHY, if any and if using the USB PHY framework |
202 | * @hcd: pointer to usb_hcd for ehci host driver |
203 | * @id_event: indicates there is an id event, and handled at ci_otg_work |
204 | * @b_sess_valid_event: indicates there is a vbus event, and handled |
205 | * at ci_otg_work |
206 | * @imx28_write_fix: Freescale imx28 needs swp instruction for writing |
207 | * @supports_runtime_pm: if runtime pm is supported |
208 | * @in_lpm: if the core in low power mode |
209 | * @wakeup_int: if wakeup interrupt occur |
210 | * @rev: The revision number for controller |
211 | * @mutex: protect code from concorrent running when doing role switch |
212 | */ |
213 | struct ci_hdrc { |
214 | struct device *dev; |
215 | spinlock_t lock; |
216 | struct hw_bank hw_bank; |
217 | int irq; |
218 | struct ci_role_driver *roles[CI_ROLE_END]; |
219 | enum ci_role role; |
220 | bool is_otg; |
221 | struct usb_otg otg; |
222 | struct otg_fsm fsm; |
223 | struct hrtimer otg_fsm_hrtimer; |
224 | ktime_t hr_timeouts[NUM_OTG_FSM_TIMERS]; |
225 | unsigned enabled_otg_timer_bits; |
226 | enum otg_fsm_timer next_otg_timer; |
227 | struct usb_role_switch *role_switch; |
228 | struct work_struct work; |
229 | struct workqueue_struct *wq; |
230 | |
231 | struct dma_pool *qh_pool; |
232 | struct dma_pool *td_pool; |
233 | |
234 | struct usb_gadget gadget; |
235 | struct usb_gadget_driver *driver; |
236 | enum usb_device_state resume_state; |
237 | unsigned hw_ep_max; |
238 | struct ci_hw_ep ci_hw_ep[ENDPT_MAX]; |
239 | u32 ep0_dir; |
240 | struct ci_hw_ep *ep0out, *ep0in; |
241 | |
242 | struct usb_request *status; |
243 | bool setaddr; |
244 | u8 address; |
245 | u8 remote_wakeup; |
246 | u8 suspended; |
247 | u8 test_mode; |
248 | |
249 | struct ci_hdrc_platform_data *platdata; |
250 | int vbus_active; |
251 | struct ulpi *ulpi; |
252 | struct ulpi_ops ulpi_ops; |
253 | struct phy *phy; |
254 | /* old usb_phy interface */ |
255 | struct usb_phy *usb_phy; |
256 | struct usb_hcd *hcd; |
257 | bool id_event; |
258 | bool b_sess_valid_event; |
259 | bool imx28_write_fix; |
260 | bool has_portsc_pec_bug; |
261 | bool supports_runtime_pm; |
262 | bool in_lpm; |
263 | bool wakeup_int; |
264 | enum ci_revision rev; |
265 | struct mutex mutex; |
266 | }; |
267 | |
268 | static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci) |
269 | { |
270 | BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]); |
271 | return ci->roles[ci->role]; |
272 | } |
273 | |
274 | static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role) |
275 | { |
276 | int ret; |
277 | |
278 | if (role >= CI_ROLE_END) |
279 | return -EINVAL; |
280 | |
281 | if (!ci->roles[role]) |
282 | return -ENXIO; |
283 | |
284 | ret = ci->roles[role]->start(ci); |
285 | if (ret) |
286 | return ret; |
287 | |
288 | ci->role = role; |
289 | |
290 | if (ci->usb_phy) { |
291 | if (role == CI_ROLE_HOST) |
292 | usb_phy_set_event(x: ci->usb_phy, event: USB_EVENT_ID); |
293 | else |
294 | /* in device mode but vbus is invalid*/ |
295 | usb_phy_set_event(x: ci->usb_phy, event: USB_EVENT_NONE); |
296 | } |
297 | |
298 | return ret; |
299 | } |
300 | |
301 | static inline void ci_role_stop(struct ci_hdrc *ci) |
302 | { |
303 | enum ci_role role = ci->role; |
304 | |
305 | if (role == CI_ROLE_END) |
306 | return; |
307 | |
308 | ci->role = CI_ROLE_END; |
309 | |
310 | ci->roles[role]->stop(ci); |
311 | |
312 | if (ci->usb_phy) |
313 | usb_phy_set_event(x: ci->usb_phy, event: USB_EVENT_NONE); |
314 | } |
315 | |
316 | static inline enum usb_role ci_role_to_usb_role(struct ci_hdrc *ci) |
317 | { |
318 | if (ci->role == CI_ROLE_HOST) |
319 | return USB_ROLE_HOST; |
320 | else if (ci->role == CI_ROLE_GADGET && ci->vbus_active) |
321 | return USB_ROLE_DEVICE; |
322 | else |
323 | return USB_ROLE_NONE; |
324 | } |
325 | |
326 | static inline enum ci_role usb_role_to_ci_role(enum usb_role role) |
327 | { |
328 | if (role == USB_ROLE_HOST) |
329 | return CI_ROLE_HOST; |
330 | else if (role == USB_ROLE_DEVICE) |
331 | return CI_ROLE_GADGET; |
332 | else |
333 | return CI_ROLE_END; |
334 | } |
335 | |
336 | /** |
337 | * hw_read_id_reg: reads from a identification register |
338 | * @ci: the controller |
339 | * @offset: offset from the beginning of identification registers region |
340 | * @mask: bitfield mask |
341 | * |
342 | * This function returns register contents |
343 | */ |
344 | static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask) |
345 | { |
346 | return ioread32(ci->hw_bank.abs + offset) & mask; |
347 | } |
348 | |
349 | /** |
350 | * hw_write_id_reg: writes to a identification register |
351 | * @ci: the controller |
352 | * @offset: offset from the beginning of identification registers region |
353 | * @mask: bitfield mask |
354 | * @data: new value |
355 | */ |
356 | static inline void hw_write_id_reg(struct ci_hdrc *ci, u32 offset, |
357 | u32 mask, u32 data) |
358 | { |
359 | if (~mask) |
360 | data = (ioread32(ci->hw_bank.abs + offset) & ~mask) |
361 | | (data & mask); |
362 | |
363 | iowrite32(data, ci->hw_bank.abs + offset); |
364 | } |
365 | |
366 | /** |
367 | * hw_read: reads from a hw register |
368 | * @ci: the controller |
369 | * @reg: register index |
370 | * @mask: bitfield mask |
371 | * |
372 | * This function returns register contents |
373 | */ |
374 | static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask) |
375 | { |
376 | return ioread32(ci->hw_bank.regmap[reg]) & mask; |
377 | } |
378 | |
379 | #ifdef CONFIG_SOC_IMX28 |
380 | static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr) |
381 | { |
382 | __asm__ ("swp %0, %0, [%1]" : : "r" (val), "r" (addr)); |
383 | } |
384 | #else |
385 | static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr) |
386 | { |
387 | } |
388 | #endif |
389 | |
390 | static inline void __hw_write(struct ci_hdrc *ci, u32 val, |
391 | void __iomem *addr) |
392 | { |
393 | if (ci->imx28_write_fix) |
394 | imx28_ci_writel(val, addr); |
395 | else |
396 | iowrite32(val, addr); |
397 | } |
398 | |
399 | /** |
400 | * hw_write: writes to a hw register |
401 | * @ci: the controller |
402 | * @reg: register index |
403 | * @mask: bitfield mask |
404 | * @data: new value |
405 | */ |
406 | static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg, |
407 | u32 mask, u32 data) |
408 | { |
409 | if (~mask) |
410 | data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask) |
411 | | (data & mask); |
412 | |
413 | __hw_write(ci, val: data, addr: ci->hw_bank.regmap[reg]); |
414 | } |
415 | |
416 | /** |
417 | * hw_test_and_clear: tests & clears a hw register |
418 | * @ci: the controller |
419 | * @reg: register index |
420 | * @mask: bitfield mask |
421 | * |
422 | * This function returns register contents |
423 | */ |
424 | static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg, |
425 | u32 mask) |
426 | { |
427 | u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask; |
428 | |
429 | __hw_write(ci, val, addr: ci->hw_bank.regmap[reg]); |
430 | return val; |
431 | } |
432 | |
433 | /** |
434 | * hw_test_and_write: tests & writes a hw register |
435 | * @ci: the controller |
436 | * @reg: register index |
437 | * @mask: bitfield mask |
438 | * @data: new value |
439 | * |
440 | * This function returns register contents |
441 | */ |
442 | static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg, |
443 | u32 mask, u32 data) |
444 | { |
445 | u32 val = hw_read(ci, reg, mask: ~0); |
446 | |
447 | hw_write(ci, reg, mask, data); |
448 | return (val & mask) >> __ffs(mask); |
449 | } |
450 | |
451 | /** |
452 | * ci_otg_is_fsm_mode: runtime check if otg controller |
453 | * is in otg fsm mode. |
454 | * |
455 | * @ci: chipidea device |
456 | */ |
457 | static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci) |
458 | { |
459 | #ifdef CONFIG_USB_OTG_FSM |
460 | struct usb_otg_caps *otg_caps = &ci->platdata->ci_otg_caps; |
461 | |
462 | return ci->is_otg && ci->roles[CI_ROLE_HOST] && |
463 | ci->roles[CI_ROLE_GADGET] && (otg_caps->srp_support || |
464 | otg_caps->hnp_support || otg_caps->adp_support); |
465 | #else |
466 | return false; |
467 | #endif |
468 | } |
469 | |
470 | int ci_ulpi_init(struct ci_hdrc *ci); |
471 | void ci_ulpi_exit(struct ci_hdrc *ci); |
472 | int ci_ulpi_resume(struct ci_hdrc *ci); |
473 | |
474 | u32 hw_read_intr_enable(struct ci_hdrc *ci); |
475 | |
476 | u32 hw_read_intr_status(struct ci_hdrc *ci); |
477 | |
478 | int hw_device_reset(struct ci_hdrc *ci); |
479 | |
480 | int hw_port_test_set(struct ci_hdrc *ci, u8 mode); |
481 | |
482 | u8 hw_port_test_get(struct ci_hdrc *ci); |
483 | |
484 | void hw_phymode_configure(struct ci_hdrc *ci); |
485 | |
486 | void ci_platform_configure(struct ci_hdrc *ci); |
487 | |
488 | void dbg_create_files(struct ci_hdrc *ci); |
489 | |
490 | void dbg_remove_files(struct ci_hdrc *ci); |
491 | #endif /* __DRIVERS_USB_CHIPIDEA_CI_H */ |
492 | |