1 | /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ |
2 | /* |
3 | * core.h - DesignWare HS OTG Controller common declarations |
4 | * |
5 | * Copyright (C) 2004-2013 Synopsys, Inc. |
6 | */ |
7 | |
8 | #ifndef __DWC2_CORE_H__ |
9 | #define __DWC2_CORE_H__ |
10 | |
11 | #include <linux/acpi.h> |
12 | #include <linux/phy/phy.h> |
13 | #include <linux/regulator/consumer.h> |
14 | #include <linux/usb/gadget.h> |
15 | #include <linux/usb/otg.h> |
16 | #include <linux/usb/phy.h> |
17 | #include "hw.h" |
18 | |
19 | /* |
20 | * Suggested defines for tracers: |
21 | * - no_printk: Disable tracing |
22 | * - pr_info: Print this info to the console |
23 | * - trace_printk: Print this info to trace buffer (good for verbose logging) |
24 | */ |
25 | |
26 | #define DWC2_TRACE_SCHEDULER no_printk |
27 | #define DWC2_TRACE_SCHEDULER_VB no_printk |
28 | |
29 | /* Detailed scheduler tracing, but won't overwhelm console */ |
30 | #define dwc2_sch_dbg(hsotg, fmt, ...) \ |
31 | DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \ |
32 | dev_name(hsotg->dev), ##__VA_ARGS__) |
33 | |
34 | /* Verbose scheduler tracing */ |
35 | #define dwc2_sch_vdbg(hsotg, fmt, ...) \ |
36 | DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \ |
37 | dev_name(hsotg->dev), ##__VA_ARGS__) |
38 | |
39 | /* Maximum number of Endpoints/HostChannels */ |
40 | #define MAX_EPS_CHANNELS 16 |
41 | |
42 | /* dwc2-hsotg declarations */ |
43 | static const char * const dwc2_hsotg_supply_names[] = { |
44 | "vusb_d" , /* digital USB supply, 1.2V */ |
45 | "vusb_a" , /* analog USB supply, 1.1V */ |
46 | }; |
47 | |
48 | #define DWC2_NUM_SUPPLIES ARRAY_SIZE(dwc2_hsotg_supply_names) |
49 | |
50 | /* |
51 | * EP0_MPS_LIMIT |
52 | * |
53 | * Unfortunately there seems to be a limit of the amount of data that can |
54 | * be transferred by IN transactions on EP0. This is either 127 bytes or 3 |
55 | * packets (which practically means 1 packet and 63 bytes of data) when the |
56 | * MPS is set to 64. |
57 | * |
58 | * This means if we are wanting to move >127 bytes of data, we need to |
59 | * split the transactions up, but just doing one packet at a time does |
60 | * not work (this may be an implicit DATA0 PID on first packet of the |
61 | * transaction) and doing 2 packets is outside the controller's limits. |
62 | * |
63 | * If we try to lower the MPS size for EP0, then no transfers work properly |
64 | * for EP0, and the system will fail basic enumeration. As no cause for this |
65 | * has currently been found, we cannot support any large IN transfers for |
66 | * EP0. |
67 | */ |
68 | #define EP0_MPS_LIMIT 64 |
69 | |
70 | struct dwc2_hsotg; |
71 | struct dwc2_hsotg_req; |
72 | |
73 | /** |
74 | * struct dwc2_hsotg_ep - driver endpoint definition. |
75 | * @ep: The gadget layer representation of the endpoint. |
76 | * @name: The driver generated name for the endpoint. |
77 | * @queue: Queue of requests for this endpoint. |
78 | * @parent: Reference back to the parent device structure. |
79 | * @req: The current request that the endpoint is processing. This is |
80 | * used to indicate an request has been loaded onto the endpoint |
81 | * and has yet to be completed (maybe due to data move, or simply |
82 | * awaiting an ack from the core all the data has been completed). |
83 | * @debugfs: File entry for debugfs file for this endpoint. |
84 | * @dir_in: Set to true if this endpoint is of the IN direction, which |
85 | * means that it is sending data to the Host. |
86 | * @map_dir: Set to the value of dir_in when the DMA buffer is mapped. |
87 | * @index: The index for the endpoint registers. |
88 | * @mc: Multi Count - number of transactions per microframe |
89 | * @interval: Interval for periodic endpoints, in frames or microframes. |
90 | * @name: The name array passed to the USB core. |
91 | * @halted: Set if the endpoint has been halted. |
92 | * @periodic: Set if this is a periodic ep, such as Interrupt |
93 | * @isochronous: Set if this is a isochronous ep |
94 | * @send_zlp: Set if we need to send a zero-length packet. |
95 | * @wedged: Set if ep is wedged. |
96 | * @desc_list_dma: The DMA address of descriptor chain currently in use. |
97 | * @desc_list: Pointer to descriptor DMA chain head currently in use. |
98 | * @desc_count: Count of entries within the DMA descriptor chain of EP. |
99 | * @next_desc: index of next free descriptor in the ISOC chain under SW control. |
100 | * @compl_desc: index of next descriptor to be completed by xFerComplete |
101 | * @total_data: The total number of data bytes done. |
102 | * @fifo_size: The size of the FIFO (for periodic IN endpoints) |
103 | * @fifo_index: For Dedicated FIFO operation, only FIFO0 can be used for EP0. |
104 | * @fifo_load: The amount of data loaded into the FIFO (periodic IN) |
105 | * @last_load: The offset of data for the last start of request. |
106 | * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN |
107 | * @target_frame: Targeted frame num to setup next ISOC transfer |
108 | * @frame_overrun: Indicates SOF number overrun in DSTS |
109 | * |
110 | * This is the driver's state for each registered endpoint, allowing it |
111 | * to keep track of transactions that need doing. Each endpoint has a |
112 | * lock to protect the state, to try and avoid using an overall lock |
113 | * for the host controller as much as possible. |
114 | * |
115 | * For periodic IN endpoints, we have fifo_size and fifo_load to try |
116 | * and keep track of the amount of data in the periodic FIFO for each |
117 | * of these as we don't have a status register that tells us how much |
118 | * is in each of them. (note, this may actually be useless information |
119 | * as in shared-fifo mode periodic in acts like a single-frame packet |
120 | * buffer than a fifo) |
121 | */ |
122 | struct dwc2_hsotg_ep { |
123 | struct usb_ep ep; |
124 | struct list_head queue; |
125 | struct dwc2_hsotg *parent; |
126 | struct dwc2_hsotg_req *req; |
127 | struct dentry *debugfs; |
128 | |
129 | unsigned long total_data; |
130 | unsigned int size_loaded; |
131 | unsigned int last_load; |
132 | unsigned int fifo_load; |
133 | unsigned short fifo_size; |
134 | unsigned short fifo_index; |
135 | |
136 | unsigned char dir_in; |
137 | unsigned char map_dir; |
138 | unsigned char index; |
139 | unsigned char mc; |
140 | u16 interval; |
141 | |
142 | unsigned int halted:1; |
143 | unsigned int periodic:1; |
144 | unsigned int isochronous:1; |
145 | unsigned int send_zlp:1; |
146 | unsigned int wedged:1; |
147 | unsigned int target_frame; |
148 | #define TARGET_FRAME_INITIAL 0xFFFFFFFF |
149 | bool frame_overrun; |
150 | |
151 | dma_addr_t desc_list_dma; |
152 | struct dwc2_dma_desc *desc_list; |
153 | u8 desc_count; |
154 | |
155 | unsigned int next_desc; |
156 | unsigned int compl_desc; |
157 | |
158 | char name[10]; |
159 | }; |
160 | |
161 | /** |
162 | * struct dwc2_hsotg_req - data transfer request |
163 | * @req: The USB gadget request |
164 | * @queue: The list of requests for the endpoint this is queued for. |
165 | * @saved_req_buf: variable to save req.buf when bounce buffers are used. |
166 | */ |
167 | struct dwc2_hsotg_req { |
168 | struct usb_request req; |
169 | struct list_head queue; |
170 | void *saved_req_buf; |
171 | }; |
172 | |
173 | #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ |
174 | IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) |
175 | #define call_gadget(_hs, _entry) \ |
176 | do { \ |
177 | if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ |
178 | (_hs)->driver && (_hs)->driver->_entry) { \ |
179 | spin_unlock(&_hs->lock); \ |
180 | (_hs)->driver->_entry(&(_hs)->gadget); \ |
181 | spin_lock(&_hs->lock); \ |
182 | } \ |
183 | } while (0) |
184 | #else |
185 | #define call_gadget(_hs, _entry) do {} while (0) |
186 | #endif |
187 | |
188 | struct dwc2_hsotg; |
189 | struct dwc2_host_chan; |
190 | |
191 | /* Device States */ |
192 | enum dwc2_lx_state { |
193 | DWC2_L0, /* On state */ |
194 | DWC2_L1, /* LPM sleep state */ |
195 | DWC2_L2, /* USB suspend state */ |
196 | DWC2_L3, /* Off state */ |
197 | }; |
198 | |
199 | /* Gadget ep0 states */ |
200 | enum dwc2_ep0_state { |
201 | DWC2_EP0_SETUP, |
202 | DWC2_EP0_DATA_IN, |
203 | DWC2_EP0_DATA_OUT, |
204 | DWC2_EP0_STATUS_IN, |
205 | DWC2_EP0_STATUS_OUT, |
206 | }; |
207 | |
208 | /** |
209 | * struct dwc2_core_params - Parameters for configuring the core |
210 | * |
211 | * @otg_caps: Specifies the OTG capabilities. OTG caps from the platform parameters, |
212 | * used to setup the: |
213 | * - HNP and SRP capable |
214 | * - SRP Only capable |
215 | * - No HNP/SRP capable (always available) |
216 | * Defaults to best available option |
217 | * - OTG revision number the device is compliant with, in binary-coded |
218 | * decimal (i.e. 2.0 is 0200H). (see struct usb_otg_caps) |
219 | * @host_dma: Specifies whether to use slave or DMA mode for accessing |
220 | * the data FIFOs. The driver will automatically detect the |
221 | * value for this parameter if none is specified. |
222 | * 0 - Slave (always available) |
223 | * 1 - DMA (default, if available) |
224 | * @dma_desc_enable: When DMA mode is enabled, specifies whether to use |
225 | * address DMA mode or descriptor DMA mode for accessing |
226 | * the data FIFOs. The driver will automatically detect the |
227 | * value for this if none is specified. |
228 | * 0 - Address DMA |
229 | * 1 - Descriptor DMA (default, if available) |
230 | * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use |
231 | * address DMA mode or descriptor DMA mode for accessing |
232 | * the data FIFOs in Full Speed mode only. The driver |
233 | * will automatically detect the value for this if none is |
234 | * specified. |
235 | * 0 - Address DMA |
236 | * 1 - Descriptor DMA in FS (default, if available) |
237 | * @speed: Specifies the maximum speed of operation in host and |
238 | * device mode. The actual speed depends on the speed of |
239 | * the attached device and the value of phy_type. |
240 | * 0 - High Speed |
241 | * (default when phy_type is UTMI+ or ULPI) |
242 | * 1 - Full Speed |
243 | * (default when phy_type is Full Speed) |
244 | * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters |
245 | * 1 - Allow dynamic FIFO sizing (default, if available) |
246 | * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs |
247 | * are enabled for non-periodic IN endpoints in device |
248 | * mode. |
249 | * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when |
250 | * dynamic FIFO sizing is enabled |
251 | * 16 to 32768 |
252 | * Actual maximum value is autodetected and also |
253 | * the default. |
254 | * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO |
255 | * in host mode when dynamic FIFO sizing is enabled |
256 | * 16 to 32768 |
257 | * Actual maximum value is autodetected and also |
258 | * the default. |
259 | * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in |
260 | * host mode when dynamic FIFO sizing is enabled |
261 | * 16 to 32768 |
262 | * Actual maximum value is autodetected and also |
263 | * the default. |
264 | * @max_transfer_size: The maximum transfer size supported, in bytes |
265 | * 2047 to 65,535 |
266 | * Actual maximum value is autodetected and also |
267 | * the default. |
268 | * @max_packet_count: The maximum number of packets in a transfer |
269 | * 15 to 511 |
270 | * Actual maximum value is autodetected and also |
271 | * the default. |
272 | * @host_channels: The number of host channel registers to use |
273 | * 1 to 16 |
274 | * Actual maximum value is autodetected and also |
275 | * the default. |
276 | * @phy_type: Specifies the type of PHY interface to use. By default, |
277 | * the driver will automatically detect the phy_type. |
278 | * 0 - Full Speed Phy |
279 | * 1 - UTMI+ Phy |
280 | * 2 - ULPI Phy |
281 | * Defaults to best available option (2, 1, then 0) |
282 | * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter |
283 | * is applicable for a phy_type of UTMI+ or ULPI. (For a |
284 | * ULPI phy_type, this parameter indicates the data width |
285 | * between the MAC and the ULPI Wrapper.) Also, this |
286 | * parameter is applicable only if the OTG_HSPHY_WIDTH cC |
287 | * parameter was set to "8 and 16 bits", meaning that the |
288 | * core has been configured to work at either data path |
289 | * width. |
290 | * 8 or 16 (default 16 if available) |
291 | * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single |
292 | * data rate. This parameter is only applicable if phy_type |
293 | * is ULPI. |
294 | * 0 - single data rate ULPI interface with 8 bit wide |
295 | * data bus (default) |
296 | * 1 - double data rate ULPI interface with 4 bit wide |
297 | * data bus |
298 | * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or |
299 | * external supply to drive the VBus |
300 | * 0 - Internal supply (default) |
301 | * 1 - External supply |
302 | * @i2c_enable: Specifies whether to use the I2Cinterface for a full |
303 | * speed PHY. This parameter is only applicable if phy_type |
304 | * is FS. |
305 | * 0 - No (default) |
306 | * 1 - Yes |
307 | * @ipg_isoc_en: Indicates the IPG supports is enabled or disabled. |
308 | * 0 - Disable (default) |
309 | * 1 - Enable |
310 | * @acg_enable: For enabling Active Clock Gating in the controller |
311 | * 0 - No |
312 | * 1 - Yes |
313 | * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only |
314 | * 0 - No (default) |
315 | * 1 - Yes |
316 | * @host_support_fs_ls_low_power: Specifies whether low power mode is supported |
317 | * when attached to a Full Speed or Low Speed device in |
318 | * host mode. |
319 | * 0 - Don't support low power mode (default) |
320 | * 1 - Support low power mode |
321 | * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode |
322 | * when connected to a Low Speed device in host |
323 | * mode. This parameter is applicable only if |
324 | * host_support_fs_ls_low_power is enabled. |
325 | * 0 - 48 MHz |
326 | * (default when phy_type is UTMI+ or ULPI) |
327 | * 1 - 6 MHz |
328 | * (default when phy_type is Full Speed) |
329 | * @oc_disable: Flag to disable overcurrent condition. |
330 | * 0 - Allow overcurrent condition to get detected |
331 | * 1 - Disable overcurrent condtion to get detected |
332 | * @ts_dline: Enable Term Select Dline pulsing |
333 | * 0 - No (default) |
334 | * 1 - Yes |
335 | * @reload_ctl: Allow dynamic reloading of HFIR register during runtime |
336 | * 0 - No (default for core < 2.92a) |
337 | * 1 - Yes (default for core >= 2.92a) |
338 | * @ahbcfg: This field allows the default value of the GAHBCFG |
339 | * register to be overridden |
340 | * -1 - GAHBCFG value will be set to 0x06 |
341 | * (INCR, default) |
342 | * all others - GAHBCFG value will be overridden with |
343 | * this value |
344 | * Not all bits can be controlled like this, the |
345 | * bits defined by GAHBCFG_CTRL_MASK are controlled |
346 | * by the driver and are ignored in this |
347 | * configuration value. |
348 | * @uframe_sched: True to enable the microframe scheduler |
349 | * @external_id_pin_ctl: Specifies whether ID pin is handled externally. |
350 | * Disable CONIDSTSCHNG controller interrupt in such |
351 | * case. |
352 | * 0 - No (default) |
353 | * 1 - Yes |
354 | * @power_down: Specifies whether the controller support power_down. |
355 | * If power_down is enabled, the controller will enter |
356 | * power_down in both peripheral and host mode when |
357 | * needed. |
358 | * 0 - No (default) |
359 | * 1 - Partial power down |
360 | * 2 - Hibernation |
361 | * @no_clock_gating: Specifies whether to avoid clock gating feature. |
362 | * 0 - No (use clock gating) |
363 | * 1 - Yes (avoid it) |
364 | * @lpm: Enable LPM support. |
365 | * 0 - No |
366 | * 1 - Yes |
367 | * @lpm_clock_gating: Enable core PHY clock gating. |
368 | * 0 - No |
369 | * 1 - Yes |
370 | * @besl: Enable LPM Errata support. |
371 | * 0 - No |
372 | * 1 - Yes |
373 | * @hird_threshold_en: HIRD or HIRD Threshold enable. |
374 | * 0 - No |
375 | * 1 - Yes |
376 | * @hird_threshold: Value of BESL or HIRD Threshold. |
377 | * @ref_clk_per: Indicates in terms of pico seconds the period |
378 | * of ref_clk. |
379 | * 62500 - 16MHz |
380 | * 58823 - 17MHz |
381 | * 52083 - 19.2MHz |
382 | * 50000 - 20MHz |
383 | * 41666 - 24MHz |
384 | * 33333 - 30MHz (default) |
385 | * 25000 - 40MHz |
386 | * @sof_cnt_wkup_alert: Indicates in term of number of SOF's after which |
387 | * the controller should generate an interrupt if the |
388 | * device had been in L1 state until that period. |
389 | * This is used by SW to initiate Remote WakeUp in the |
390 | * controller so as to sync to the uF number from the host. |
391 | * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO |
392 | * register. |
393 | * 0 - Deactivate the transceiver (default) |
394 | * 1 - Activate the transceiver |
395 | * @activate_stm_id_vb_detection: Activate external ID pin and Vbus level |
396 | * detection using GGPIO register. |
397 | * 0 - Deactivate the external level detection (default) |
398 | * 1 - Activate the external level detection |
399 | * @activate_ingenic_overcurrent_detection: Activate Ingenic overcurrent |
400 | * detection. |
401 | * 0 - Deactivate the overcurrent detection |
402 | * 1 - Activate the overcurrent detection (default) |
403 | * @g_dma: Enables gadget dma usage (default: autodetect). |
404 | * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect). |
405 | * @g_rx_fifo_size: The periodic rx fifo size for the device, in |
406 | * DWORDS from 16-32768 (default: 2048 if |
407 | * possible, otherwise autodetect). |
408 | * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in |
409 | * DWORDS from 16-32768 (default: 1024 if |
410 | * possible, otherwise autodetect). |
411 | * @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo |
412 | * mode. Each value corresponds to one EP |
413 | * starting from EP1 (max 15 values). Sizes are |
414 | * in DWORDS with possible values from |
415 | * 16-32768 (default: 256, 256, 256, 256, 768, |
416 | * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0). |
417 | * @change_speed_quirk: Change speed configuration to DWC2_SPEED_PARAM_FULL |
418 | * while full&low speed device connect. And change speed |
419 | * back to DWC2_SPEED_PARAM_HIGH while device is gone. |
420 | * 0 - No (default) |
421 | * 1 - Yes |
422 | * @service_interval: Enable service interval based scheduling. |
423 | * 0 - No |
424 | * 1 - Yes |
425 | * |
426 | * The following parameters may be specified when starting the module. These |
427 | * parameters define how the DWC_otg controller should be configured. A |
428 | * value of -1 (or any other out of range value) for any parameter means |
429 | * to read the value from hardware (if possible) or use the builtin |
430 | * default described above. |
431 | */ |
432 | struct dwc2_core_params { |
433 | struct usb_otg_caps otg_caps; |
434 | u8 phy_type; |
435 | #define DWC2_PHY_TYPE_PARAM_FS 0 |
436 | #define DWC2_PHY_TYPE_PARAM_UTMI 1 |
437 | #define DWC2_PHY_TYPE_PARAM_ULPI 2 |
438 | |
439 | u8 speed; |
440 | #define DWC2_SPEED_PARAM_HIGH 0 |
441 | #define DWC2_SPEED_PARAM_FULL 1 |
442 | #define DWC2_SPEED_PARAM_LOW 2 |
443 | |
444 | u8 phy_utmi_width; |
445 | bool phy_ulpi_ddr; |
446 | bool phy_ulpi_ext_vbus; |
447 | bool enable_dynamic_fifo; |
448 | bool en_multiple_tx_fifo; |
449 | bool i2c_enable; |
450 | bool acg_enable; |
451 | bool ulpi_fs_ls; |
452 | bool ts_dline; |
453 | bool reload_ctl; |
454 | bool uframe_sched; |
455 | bool external_id_pin_ctl; |
456 | |
457 | int power_down; |
458 | #define DWC2_POWER_DOWN_PARAM_NONE 0 |
459 | #define DWC2_POWER_DOWN_PARAM_PARTIAL 1 |
460 | #define DWC2_POWER_DOWN_PARAM_HIBERNATION 2 |
461 | bool no_clock_gating; |
462 | |
463 | bool lpm; |
464 | bool lpm_clock_gating; |
465 | bool besl; |
466 | bool hird_threshold_en; |
467 | bool service_interval; |
468 | u8 hird_threshold; |
469 | bool activate_stm_fs_transceiver; |
470 | bool activate_stm_id_vb_detection; |
471 | bool activate_ingenic_overcurrent_detection; |
472 | bool ipg_isoc_en; |
473 | u16 max_packet_count; |
474 | u32 max_transfer_size; |
475 | u32 ahbcfg; |
476 | |
477 | /* GREFCLK parameters */ |
478 | u32 ref_clk_per; |
479 | u16 sof_cnt_wkup_alert; |
480 | |
481 | /* Host parameters */ |
482 | bool host_dma; |
483 | bool dma_desc_enable; |
484 | bool dma_desc_fs_enable; |
485 | bool host_support_fs_ls_low_power; |
486 | bool host_ls_low_power_phy_clk; |
487 | bool oc_disable; |
488 | |
489 | u8 host_channels; |
490 | u16 host_rx_fifo_size; |
491 | u16 host_nperio_tx_fifo_size; |
492 | u16 host_perio_tx_fifo_size; |
493 | |
494 | /* Gadget parameters */ |
495 | bool g_dma; |
496 | bool g_dma_desc; |
497 | u32 g_rx_fifo_size; |
498 | u32 g_np_tx_fifo_size; |
499 | u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; |
500 | |
501 | bool change_speed_quirk; |
502 | }; |
503 | |
504 | /** |
505 | * struct dwc2_hw_params - Autodetected parameters. |
506 | * |
507 | * These parameters are the various parameters read from hardware |
508 | * registers during initialization. They typically contain the best |
509 | * supported or maximum value that can be configured in the |
510 | * corresponding dwc2_core_params value. |
511 | * |
512 | * The values that are not in dwc2_core_params are documented below. |
513 | * |
514 | * @op_mode: Mode of Operation |
515 | * 0 - HNP- and SRP-Capable OTG (Host & Device) |
516 | * 1 - SRP-Capable OTG (Host & Device) |
517 | * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) |
518 | * 3 - SRP-Capable Device |
519 | * 4 - Non-OTG Device |
520 | * 5 - SRP-Capable Host |
521 | * 6 - Non-OTG Host |
522 | * @arch: Architecture |
523 | * 0 - Slave only |
524 | * 1 - External DMA |
525 | * 2 - Internal DMA |
526 | * @ipg_isoc_en: This feature indicates that the controller supports |
527 | * the worst-case scenario of Rx followed by Rx |
528 | * Interpacket Gap (IPG) (32 bitTimes) as per the utmi |
529 | * specification for any token following ISOC OUT token. |
530 | * 0 - Don't support |
531 | * 1 - Support |
532 | * @power_optimized: Are power optimizations enabled? |
533 | * @num_dev_ep: Number of device endpoints available |
534 | * @num_dev_in_eps: Number of device IN endpoints available |
535 | * @num_dev_perio_in_ep: Number of device periodic IN endpoints |
536 | * available |
537 | * @dev_token_q_depth: Device Mode IN Token Sequence Learning Queue |
538 | * Depth |
539 | * 0 to 30 |
540 | * @host_perio_tx_q_depth: |
541 | * Host Mode Periodic Request Queue Depth |
542 | * 2, 4 or 8 |
543 | * @nperio_tx_q_depth: |
544 | * Non-Periodic Request Queue Depth |
545 | * 2, 4 or 8 |
546 | * @hs_phy_type: High-speed PHY interface type |
547 | * 0 - High-speed interface not supported |
548 | * 1 - UTMI+ |
549 | * 2 - ULPI |
550 | * 3 - UTMI+ and ULPI |
551 | * @fs_phy_type: Full-speed PHY interface type |
552 | * 0 - Full speed interface not supported |
553 | * 1 - Dedicated full speed interface |
554 | * 2 - FS pins shared with UTMI+ pins |
555 | * 3 - FS pins shared with ULPI pins |
556 | * @total_fifo_size: Total internal RAM for FIFOs (bytes) |
557 | * @hibernation: Is hibernation enabled? |
558 | * @utmi_phy_data_width: UTMI+ PHY data width |
559 | * 0 - 8 bits |
560 | * 1 - 16 bits |
561 | * 2 - 8 or 16 bits |
562 | * @snpsid: Value from SNPSID register |
563 | * @dev_ep_dirs: Direction of device endpoints (GHWCFG1) |
564 | * @g_tx_fifo_size: Power-on values of TxFIFO sizes |
565 | * @dma_desc_enable: When DMA mode is enabled, specifies whether to use |
566 | * address DMA mode or descriptor DMA mode for accessing |
567 | * the data FIFOs. The driver will automatically detect the |
568 | * value for this if none is specified. |
569 | * 0 - Address DMA |
570 | * 1 - Descriptor DMA (default, if available) |
571 | * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters |
572 | * 1 - Allow dynamic FIFO sizing (default, if available) |
573 | * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs |
574 | * are enabled for non-periodic IN endpoints in device |
575 | * mode. |
576 | * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO |
577 | * in host mode when dynamic FIFO sizing is enabled |
578 | * 16 to 32768 |
579 | * Actual maximum value is autodetected and also |
580 | * the default. |
581 | * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in |
582 | * host mode when dynamic FIFO sizing is enabled |
583 | * 16 to 32768 |
584 | * Actual maximum value is autodetected and also |
585 | * the default. |
586 | * @max_transfer_size: The maximum transfer size supported, in bytes |
587 | * 2047 to 65,535 |
588 | * Actual maximum value is autodetected and also |
589 | * the default. |
590 | * @max_packet_count: The maximum number of packets in a transfer |
591 | * 15 to 511 |
592 | * Actual maximum value is autodetected and also |
593 | * the default. |
594 | * @host_channels: The number of host channel registers to use |
595 | * 1 to 16 |
596 | * Actual maximum value is autodetected and also |
597 | * the default. |
598 | * @dev_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO |
599 | * in device mode when dynamic FIFO sizing is enabled |
600 | * 16 to 32768 |
601 | * Actual maximum value is autodetected and also |
602 | * the default. |
603 | * @i2c_enable: Specifies whether to use the I2Cinterface for a full |
604 | * speed PHY. This parameter is only applicable if phy_type |
605 | * is FS. |
606 | * 0 - No (default) |
607 | * 1 - Yes |
608 | * @acg_enable: For enabling Active Clock Gating in the controller |
609 | * 0 - Disable |
610 | * 1 - Enable |
611 | * @lpm_mode: For enabling Link Power Management in the controller |
612 | * 0 - Disable |
613 | * 1 - Enable |
614 | * @rx_fifo_size: Number of 4-byte words in the Rx FIFO when dynamic |
615 | * FIFO sizing is enabled 16 to 32768 |
616 | * Actual maximum value is autodetected and also |
617 | * the default. |
618 | * @service_interval_mode: For enabling service interval based scheduling in the |
619 | * controller. |
620 | * 0 - Disable |
621 | * 1 - Enable |
622 | */ |
623 | struct dwc2_hw_params { |
624 | unsigned op_mode:3; |
625 | unsigned arch:2; |
626 | unsigned dma_desc_enable:1; |
627 | unsigned enable_dynamic_fifo:1; |
628 | unsigned en_multiple_tx_fifo:1; |
629 | unsigned rx_fifo_size:16; |
630 | unsigned host_nperio_tx_fifo_size:16; |
631 | unsigned dev_nperio_tx_fifo_size:16; |
632 | unsigned host_perio_tx_fifo_size:16; |
633 | unsigned nperio_tx_q_depth:3; |
634 | unsigned host_perio_tx_q_depth:3; |
635 | unsigned dev_token_q_depth:5; |
636 | unsigned max_transfer_size:26; |
637 | unsigned max_packet_count:11; |
638 | unsigned host_channels:5; |
639 | unsigned hs_phy_type:2; |
640 | unsigned fs_phy_type:2; |
641 | unsigned i2c_enable:1; |
642 | unsigned acg_enable:1; |
643 | unsigned num_dev_ep:4; |
644 | unsigned num_dev_in_eps : 4; |
645 | unsigned num_dev_perio_in_ep:4; |
646 | unsigned total_fifo_size:16; |
647 | unsigned power_optimized:1; |
648 | unsigned hibernation:1; |
649 | unsigned utmi_phy_data_width:2; |
650 | unsigned lpm_mode:1; |
651 | unsigned ipg_isoc_en:1; |
652 | unsigned service_interval_mode:1; |
653 | u32 snpsid; |
654 | u32 dev_ep_dirs; |
655 | u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; |
656 | }; |
657 | |
658 | /* Size of control and EP0 buffers */ |
659 | #define DWC2_CTRL_BUFF_SIZE 8 |
660 | |
661 | /** |
662 | * struct dwc2_gregs_backup - Holds global registers state before |
663 | * entering partial power down |
664 | * @gotgctl: Backup of GOTGCTL register |
665 | * @gintmsk: Backup of GINTMSK register |
666 | * @gahbcfg: Backup of GAHBCFG register |
667 | * @gusbcfg: Backup of GUSBCFG register |
668 | * @grxfsiz: Backup of GRXFSIZ register |
669 | * @gnptxfsiz: Backup of GNPTXFSIZ register |
670 | * @gi2cctl: Backup of GI2CCTL register |
671 | * @glpmcfg: Backup of GLPMCFG register |
672 | * @gdfifocfg: Backup of GDFIFOCFG register |
673 | * @pcgcctl: Backup of PCGCCTL register |
674 | * @pcgcctl1: Backup of PCGCCTL1 register |
675 | * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint |
676 | * @gpwrdn: Backup of GPWRDN register |
677 | * @valid: True if registers values backuped. |
678 | */ |
679 | struct dwc2_gregs_backup { |
680 | u32 gotgctl; |
681 | u32 gintmsk; |
682 | u32 gahbcfg; |
683 | u32 gusbcfg; |
684 | u32 grxfsiz; |
685 | u32 gnptxfsiz; |
686 | u32 gi2cctl; |
687 | u32 glpmcfg; |
688 | u32 pcgcctl; |
689 | u32 pcgcctl1; |
690 | u32 gdfifocfg; |
691 | u32 gpwrdn; |
692 | bool valid; |
693 | }; |
694 | |
695 | /** |
696 | * struct dwc2_dregs_backup - Holds device registers state before |
697 | * entering partial power down |
698 | * @dcfg: Backup of DCFG register |
699 | * @dctl: Backup of DCTL register |
700 | * @daintmsk: Backup of DAINTMSK register |
701 | * @diepmsk: Backup of DIEPMSK register |
702 | * @doepmsk: Backup of DOEPMSK register |
703 | * @diepctl: Backup of DIEPCTL register |
704 | * @dieptsiz: Backup of DIEPTSIZ register |
705 | * @diepdma: Backup of DIEPDMA register |
706 | * @doepctl: Backup of DOEPCTL register |
707 | * @doeptsiz: Backup of DOEPTSIZ register |
708 | * @doepdma: Backup of DOEPDMA register |
709 | * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint |
710 | * @valid: True if registers values backuped. |
711 | */ |
712 | struct dwc2_dregs_backup { |
713 | u32 dcfg; |
714 | u32 dctl; |
715 | u32 daintmsk; |
716 | u32 diepmsk; |
717 | u32 doepmsk; |
718 | u32 diepctl[MAX_EPS_CHANNELS]; |
719 | u32 dieptsiz[MAX_EPS_CHANNELS]; |
720 | u32 diepdma[MAX_EPS_CHANNELS]; |
721 | u32 doepctl[MAX_EPS_CHANNELS]; |
722 | u32 doeptsiz[MAX_EPS_CHANNELS]; |
723 | u32 doepdma[MAX_EPS_CHANNELS]; |
724 | u32 dtxfsiz[MAX_EPS_CHANNELS]; |
725 | bool valid; |
726 | }; |
727 | |
728 | /** |
729 | * struct dwc2_hregs_backup - Holds host registers state before |
730 | * entering partial power down |
731 | * @hcfg: Backup of HCFG register |
732 | * @haintmsk: Backup of HAINTMSK register |
733 | * @hcintmsk: Backup of HCINTMSK register |
734 | * @hprt0: Backup of HPTR0 register |
735 | * @hfir: Backup of HFIR register |
736 | * @hptxfsiz: Backup of HPTXFSIZ register |
737 | * @valid: True if registers values backuped. |
738 | */ |
739 | struct dwc2_hregs_backup { |
740 | u32 hcfg; |
741 | u32 haintmsk; |
742 | u32 hcintmsk[MAX_EPS_CHANNELS]; |
743 | u32 hprt0; |
744 | u32 hfir; |
745 | u32 hptxfsiz; |
746 | bool valid; |
747 | }; |
748 | |
749 | /* |
750 | * Constants related to high speed periodic scheduling |
751 | * |
752 | * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a |
753 | * reservation point of view it's assumed that the schedule goes right back to |
754 | * the beginning after the end of the schedule. |
755 | * |
756 | * What does that mean for scheduling things with a long interval? It means |
757 | * we'll reserve time for them in every possible microframe that they could |
758 | * ever be scheduled in. ...but we'll still only actually schedule them as |
759 | * often as they were requested. |
760 | * |
761 | * We keep our schedule in a "bitmap" structure. This simplifies having |
762 | * to keep track of and merge intervals: we just let the bitmap code do most |
763 | * of the heavy lifting. In a way scheduling is much like memory allocation. |
764 | * |
765 | * We schedule 100us per uframe or 80% of 125us (the maximum amount you're |
766 | * supposed to schedule for periodic transfers). That's according to spec. |
767 | * |
768 | * Note that though we only schedule 80% of each microframe, the bitmap that we |
769 | * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of |
770 | * space for each uFrame). |
771 | * |
772 | * Requirements: |
773 | * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1) |
774 | * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably |
775 | * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might |
776 | * be bugs). The 8 comes from the USB spec: number of microframes per frame. |
777 | */ |
778 | #define DWC2_US_PER_UFRAME 125 |
779 | #define DWC2_HS_PERIODIC_US_PER_UFRAME 100 |
780 | |
781 | #define DWC2_HS_SCHEDULE_UFRAMES 8 |
782 | #define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \ |
783 | DWC2_HS_PERIODIC_US_PER_UFRAME) |
784 | |
785 | /* |
786 | * Constants related to low speed scheduling |
787 | * |
788 | * For high speed we schedule every 1us. For low speed that's a bit overkill, |
789 | * so we make up a unit called a "slice" that's worth 25us. There are 40 |
790 | * slices in a full frame and we can schedule 36 of those (90%) for periodic |
791 | * transfers. |
792 | * |
793 | * Our low speed schedule can be as short as 1 frame or could be longer. When |
794 | * we only schedule 1 frame it means that we'll need to reserve a time every |
795 | * frame even for things that only transfer very rarely, so something that runs |
796 | * every 2048 frames will get time reserved in every frame. Our low speed |
797 | * schedule can be longer and we'll be able to handle more overlap, but that |
798 | * will come at increased memory cost and increased time to schedule. |
799 | * |
800 | * Note: one other advantage of a short low speed schedule is that if we mess |
801 | * up and miss scheduling we can jump in and use any of the slots that we |
802 | * happened to reserve. |
803 | * |
804 | * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for |
805 | * the schedule. There will be one schedule per TT. |
806 | * |
807 | * Requirements: |
808 | * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME. |
809 | */ |
810 | #define DWC2_US_PER_SLICE 25 |
811 | #define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE) |
812 | |
813 | #define DWC2_ROUND_US_TO_SLICE(us) \ |
814 | (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \ |
815 | DWC2_US_PER_SLICE) |
816 | |
817 | #define DWC2_LS_PERIODIC_US_PER_FRAME \ |
818 | 900 |
819 | #define DWC2_LS_PERIODIC_SLICES_PER_FRAME \ |
820 | (DWC2_LS_PERIODIC_US_PER_FRAME / \ |
821 | DWC2_US_PER_SLICE) |
822 | |
823 | #define DWC2_LS_SCHEDULE_FRAMES 1 |
824 | #define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \ |
825 | DWC2_LS_PERIODIC_SLICES_PER_FRAME) |
826 | |
827 | /** |
828 | * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic |
829 | * and periodic schedules |
830 | * |
831 | * These are common for both host and peripheral modes: |
832 | * |
833 | * @dev: The struct device pointer |
834 | * @regs: Pointer to controller regs |
835 | * @hw_params: Parameters that were autodetected from the |
836 | * hardware registers |
837 | * @params: Parameters that define how the core should be configured |
838 | * @op_state: The operational State, during transitions (a_host=> |
839 | * a_peripheral and b_device=>b_host) this may not match |
840 | * the core, but allows the software to determine |
841 | * transitions |
842 | * @dr_mode: Requested mode of operation, one of following: |
843 | * - USB_DR_MODE_PERIPHERAL |
844 | * - USB_DR_MODE_HOST |
845 | * - USB_DR_MODE_OTG |
846 | * @role_sw: usb_role_switch handle |
847 | * @role_sw_default_mode: default operation mode of controller while usb role |
848 | * is USB_ROLE_NONE |
849 | * @hcd_enabled: Host mode sub-driver initialization indicator. |
850 | * @gadget_enabled: Peripheral mode sub-driver initialization indicator. |
851 | * @ll_hw_enabled: Status of low-level hardware resources. |
852 | * @hibernated: True if core is hibernated |
853 | * @in_ppd: True if core is partial power down mode. |
854 | * @bus_suspended: True if bus is suspended |
855 | * @reset_phy_on_wake: Quirk saying that we should assert PHY reset on a |
856 | * remote wakeup. |
857 | * @phy_off_for_suspend: Status of whether we turned the PHY off at suspend. |
858 | * @need_phy_for_wake: Quirk saying that we should keep the PHY on at |
859 | * suspend if we need USB to wake us up. |
860 | * @frame_number: Frame number read from the core. For both device |
861 | * and host modes. The value ranges are from 0 |
862 | * to HFNUM_MAX_FRNUM. |
863 | * @phy: The otg phy transceiver structure for phy control. |
864 | * @uphy: The otg phy transceiver structure for old USB phy |
865 | * control. |
866 | * @plat: The platform specific configuration data. This can be |
867 | * removed once all SoCs support usb transceiver. |
868 | * @supplies: Definition of USB power supplies |
869 | * @vbus_supply: Regulator supplying vbus. |
870 | * @usb33d: Optional 3.3v regulator used on some stm32 devices to |
871 | * supply ID and VBUS detection hardware. |
872 | * @lock: Spinlock that protects all the driver data structures |
873 | * @priv: Stores a pointer to the struct usb_hcd |
874 | * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth |
875 | * transfer are in process of being queued |
876 | * @srp_success: Stores status of SRP request in the case of a FS PHY |
877 | * with an I2C interface |
878 | * @wq_otg: Workqueue object used for handling of some interrupts |
879 | * @wf_otg: Work object for handling Connector ID Status Change |
880 | * interrupt |
881 | * @wkp_timer: Timer object for handling Wakeup Detected interrupt |
882 | * @lx_state: Lx state of connected device |
883 | * @gr_backup: Backup of global registers during suspend |
884 | * @dr_backup: Backup of device registers during suspend |
885 | * @hr_backup: Backup of host registers during suspend |
886 | * @needs_byte_swap: Specifies whether the opposite endianness. |
887 | * |
888 | * These are for host mode: |
889 | * |
890 | * @flags: Flags for handling root port state changes |
891 | * @flags.d32: Contain all root port flags |
892 | * @flags.b: Separate root port flags from each other |
893 | * @flags.b.port_connect_status_change: True if root port connect status |
894 | * changed |
895 | * @flags.b.port_connect_status: True if device connected to root port |
896 | * @flags.b.port_reset_change: True if root port reset status changed |
897 | * @flags.b.port_enable_change: True if root port enable status changed |
898 | * @flags.b.port_suspend_change: True if root port suspend status changed |
899 | * @flags.b.port_over_current_change: True if root port over current state |
900 | * changed. |
901 | * @flags.b.port_l1_change: True if root port l1 status changed |
902 | * @flags.b.reserved: Reserved bits of root port register |
903 | * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. |
904 | * Transfers associated with these QHs are not currently |
905 | * assigned to a host channel. |
906 | * @non_periodic_sched_active: Active QHs in the non-periodic schedule. |
907 | * Transfers associated with these QHs are currently |
908 | * assigned to a host channel. |
909 | * @non_periodic_qh_ptr: Pointer to next QH to process in the active |
910 | * non-periodic schedule |
911 | * @non_periodic_sched_waiting: Waiting QHs in the non-periodic schedule. |
912 | * Transfers associated with these QHs are not currently |
913 | * assigned to a host channel. |
914 | * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a |
915 | * list of QHs for periodic transfers that are _not_ |
916 | * scheduled for the next frame. Each QH in the list has an |
917 | * interval counter that determines when it needs to be |
918 | * scheduled for execution. This scheduling mechanism |
919 | * allows only a simple calculation for periodic bandwidth |
920 | * used (i.e. must assume that all periodic transfers may |
921 | * need to execute in the same frame). However, it greatly |
922 | * simplifies scheduling and should be sufficient for the |
923 | * vast majority of OTG hosts, which need to connect to a |
924 | * small number of peripherals at one time. Items move from |
925 | * this list to periodic_sched_ready when the QH interval |
926 | * counter is 0 at SOF. |
927 | * @periodic_sched_ready: List of periodic QHs that are ready for execution in |
928 | * the next frame, but have not yet been assigned to host |
929 | * channels. Items move from this list to |
930 | * periodic_sched_assigned as host channels become |
931 | * available during the current frame. |
932 | * @periodic_sched_assigned: List of periodic QHs to be executed in the next |
933 | * frame that are assigned to host channels. Items move |
934 | * from this list to periodic_sched_queued as the |
935 | * transactions for the QH are queued to the DWC_otg |
936 | * controller. |
937 | * @periodic_sched_queued: List of periodic QHs that have been queued for |
938 | * execution. Items move from this list to either |
939 | * periodic_sched_inactive or periodic_sched_ready when the |
940 | * channel associated with the transfer is released. If the |
941 | * interval for the QH is 1, the item moves to |
942 | * periodic_sched_ready because it must be rescheduled for |
943 | * the next frame. Otherwise, the item moves to |
944 | * periodic_sched_inactive. |
945 | * @split_order: List keeping track of channels doing splits, in order. |
946 | * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. |
947 | * This value is in microseconds per (micro)frame. The |
948 | * assumption is that all periodic transfers may occur in |
949 | * the same (micro)frame. |
950 | * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the |
951 | * host is in high speed mode; low speed schedules are |
952 | * stored elsewhere since we need one per TT. |
953 | * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for |
954 | * SOF enable/disable. |
955 | * @free_hc_list: Free host channels in the controller. This is a list of |
956 | * struct dwc2_host_chan items. |
957 | * @periodic_channels: Number of host channels assigned to periodic transfers. |
958 | * Currently assuming that there is a dedicated host |
959 | * channel for each periodic transaction and at least one |
960 | * host channel is available for non-periodic transactions. |
961 | * @non_periodic_channels: Number of host channels assigned to non-periodic |
962 | * transfers |
963 | * @available_host_channels: Number of host channels available for the |
964 | * microframe scheduler to use |
965 | * @hc_ptr_array: Array of pointers to the host channel descriptors. |
966 | * Allows accessing a host channel descriptor given the |
967 | * host channel number. This is useful in interrupt |
968 | * handlers. |
969 | * @status_buf: Buffer used for data received during the status phase of |
970 | * a control transfer. |
971 | * @status_buf_dma: DMA address for status_buf |
972 | * @start_work: Delayed work for handling host A-cable connection |
973 | * @reset_work: Delayed work for handling a port reset |
974 | * @phy_reset_work: Work structure for doing a PHY reset |
975 | * @otg_port: OTG port number |
976 | * @frame_list: Frame list |
977 | * @frame_list_dma: Frame list DMA address |
978 | * @frame_list_sz: Frame list size |
979 | * @desc_gen_cache: Kmem cache for generic descriptors |
980 | * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors |
981 | * @unaligned_cache: Kmem cache for DMA mode to handle non-aligned buf |
982 | * |
983 | * These are for peripheral mode: |
984 | * |
985 | * @driver: USB gadget driver |
986 | * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. |
987 | * @num_of_eps: Number of available EPs (excluding EP0) |
988 | * @debug_root: Root directrory for debugfs. |
989 | * @ep0_reply: Request used for ep0 reply. |
990 | * @ep0_buff: Buffer for EP0 reply data, if needed. |
991 | * @ctrl_buff: Buffer for EP0 control requests. |
992 | * @ctrl_req: Request for EP0 control packets. |
993 | * @ep0_state: EP0 control transfers state |
994 | * @delayed_status: true when gadget driver asks for delayed status |
995 | * @test_mode: USB test mode requested by the host |
996 | * @remote_wakeup_allowed: True if device is allowed to wake-up host by |
997 | * remote-wakeup signalling |
998 | * @setup_desc_dma: EP0 setup stage desc chain DMA address |
999 | * @setup_desc: EP0 setup stage desc chain pointer |
1000 | * @ctrl_in_desc_dma: EP0 IN data phase desc chain DMA address |
1001 | * @ctrl_in_desc: EP0 IN data phase desc chain pointer |
1002 | * @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address |
1003 | * @ctrl_out_desc: EP0 OUT data phase desc chain pointer |
1004 | * @irq: Interrupt request line number |
1005 | * @clk: Pointer to otg clock |
1006 | * @utmi_clk: Pointer to utmi_clk clock |
1007 | * @reset: Pointer to dwc2 reset controller |
1008 | * @reset_ecc: Pointer to dwc2 optional reset controller in Stratix10. |
1009 | * @regset: A pointer to a struct debugfs_regset32, which contains |
1010 | * a pointer to an array of register definitions, the |
1011 | * array size and the base address where the register bank |
1012 | * is to be found. |
1013 | * @last_frame_num: Number of last frame. Range from 0 to 32768 |
1014 | * @frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is |
1015 | * defined, for missed SOFs tracking. Array holds that |
1016 | * frame numbers, which not equal to last_frame_num +1 |
1017 | * @last_frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is |
1018 | * defined, for missed SOFs tracking. |
1019 | * If current_frame_number != last_frame_num+1 |
1020 | * then last_frame_num added to this array |
1021 | * @frame_num_idx: Actual size of frame_num_array and last_frame_num_array |
1022 | * @dumped_frame_num_array: 1 - if missed SOFs frame numbers dumbed |
1023 | * 0 - if missed SOFs frame numbers not dumbed |
1024 | * @fifo_mem: Total internal RAM for FIFOs (bytes) |
1025 | * @fifo_map: Each bit intend for concrete fifo. If that bit is set, |
1026 | * then that fifo is used |
1027 | * @gadget: Represents a usb gadget device |
1028 | * @connected: Used in slave mode. True if device connected with host |
1029 | * @eps_in: The IN endpoints being supplied to the gadget framework |
1030 | * @eps_out: The OUT endpoints being supplied to the gadget framework |
1031 | * @new_connection: Used in host mode. True if there are new connected |
1032 | * device |
1033 | * @enabled: Indicates the enabling state of controller |
1034 | * |
1035 | */ |
1036 | struct dwc2_hsotg { |
1037 | struct device *dev; |
1038 | void __iomem *regs; |
1039 | /** Params detected from hardware */ |
1040 | struct dwc2_hw_params hw_params; |
1041 | /** Params to actually use */ |
1042 | struct dwc2_core_params params; |
1043 | enum usb_otg_state op_state; |
1044 | enum usb_dr_mode dr_mode; |
1045 | struct usb_role_switch *role_sw; |
1046 | enum usb_dr_mode role_sw_default_mode; |
1047 | unsigned int hcd_enabled:1; |
1048 | unsigned int gadget_enabled:1; |
1049 | unsigned int ll_hw_enabled:1; |
1050 | unsigned int hibernated:1; |
1051 | unsigned int in_ppd:1; |
1052 | bool bus_suspended; |
1053 | unsigned int reset_phy_on_wake:1; |
1054 | unsigned int need_phy_for_wake:1; |
1055 | unsigned int phy_off_for_suspend:1; |
1056 | u16 frame_number; |
1057 | |
1058 | struct phy *phy; |
1059 | struct usb_phy *uphy; |
1060 | struct dwc2_hsotg_plat *plat; |
1061 | struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES]; |
1062 | struct regulator *vbus_supply; |
1063 | struct regulator *usb33d; |
1064 | |
1065 | spinlock_t lock; |
1066 | void *priv; |
1067 | int irq; |
1068 | struct clk *clk; |
1069 | struct clk *utmi_clk; |
1070 | struct reset_control *reset; |
1071 | struct reset_control *reset_ecc; |
1072 | |
1073 | unsigned int queuing_high_bandwidth:1; |
1074 | unsigned int srp_success:1; |
1075 | |
1076 | struct workqueue_struct *wq_otg; |
1077 | struct work_struct wf_otg; |
1078 | struct timer_list wkp_timer; |
1079 | enum dwc2_lx_state lx_state; |
1080 | struct dwc2_gregs_backup gr_backup; |
1081 | struct dwc2_dregs_backup dr_backup; |
1082 | struct dwc2_hregs_backup hr_backup; |
1083 | |
1084 | struct dentry *debug_root; |
1085 | struct debugfs_regset32 *regset; |
1086 | bool needs_byte_swap; |
1087 | |
1088 | /* DWC OTG HW Release versions */ |
1089 | #define DWC2_CORE_REV_2_71a 0x4f54271a |
1090 | #define DWC2_CORE_REV_2_72a 0x4f54272a |
1091 | #define DWC2_CORE_REV_2_80a 0x4f54280a |
1092 | #define DWC2_CORE_REV_2_90a 0x4f54290a |
1093 | #define DWC2_CORE_REV_2_91a 0x4f54291a |
1094 | #define DWC2_CORE_REV_2_92a 0x4f54292a |
1095 | #define DWC2_CORE_REV_2_94a 0x4f54294a |
1096 | #define DWC2_CORE_REV_3_00a 0x4f54300a |
1097 | #define DWC2_CORE_REV_3_10a 0x4f54310a |
1098 | #define DWC2_CORE_REV_4_00a 0x4f54400a |
1099 | #define DWC2_CORE_REV_4_20a 0x4f54420a |
1100 | #define DWC2_FS_IOT_REV_1_00a 0x5531100a |
1101 | #define DWC2_HS_IOT_REV_1_00a 0x5532100a |
1102 | #define DWC2_CORE_REV_MASK 0x0000ffff |
1103 | |
1104 | /* DWC OTG HW Core ID */ |
1105 | #define DWC2_OTG_ID 0x4f540000 |
1106 | #define DWC2_FS_IOT_ID 0x55310000 |
1107 | #define DWC2_HS_IOT_ID 0x55320000 |
1108 | |
1109 | #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) |
1110 | union dwc2_hcd_internal_flags { |
1111 | u32 d32; |
1112 | struct { |
1113 | unsigned port_connect_status_change:1; |
1114 | unsigned port_connect_status:1; |
1115 | unsigned port_reset_change:1; |
1116 | unsigned port_enable_change:1; |
1117 | unsigned port_suspend_change:1; |
1118 | unsigned port_over_current_change:1; |
1119 | unsigned port_l1_change:1; |
1120 | unsigned reserved:25; |
1121 | } b; |
1122 | } flags; |
1123 | |
1124 | struct list_head non_periodic_sched_inactive; |
1125 | struct list_head non_periodic_sched_waiting; |
1126 | struct list_head non_periodic_sched_active; |
1127 | struct list_head *non_periodic_qh_ptr; |
1128 | struct list_head periodic_sched_inactive; |
1129 | struct list_head periodic_sched_ready; |
1130 | struct list_head periodic_sched_assigned; |
1131 | struct list_head periodic_sched_queued; |
1132 | struct list_head split_order; |
1133 | u16 periodic_usecs; |
1134 | DECLARE_BITMAP(hs_periodic_bitmap, DWC2_HS_SCHEDULE_US); |
1135 | u16 periodic_qh_count; |
1136 | bool new_connection; |
1137 | |
1138 | u16 last_frame_num; |
1139 | |
1140 | #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS |
1141 | #define FRAME_NUM_ARRAY_SIZE 1000 |
1142 | u16 *frame_num_array; |
1143 | u16 *last_frame_num_array; |
1144 | int frame_num_idx; |
1145 | int dumped_frame_num_array; |
1146 | #endif |
1147 | |
1148 | struct list_head free_hc_list; |
1149 | int periodic_channels; |
1150 | int non_periodic_channels; |
1151 | int available_host_channels; |
1152 | struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; |
1153 | u8 *status_buf; |
1154 | dma_addr_t status_buf_dma; |
1155 | #define DWC2_HCD_STATUS_BUF_SIZE 64 |
1156 | |
1157 | struct delayed_work start_work; |
1158 | struct delayed_work reset_work; |
1159 | struct work_struct phy_reset_work; |
1160 | u8 otg_port; |
1161 | u32 *frame_list; |
1162 | dma_addr_t frame_list_dma; |
1163 | u32 frame_list_sz; |
1164 | struct kmem_cache *desc_gen_cache; |
1165 | struct kmem_cache *desc_hsisoc_cache; |
1166 | struct kmem_cache *unaligned_cache; |
1167 | #define DWC2_KMEM_UNALIGNED_BUF_SIZE 1024 |
1168 | |
1169 | #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */ |
1170 | |
1171 | #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ |
1172 | IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) |
1173 | /* Gadget structures */ |
1174 | struct usb_gadget_driver *driver; |
1175 | int fifo_mem; |
1176 | unsigned int dedicated_fifos:1; |
1177 | unsigned char num_of_eps; |
1178 | u32 fifo_map; |
1179 | |
1180 | struct usb_request *ep0_reply; |
1181 | struct usb_request *ctrl_req; |
1182 | void *ep0_buff; |
1183 | void *ctrl_buff; |
1184 | enum dwc2_ep0_state ep0_state; |
1185 | unsigned delayed_status : 1; |
1186 | u8 test_mode; |
1187 | |
1188 | dma_addr_t setup_desc_dma[2]; |
1189 | struct dwc2_dma_desc *setup_desc[2]; |
1190 | dma_addr_t ctrl_in_desc_dma; |
1191 | struct dwc2_dma_desc *ctrl_in_desc; |
1192 | dma_addr_t ctrl_out_desc_dma; |
1193 | struct dwc2_dma_desc *ctrl_out_desc; |
1194 | |
1195 | struct usb_gadget gadget; |
1196 | unsigned int enabled:1; |
1197 | unsigned int connected:1; |
1198 | unsigned int remote_wakeup_allowed:1; |
1199 | struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS]; |
1200 | struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS]; |
1201 | #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ |
1202 | }; |
1203 | |
1204 | /* Normal architectures just use readl/write */ |
1205 | static inline u32 dwc2_readl(struct dwc2_hsotg *hsotg, u32 offset) |
1206 | { |
1207 | u32 val; |
1208 | |
1209 | val = readl(addr: hsotg->regs + offset); |
1210 | if (hsotg->needs_byte_swap) |
1211 | return swab32(val); |
1212 | else |
1213 | return val; |
1214 | } |
1215 | |
1216 | static inline void dwc2_writel(struct dwc2_hsotg *hsotg, u32 value, u32 offset) |
1217 | { |
1218 | if (hsotg->needs_byte_swap) |
1219 | writel(swab32(value), addr: hsotg->regs + offset); |
1220 | else |
1221 | writel(val: value, addr: hsotg->regs + offset); |
1222 | |
1223 | #ifdef DWC2_LOG_WRITES |
1224 | pr_info("info:: wrote %08x to %p\n" , value, hsotg->regs + offset); |
1225 | #endif |
1226 | } |
1227 | |
1228 | static inline void dwc2_readl_rep(struct dwc2_hsotg *hsotg, u32 offset, |
1229 | void *buffer, unsigned int count) |
1230 | { |
1231 | if (count) { |
1232 | u32 *buf = buffer; |
1233 | |
1234 | do { |
1235 | u32 x = dwc2_readl(hsotg, offset); |
1236 | *buf++ = x; |
1237 | } while (--count); |
1238 | } |
1239 | } |
1240 | |
1241 | static inline void dwc2_writel_rep(struct dwc2_hsotg *hsotg, u32 offset, |
1242 | const void *buffer, unsigned int count) |
1243 | { |
1244 | if (count) { |
1245 | const u32 *buf = buffer; |
1246 | |
1247 | do { |
1248 | dwc2_writel(hsotg, value: *buf++, offset); |
1249 | } while (--count); |
1250 | } |
1251 | } |
1252 | |
1253 | /* Reasons for halting a host channel */ |
1254 | enum dwc2_halt_status { |
1255 | DWC2_HC_XFER_NO_HALT_STATUS, |
1256 | DWC2_HC_XFER_COMPLETE, |
1257 | DWC2_HC_XFER_URB_COMPLETE, |
1258 | DWC2_HC_XFER_ACK, |
1259 | DWC2_HC_XFER_NAK, |
1260 | DWC2_HC_XFER_NYET, |
1261 | DWC2_HC_XFER_STALL, |
1262 | DWC2_HC_XFER_XACT_ERR, |
1263 | DWC2_HC_XFER_FRAME_OVERRUN, |
1264 | DWC2_HC_XFER_BABBLE_ERR, |
1265 | DWC2_HC_XFER_DATA_TOGGLE_ERR, |
1266 | DWC2_HC_XFER_AHB_ERR, |
1267 | DWC2_HC_XFER_PERIODIC_INCOMPLETE, |
1268 | DWC2_HC_XFER_URB_DEQUEUE, |
1269 | }; |
1270 | |
1271 | /* Core version information */ |
1272 | static inline bool dwc2_is_iot(struct dwc2_hsotg *hsotg) |
1273 | { |
1274 | return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000; |
1275 | } |
1276 | |
1277 | static inline bool dwc2_is_fs_iot(struct dwc2_hsotg *hsotg) |
1278 | { |
1279 | return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000; |
1280 | } |
1281 | |
1282 | static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg) |
1283 | { |
1284 | return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000; |
1285 | } |
1286 | |
1287 | /* |
1288 | * The following functions support initialization of the core driver component |
1289 | * and the DWC_otg controller |
1290 | */ |
1291 | int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait); |
1292 | int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg); |
1293 | int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, int rem_wakeup, |
1294 | bool restore); |
1295 | int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host); |
1296 | int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup, |
1297 | int reset, int is_host); |
1298 | void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg); |
1299 | int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy); |
1300 | |
1301 | void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host); |
1302 | void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg); |
1303 | |
1304 | bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); |
1305 | |
1306 | int dwc2_check_core_version(struct dwc2_hsotg *hsotg); |
1307 | |
1308 | /* |
1309 | * Common core Functions. |
1310 | * The following functions support managing the DWC_otg controller in either |
1311 | * device or host mode. |
1312 | */ |
1313 | void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); |
1314 | void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); |
1315 | void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); |
1316 | |
1317 | void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); |
1318 | void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); |
1319 | |
1320 | void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup, |
1321 | int is_host); |
1322 | int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg); |
1323 | int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg); |
1324 | |
1325 | void dwc2_enable_acg(struct dwc2_hsotg *hsotg); |
1326 | |
1327 | /* This function should be called on every hardware interrupt. */ |
1328 | irqreturn_t dwc2_handle_common_intr(int irq, void *dev); |
1329 | |
1330 | /* The device ID match table */ |
1331 | extern const struct of_device_id dwc2_of_match_table[]; |
1332 | extern const struct acpi_device_id dwc2_acpi_match[]; |
1333 | extern const struct pci_device_id dwc2_pci_ids[]; |
1334 | |
1335 | int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg); |
1336 | int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg); |
1337 | |
1338 | /* Common polling functions */ |
1339 | int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit, |
1340 | u32 timeout); |
1341 | int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit, |
1342 | u32 timeout); |
1343 | /* Parameters */ |
1344 | int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); |
1345 | int dwc2_init_params(struct dwc2_hsotg *hsotg); |
1346 | |
1347 | /* |
1348 | * The following functions check the controller's OTG operation mode |
1349 | * capability (GHWCFG2.OTG_MODE). |
1350 | * |
1351 | * These functions can be used before the internal hsotg->hw_params |
1352 | * are read in and cached so they always read directly from the |
1353 | * GHWCFG2 register. |
1354 | */ |
1355 | unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg); |
1356 | bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg); |
1357 | bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg); |
1358 | bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg); |
1359 | |
1360 | /* |
1361 | * Returns the mode of operation, host or device |
1362 | */ |
1363 | static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) |
1364 | { |
1365 | return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) != 0; |
1366 | } |
1367 | |
1368 | static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) |
1369 | { |
1370 | return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) == 0; |
1371 | } |
1372 | |
1373 | int dwc2_drd_init(struct dwc2_hsotg *hsotg); |
1374 | void dwc2_drd_suspend(struct dwc2_hsotg *hsotg); |
1375 | void dwc2_drd_resume(struct dwc2_hsotg *hsotg); |
1376 | void dwc2_drd_exit(struct dwc2_hsotg *hsotg); |
1377 | |
1378 | /* |
1379 | * Dump core registers and SPRAM |
1380 | */ |
1381 | void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); |
1382 | void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); |
1383 | void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); |
1384 | |
1385 | /* Gadget defines */ |
1386 | #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ |
1387 | IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) |
1388 | int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg); |
1389 | int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2); |
1390 | int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2); |
1391 | int dwc2_gadget_init(struct dwc2_hsotg *hsotg); |
1392 | void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, |
1393 | bool reset); |
1394 | void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg); |
1395 | void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg); |
1396 | void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2); |
1397 | int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode); |
1398 | #define dwc2_is_device_connected(hsotg) (hsotg->connected) |
1399 | #define dwc2_is_device_enabled(hsotg) (hsotg->enabled) |
1400 | int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg); |
1401 | int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup); |
1402 | int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg); |
1403 | int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, |
1404 | int rem_wakeup, int reset); |
1405 | int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg); |
1406 | int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg, |
1407 | bool restore); |
1408 | void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg); |
1409 | void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg, |
1410 | int rem_wakeup); |
1411 | int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg); |
1412 | int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg); |
1413 | int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg); |
1414 | void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg); |
1415 | void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg); |
1416 | static inline void dwc2_clear_fifo_map(struct dwc2_hsotg *hsotg) |
1417 | { hsotg->fifo_map = 0; } |
1418 | #else |
1419 | static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2) |
1420 | { return 0; } |
1421 | static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2) |
1422 | { return 0; } |
1423 | static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2) |
1424 | { return 0; } |
1425 | static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg) |
1426 | { return 0; } |
1427 | static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, |
1428 | bool reset) {} |
1429 | static inline void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) {} |
1430 | static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {} |
1431 | static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {} |
1432 | static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, |
1433 | int testmode) |
1434 | { return 0; } |
1435 | #define dwc2_is_device_connected(hsotg) (0) |
1436 | #define dwc2_is_device_enabled(hsotg) (0) |
1437 | static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) |
1438 | { return 0; } |
1439 | static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, |
1440 | int remote_wakeup) |
1441 | { return 0; } |
1442 | static inline int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg) |
1443 | { return 0; } |
1444 | static inline int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, |
1445 | int rem_wakeup, int reset) |
1446 | { return 0; } |
1447 | static inline int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg) |
1448 | { return 0; } |
1449 | static inline int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg, |
1450 | bool restore) |
1451 | { return 0; } |
1452 | static inline void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg) {} |
1453 | static inline void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg, |
1454 | int rem_wakeup) {} |
1455 | static inline int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg) |
1456 | { return 0; } |
1457 | static inline int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg) |
1458 | { return 0; } |
1459 | static inline int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg) |
1460 | { return 0; } |
1461 | static inline void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) {} |
1462 | static inline void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg) {} |
1463 | static inline void dwc2_clear_fifo_map(struct dwc2_hsotg *hsotg) {} |
1464 | #endif |
1465 | |
1466 | #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) |
1467 | int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); |
1468 | int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us); |
1469 | void dwc2_hcd_connect(struct dwc2_hsotg *hsotg); |
1470 | void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force); |
1471 | void dwc2_hcd_start(struct dwc2_hsotg *hsotg); |
1472 | int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup); |
1473 | int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex); |
1474 | int dwc2_port_resume(struct dwc2_hsotg *hsotg); |
1475 | int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg); |
1476 | int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg); |
1477 | int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg); |
1478 | int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, |
1479 | int rem_wakeup, int reset); |
1480 | int dwc2_host_enter_partial_power_down(struct dwc2_hsotg *hsotg); |
1481 | int dwc2_host_exit_partial_power_down(struct dwc2_hsotg *hsotg, |
1482 | int rem_wakeup, bool restore); |
1483 | void dwc2_host_enter_clock_gating(struct dwc2_hsotg *hsotg); |
1484 | void dwc2_host_exit_clock_gating(struct dwc2_hsotg *hsotg, int rem_wakeup); |
1485 | bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2); |
1486 | static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg) |
1487 | { schedule_work(work: &hsotg->phy_reset_work); } |
1488 | #else |
1489 | static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) |
1490 | { return 0; } |
1491 | static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, |
1492 | int us) |
1493 | { return 0; } |
1494 | static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {} |
1495 | static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {} |
1496 | static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {} |
1497 | static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {} |
1498 | static inline int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup) |
1499 | { return 0; } |
1500 | static inline int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) |
1501 | { return 0; } |
1502 | static inline int dwc2_port_resume(struct dwc2_hsotg *hsotg) |
1503 | { return 0; } |
1504 | static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg) |
1505 | { return 0; } |
1506 | static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) |
1507 | { return 0; } |
1508 | static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) |
1509 | { return 0; } |
1510 | static inline int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg) |
1511 | { return 0; } |
1512 | static inline int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, |
1513 | int rem_wakeup, int reset) |
1514 | { return 0; } |
1515 | static inline int dwc2_host_enter_partial_power_down(struct dwc2_hsotg *hsotg) |
1516 | { return 0; } |
1517 | static inline int dwc2_host_exit_partial_power_down(struct dwc2_hsotg *hsotg, |
1518 | int rem_wakeup, bool restore) |
1519 | { return 0; } |
1520 | static inline void dwc2_host_enter_clock_gating(struct dwc2_hsotg *hsotg) {} |
1521 | static inline void dwc2_host_exit_clock_gating(struct dwc2_hsotg *hsotg, |
1522 | int rem_wakeup) {} |
1523 | static inline bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2) |
1524 | { return false; } |
1525 | static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg) {} |
1526 | |
1527 | #endif |
1528 | |
1529 | #endif /* __DWC2_CORE_H__ */ |
1530 | |