1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * core.h - DesignWare USB3 DRD Core Header |
4 | * |
5 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com |
6 | * |
7 | * Authors: Felipe Balbi <balbi@ti.com>, |
8 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> |
9 | */ |
10 | |
11 | #ifndef __DRIVERS_USB_DWC3_CORE_H |
12 | #define __DRIVERS_USB_DWC3_CORE_H |
13 | |
14 | #include <linux/device.h> |
15 | #include <linux/spinlock.h> |
16 | #include <linux/mutex.h> |
17 | #include <linux/ioport.h> |
18 | #include <linux/list.h> |
19 | #include <linux/bitops.h> |
20 | #include <linux/dma-mapping.h> |
21 | #include <linux/mm.h> |
22 | #include <linux/debugfs.h> |
23 | #include <linux/wait.h> |
24 | #include <linux/workqueue.h> |
25 | |
26 | #include <linux/usb/ch9.h> |
27 | #include <linux/usb/gadget.h> |
28 | #include <linux/usb/otg.h> |
29 | #include <linux/usb/role.h> |
30 | #include <linux/ulpi/interface.h> |
31 | |
32 | #include <linux/phy/phy.h> |
33 | |
34 | #include <linux/power_supply.h> |
35 | |
36 | #define DWC3_MSG_MAX 500 |
37 | |
38 | /* Global constants */ |
39 | #define DWC3_PULL_UP_TIMEOUT 500 /* ms */ |
40 | #define DWC3_BOUNCE_SIZE 1024 /* size of a superspeed bulk */ |
41 | #define DWC3_EP0_SETUP_SIZE 512 |
42 | #define DWC3_ENDPOINTS_NUM 32 |
43 | #define DWC3_XHCI_RESOURCES_NUM 2 |
44 | #define DWC3_ISOC_MAX_RETRIES 5 |
45 | |
46 | #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ |
47 | #define DWC3_EVENT_BUFFERS_SIZE 4096 |
48 | #define DWC3_EVENT_TYPE_MASK 0xfe |
49 | |
50 | #define DWC3_EVENT_TYPE_DEV 0 |
51 | #define DWC3_EVENT_TYPE_CARKIT 3 |
52 | #define DWC3_EVENT_TYPE_I2C 4 |
53 | |
54 | #define DWC3_DEVICE_EVENT_DISCONNECT 0 |
55 | #define DWC3_DEVICE_EVENT_RESET 1 |
56 | #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 |
57 | #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 |
58 | #define DWC3_DEVICE_EVENT_WAKEUP 4 |
59 | #define DWC3_DEVICE_EVENT_HIBER_REQ 5 |
60 | #define DWC3_DEVICE_EVENT_SUSPEND 6 |
61 | #define DWC3_DEVICE_EVENT_SOF 7 |
62 | #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 |
63 | #define DWC3_DEVICE_EVENT_CMD_CMPL 10 |
64 | #define DWC3_DEVICE_EVENT_OVERFLOW 11 |
65 | |
66 | /* Controller's role while using the OTG block */ |
67 | #define DWC3_OTG_ROLE_IDLE 0 |
68 | #define DWC3_OTG_ROLE_HOST 1 |
69 | #define DWC3_OTG_ROLE_DEVICE 2 |
70 | |
71 | #define DWC3_GEVNTCOUNT_MASK 0xfffc |
72 | #define DWC3_GEVNTCOUNT_EHB BIT(31) |
73 | #define DWC3_GSNPSID_MASK 0xffff0000 |
74 | #define DWC3_GSNPSREV_MASK 0xffff |
75 | #define DWC3_GSNPS_ID(p) (((p) & DWC3_GSNPSID_MASK) >> 16) |
76 | |
77 | /* DWC3 registers memory space boundries */ |
78 | #define DWC3_XHCI_REGS_START 0x0 |
79 | #define DWC3_XHCI_REGS_END 0x7fff |
80 | #define DWC3_GLOBALS_REGS_START 0xc100 |
81 | #define DWC3_GLOBALS_REGS_END 0xc6ff |
82 | #define DWC3_DEVICE_REGS_START 0xc700 |
83 | #define DWC3_DEVICE_REGS_END 0xcbff |
84 | #define DWC3_OTG_REGS_START 0xcc00 |
85 | #define DWC3_OTG_REGS_END 0xccff |
86 | |
87 | #define DWC3_RTK_RTD_GLOBALS_REGS_START 0x8100 |
88 | |
89 | /* Global Registers */ |
90 | #define DWC3_GSBUSCFG0 0xc100 |
91 | #define DWC3_GSBUSCFG1 0xc104 |
92 | #define DWC3_GTXTHRCFG 0xc108 |
93 | #define DWC3_GRXTHRCFG 0xc10c |
94 | #define DWC3_GCTL 0xc110 |
95 | #define DWC3_GEVTEN 0xc114 |
96 | #define DWC3_GSTS 0xc118 |
97 | #define DWC3_GUCTL1 0xc11c |
98 | #define DWC3_GSNPSID 0xc120 |
99 | #define DWC3_GGPIO 0xc124 |
100 | #define DWC3_GUID 0xc128 |
101 | #define DWC3_GUCTL 0xc12c |
102 | #define DWC3_GBUSERRADDR0 0xc130 |
103 | #define DWC3_GBUSERRADDR1 0xc134 |
104 | #define DWC3_GPRTBIMAP0 0xc138 |
105 | #define DWC3_GPRTBIMAP1 0xc13c |
106 | #define DWC3_GHWPARAMS0 0xc140 |
107 | #define DWC3_GHWPARAMS1 0xc144 |
108 | #define DWC3_GHWPARAMS2 0xc148 |
109 | #define DWC3_GHWPARAMS3 0xc14c |
110 | #define DWC3_GHWPARAMS4 0xc150 |
111 | #define DWC3_GHWPARAMS5 0xc154 |
112 | #define DWC3_GHWPARAMS6 0xc158 |
113 | #define DWC3_GHWPARAMS7 0xc15c |
114 | #define DWC3_GDBGFIFOSPACE 0xc160 |
115 | #define DWC3_GDBGLTSSM 0xc164 |
116 | #define DWC3_GDBGBMU 0xc16c |
117 | #define DWC3_GDBGLSPMUX 0xc170 |
118 | #define DWC3_GDBGLSP 0xc174 |
119 | #define DWC3_GDBGEPINFO0 0xc178 |
120 | #define DWC3_GDBGEPINFO1 0xc17c |
121 | #define DWC3_GPRTBIMAP_HS0 0xc180 |
122 | #define DWC3_GPRTBIMAP_HS1 0xc184 |
123 | #define DWC3_GPRTBIMAP_FS0 0xc188 |
124 | #define DWC3_GPRTBIMAP_FS1 0xc18c |
125 | #define DWC3_GUCTL2 0xc19c |
126 | |
127 | #define DWC3_VER_NUMBER 0xc1a0 |
128 | #define DWC3_VER_TYPE 0xc1a4 |
129 | |
130 | #define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 0x04)) |
131 | #define DWC3_GUSB2I2CCTL(n) (0xc240 + ((n) * 0x04)) |
132 | |
133 | #define DWC3_GUSB2PHYACC(n) (0xc280 + ((n) * 0x04)) |
134 | |
135 | #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 0x04)) |
136 | |
137 | #define DWC3_GTXFIFOSIZ(n) (0xc300 + ((n) * 0x04)) |
138 | #define DWC3_GRXFIFOSIZ(n) (0xc380 + ((n) * 0x04)) |
139 | |
140 | #define DWC3_GEVNTADRLO(n) (0xc400 + ((n) * 0x10)) |
141 | #define DWC3_GEVNTADRHI(n) (0xc404 + ((n) * 0x10)) |
142 | #define DWC3_GEVNTSIZ(n) (0xc408 + ((n) * 0x10)) |
143 | #define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10)) |
144 | |
145 | #define DWC3_GHWPARAMS8 0xc600 |
146 | #define DWC3_GUCTL3 0xc60c |
147 | #define DWC3_GFLADJ 0xc630 |
148 | #define DWC3_GHWPARAMS9 0xc6e0 |
149 | |
150 | /* Device Registers */ |
151 | #define DWC3_DCFG 0xc700 |
152 | #define DWC3_DCTL 0xc704 |
153 | #define DWC3_DEVTEN 0xc708 |
154 | #define DWC3_DSTS 0xc70c |
155 | #define DWC3_DGCMDPAR 0xc710 |
156 | #define DWC3_DGCMD 0xc714 |
157 | #define DWC3_DALEPENA 0xc720 |
158 | #define DWC3_DCFG1 0xc740 /* DWC_usb32 only */ |
159 | |
160 | #define DWC3_DEP_BASE(n) (0xc800 + ((n) * 0x10)) |
161 | #define DWC3_DEPCMDPAR2 0x00 |
162 | #define DWC3_DEPCMDPAR1 0x04 |
163 | #define DWC3_DEPCMDPAR0 0x08 |
164 | #define DWC3_DEPCMD 0x0c |
165 | |
166 | #define DWC3_DEV_IMOD(n) (0xca00 + ((n) * 0x4)) |
167 | |
168 | /* OTG Registers */ |
169 | #define DWC3_OCFG 0xcc00 |
170 | #define DWC3_OCTL 0xcc04 |
171 | #define DWC3_OEVT 0xcc08 |
172 | #define DWC3_OEVTEN 0xcc0C |
173 | #define DWC3_OSTS 0xcc10 |
174 | |
175 | /* Bit fields */ |
176 | |
177 | /* Global SoC Bus Configuration INCRx Register 0 */ |
178 | #define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */ |
179 | #define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */ |
180 | #define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */ |
181 | #define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */ |
182 | #define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */ |
183 | #define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */ |
184 | #define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */ |
185 | #define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */ |
186 | #define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff |
187 | |
188 | /* Global Debug LSP MUX Select */ |
189 | #define DWC3_GDBGLSPMUX_ENDBC BIT(15) /* Host only */ |
190 | #define DWC3_GDBGLSPMUX_HOSTSELECT(n) ((n) & 0x3fff) |
191 | #define DWC3_GDBGLSPMUX_DEVSELECT(n) (((n) & 0xf) << 4) |
192 | #define DWC3_GDBGLSPMUX_EPSELECT(n) ((n) & 0xf) |
193 | |
194 | /* Global Debug Queue/FIFO Space Available Register */ |
195 | #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f) |
196 | #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0) |
197 | #define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff) |
198 | |
199 | #define DWC3_TXFIFO 0 |
200 | #define DWC3_RXFIFO 1 |
201 | #define DWC3_TXREQQ 2 |
202 | #define DWC3_RXREQQ 3 |
203 | #define DWC3_RXINFOQ 4 |
204 | #define DWC3_PSTATQ 5 |
205 | #define DWC3_DESCFETCHQ 6 |
206 | #define DWC3_EVENTQ 7 |
207 | #define DWC3_AUXEVENTQ 8 |
208 | |
209 | /* Global RX Threshold Configuration Register */ |
210 | #define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19) |
211 | #define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24) |
212 | #define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29) |
213 | |
214 | /* Global TX Threshold Configuration Register */ |
215 | #define DWC3_GTXTHRCFG_MAXTXBURSTSIZE(n) (((n) & 0xff) << 16) |
216 | #define DWC3_GTXTHRCFG_TXPKTCNT(n) (((n) & 0xf) << 24) |
217 | #define DWC3_GTXTHRCFG_PKTCNTSEL BIT(29) |
218 | |
219 | /* Global RX Threshold Configuration Register for DWC_usb31 only */ |
220 | #define DWC31_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 16) |
221 | #define DWC31_GRXTHRCFG_RXPKTCNT(n) (((n) & 0x1f) << 21) |
222 | #define DWC31_GRXTHRCFG_PKTCNTSEL BIT(26) |
223 | #define DWC31_RXTHRNUMPKTSEL_HS_PRD BIT(15) |
224 | #define DWC31_RXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13) |
225 | #define DWC31_RXTHRNUMPKTSEL_PRD BIT(10) |
226 | #define DWC31_RXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5) |
227 | #define DWC31_MAXRXBURSTSIZE_PRD(n) ((n) & 0x1f) |
228 | |
229 | /* Global TX Threshold Configuration Register for DWC_usb31 only */ |
230 | #define DWC31_GTXTHRCFG_MAXTXBURSTSIZE(n) (((n) & 0x1f) << 16) |
231 | #define DWC31_GTXTHRCFG_TXPKTCNT(n) (((n) & 0x1f) << 21) |
232 | #define DWC31_GTXTHRCFG_PKTCNTSEL BIT(26) |
233 | #define DWC31_TXTHRNUMPKTSEL_HS_PRD BIT(15) |
234 | #define DWC31_TXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13) |
235 | #define DWC31_TXTHRNUMPKTSEL_PRD BIT(10) |
236 | #define DWC31_TXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5) |
237 | #define DWC31_MAXTXBURSTSIZE_PRD(n) ((n) & 0x1f) |
238 | |
239 | /* Global Configuration Register */ |
240 | #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) |
241 | #define DWC3_GCTL_PWRDNSCALE_MASK GENMASK(31, 19) |
242 | #define DWC3_GCTL_U2RSTECN BIT(16) |
243 | #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) |
244 | #define DWC3_GCTL_CLK_BUS (0) |
245 | #define DWC3_GCTL_CLK_PIPE (1) |
246 | #define DWC3_GCTL_CLK_PIPEHALF (2) |
247 | #define DWC3_GCTL_CLK_MASK (3) |
248 | |
249 | #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) |
250 | #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) |
251 | #define DWC3_GCTL_PRTCAP_HOST 1 |
252 | #define DWC3_GCTL_PRTCAP_DEVICE 2 |
253 | #define DWC3_GCTL_PRTCAP_OTG 3 |
254 | |
255 | #define DWC3_GCTL_CORESOFTRESET BIT(11) |
256 | #define DWC3_GCTL_SOFITPSYNC BIT(10) |
257 | #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) |
258 | #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) |
259 | #define DWC3_GCTL_DISSCRAMBLE BIT(3) |
260 | #define DWC3_GCTL_U2EXIT_LFPS BIT(2) |
261 | #define DWC3_GCTL_GBLHIBERNATIONEN BIT(1) |
262 | #define DWC3_GCTL_DSBLCLKGTNG BIT(0) |
263 | |
264 | /* Global User Control 1 Register */ |
265 | #define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT BIT(31) |
266 | #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28) |
267 | #define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK BIT(26) |
268 | #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24) |
269 | #define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17) |
270 | #define DWC3_GUCTL1_PARKMODE_DISABLE_HS BIT(16) |
271 | #define DWC3_GUCTL1_RESUME_OPMODE_HS_HOST BIT(10) |
272 | |
273 | /* Global Status Register */ |
274 | #define DWC3_GSTS_OTG_IP BIT(10) |
275 | #define DWC3_GSTS_BC_IP BIT(9) |
276 | #define DWC3_GSTS_ADP_IP BIT(8) |
277 | #define DWC3_GSTS_HOST_IP BIT(7) |
278 | #define DWC3_GSTS_DEVICE_IP BIT(6) |
279 | #define DWC3_GSTS_CSR_TIMEOUT BIT(5) |
280 | #define DWC3_GSTS_BUS_ERR_ADDR_VLD BIT(4) |
281 | #define DWC3_GSTS_CURMOD(n) ((n) & 0x3) |
282 | #define DWC3_GSTS_CURMOD_DEVICE 0 |
283 | #define DWC3_GSTS_CURMOD_HOST 1 |
284 | |
285 | /* Global USB2 PHY Configuration Register */ |
286 | #define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31) |
287 | #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS BIT(30) |
288 | #define DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV BIT(17) |
289 | #define DWC3_GUSB2PHYCFG_SUSPHY BIT(6) |
290 | #define DWC3_GUSB2PHYCFG_ULPI_UTMI BIT(4) |
291 | #define DWC3_GUSB2PHYCFG_ENBLSLPM BIT(8) |
292 | #define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3) |
293 | #define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) |
294 | #define DWC3_GUSB2PHYCFG_USBTRDTIM(n) (n << 10) |
295 | #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) |
296 | #define USBTRDTIM_UTMI_8_BIT 9 |
297 | #define USBTRDTIM_UTMI_16_BIT 5 |
298 | #define UTMI_PHYIF_16_BIT 1 |
299 | #define UTMI_PHYIF_8_BIT 0 |
300 | |
301 | /* Global USB2 PHY Vendor Control Register */ |
302 | #define DWC3_GUSB2PHYACC_NEWREGREQ BIT(25) |
303 | #define DWC3_GUSB2PHYACC_DONE BIT(24) |
304 | #define DWC3_GUSB2PHYACC_BUSY BIT(23) |
305 | #define DWC3_GUSB2PHYACC_WRITE BIT(22) |
306 | #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16) |
307 | #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8) |
308 | #define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff) |
309 | |
310 | /* Global USB3 PIPE Control Register */ |
311 | #define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT(31) |
312 | #define DWC3_GUSB3PIPECTL_U2SSINP3OK BIT(29) |
313 | #define DWC3_GUSB3PIPECTL_DISRXDETINP3 BIT(28) |
314 | #define DWC3_GUSB3PIPECTL_UX_EXIT_PX BIT(27) |
315 | #define DWC3_GUSB3PIPECTL_REQP1P2P3 BIT(24) |
316 | #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19) |
317 | #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7) |
318 | #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1) |
319 | #define DWC3_GUSB3PIPECTL_DEPOCHANGE BIT(18) |
320 | #define DWC3_GUSB3PIPECTL_SUSPHY BIT(17) |
321 | #define DWC3_GUSB3PIPECTL_LFPSFILT BIT(9) |
322 | #define DWC3_GUSB3PIPECTL_RX_DETOPOLL BIT(8) |
323 | #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3) |
324 | #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1) |
325 | |
326 | /* Global TX Fifo Size Register */ |
327 | #define DWC31_GTXFIFOSIZ_TXFRAMNUM BIT(15) /* DWC_usb31 only */ |
328 | #define DWC31_GTXFIFOSIZ_TXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */ |
329 | #define DWC3_GTXFIFOSIZ_TXFDEP(n) ((n) & 0xffff) |
330 | #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) |
331 | |
332 | /* Global RX Fifo Size Register */ |
333 | #define DWC31_GRXFIFOSIZ_RXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */ |
334 | #define DWC3_GRXFIFOSIZ_RXFDEP(n) ((n) & 0xffff) |
335 | |
336 | /* Global Event Size Registers */ |
337 | #define DWC3_GEVNTSIZ_INTMASK BIT(31) |
338 | #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) |
339 | |
340 | /* Global HWPARAMS0 Register */ |
341 | #define DWC3_GHWPARAMS0_MODE(n) ((n) & 0x3) |
342 | #define DWC3_GHWPARAMS0_MODE_GADGET 0 |
343 | #define DWC3_GHWPARAMS0_MODE_HOST 1 |
344 | #define DWC3_GHWPARAMS0_MODE_DRD 2 |
345 | #define DWC3_GHWPARAMS0_MBUS_TYPE(n) (((n) >> 3) & 0x7) |
346 | #define DWC3_GHWPARAMS0_SBUS_TYPE(n) (((n) >> 6) & 0x3) |
347 | #define DWC3_GHWPARAMS0_MDWIDTH(n) (((n) >> 8) & 0xff) |
348 | #define DWC3_GHWPARAMS0_SDWIDTH(n) (((n) >> 16) & 0xff) |
349 | #define DWC3_GHWPARAMS0_AWIDTH(n) (((n) >> 24) & 0xff) |
350 | |
351 | /* Global HWPARAMS1 Register */ |
352 | #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) |
353 | #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 |
354 | #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 |
355 | #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 |
356 | #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) |
357 | #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) |
358 | #define DWC3_GHWPARAMS1_ENDBC BIT(31) |
359 | |
360 | /* Global HWPARAMS3 Register */ |
361 | #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3) |
362 | #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0 |
363 | #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1 |
364 | #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2 /* DWC_usb31 only */ |
365 | #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2) |
366 | #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0 |
367 | #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1 |
368 | #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2 |
369 | #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3 |
370 | #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4) |
371 | #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0 |
372 | #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1 |
373 | |
374 | /* Global HWPARAMS4 Register */ |
375 | #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) |
376 | #define DWC3_MAX_HIBER_SCRATCHBUFS 15 |
377 | |
378 | /* Global HWPARAMS6 Register */ |
379 | #define DWC3_GHWPARAMS6_BCSUPPORT BIT(14) |
380 | #define DWC3_GHWPARAMS6_OTG3SUPPORT BIT(13) |
381 | #define DWC3_GHWPARAMS6_ADPSUPPORT BIT(12) |
382 | #define DWC3_GHWPARAMS6_HNPSUPPORT BIT(11) |
383 | #define DWC3_GHWPARAMS6_SRPSUPPORT BIT(10) |
384 | #define DWC3_GHWPARAMS6_EN_FPGA BIT(7) |
385 | |
386 | /* DWC_usb32 only */ |
387 | #define DWC3_GHWPARAMS6_MDWIDTH(n) ((n) & (0x3 << 8)) |
388 | |
389 | /* Global HWPARAMS7 Register */ |
390 | #define DWC3_GHWPARAMS7_RAM1_DEPTH(n) ((n) & 0xffff) |
391 | #define DWC3_GHWPARAMS7_RAM2_DEPTH(n) (((n) >> 16) & 0xffff) |
392 | |
393 | /* Global HWPARAMS9 Register */ |
394 | #define DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS BIT(0) |
395 | #define DWC3_GHWPARAMS9_DEV_MST BIT(1) |
396 | |
397 | /* Global Frame Length Adjustment Register */ |
398 | #define DWC3_GFLADJ_30MHZ_SDBND_SEL BIT(7) |
399 | #define DWC3_GFLADJ_30MHZ_MASK 0x3f |
400 | #define DWC3_GFLADJ_REFCLK_FLADJ_MASK GENMASK(21, 8) |
401 | #define DWC3_GFLADJ_REFCLK_LPM_SEL BIT(23) |
402 | #define DWC3_GFLADJ_240MHZDECR GENMASK(30, 24) |
403 | #define DWC3_GFLADJ_240MHZDECR_PLS1 BIT(31) |
404 | |
405 | /* Global User Control Register*/ |
406 | #define DWC3_GUCTL_REFCLKPER_MASK 0xffc00000 |
407 | #define DWC3_GUCTL_REFCLKPER_SEL 22 |
408 | |
409 | /* Global User Control Register 2 */ |
410 | #define DWC3_GUCTL2_RST_ACTBITLATER BIT(14) |
411 | |
412 | /* Global User Control Register 3 */ |
413 | #define DWC3_GUCTL3_SPLITDISABLE BIT(14) |
414 | |
415 | /* Device Configuration Register */ |
416 | #define DWC3_DCFG_NUMLANES(n) (((n) & 0x3) << 30) /* DWC_usb32 only */ |
417 | |
418 | #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) |
419 | #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) |
420 | |
421 | #define DWC3_DCFG_SPEED_MASK (7 << 0) |
422 | #define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */ |
423 | #define DWC3_DCFG_SUPERSPEED (4 << 0) |
424 | #define DWC3_DCFG_HIGHSPEED (0 << 0) |
425 | #define DWC3_DCFG_FULLSPEED BIT(0) |
426 | |
427 | #define DWC3_DCFG_NUMP_SHIFT 17 |
428 | #define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f) |
429 | #define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT) |
430 | #define DWC3_DCFG_LPM_CAP BIT(22) |
431 | #define DWC3_DCFG_IGNSTRMPP BIT(23) |
432 | |
433 | /* Device Control Register */ |
434 | #define DWC3_DCTL_RUN_STOP BIT(31) |
435 | #define DWC3_DCTL_CSFTRST BIT(30) |
436 | #define DWC3_DCTL_LSFTRST BIT(29) |
437 | |
438 | #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) |
439 | #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) |
440 | |
441 | #define DWC3_DCTL_APPL1RES BIT(23) |
442 | |
443 | /* These apply for core versions 1.87a and earlier */ |
444 | #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) |
445 | #define DWC3_DCTL_TRGTULST(n) ((n) << 17) |
446 | #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) |
447 | #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) |
448 | #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) |
449 | #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) |
450 | #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) |
451 | |
452 | /* These apply for core versions 1.94a and later */ |
453 | #define DWC3_DCTL_NYET_THRES(n) (((n) & 0xf) << 20) |
454 | |
455 | #define DWC3_DCTL_KEEP_CONNECT BIT(19) |
456 | #define DWC3_DCTL_L1_HIBER_EN BIT(18) |
457 | #define DWC3_DCTL_CRS BIT(17) |
458 | #define DWC3_DCTL_CSS BIT(16) |
459 | |
460 | #define DWC3_DCTL_INITU2ENA BIT(12) |
461 | #define DWC3_DCTL_ACCEPTU2ENA BIT(11) |
462 | #define DWC3_DCTL_INITU1ENA BIT(10) |
463 | #define DWC3_DCTL_ACCEPTU1ENA BIT(9) |
464 | #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) |
465 | |
466 | #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) |
467 | #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) |
468 | |
469 | #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) |
470 | #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) |
471 | #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) |
472 | #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) |
473 | #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) |
474 | #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) |
475 | #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) |
476 | |
477 | /* Device Event Enable Register */ |
478 | #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN BIT(12) |
479 | #define DWC3_DEVTEN_EVNTOVERFLOWEN BIT(11) |
480 | #define DWC3_DEVTEN_CMDCMPLTEN BIT(10) |
481 | #define DWC3_DEVTEN_ERRTICERREN BIT(9) |
482 | #define DWC3_DEVTEN_SOFEN BIT(7) |
483 | #define DWC3_DEVTEN_U3L2L1SUSPEN BIT(6) |
484 | #define DWC3_DEVTEN_HIBERNATIONREQEVTEN BIT(5) |
485 | #define DWC3_DEVTEN_WKUPEVTEN BIT(4) |
486 | #define DWC3_DEVTEN_ULSTCNGEN BIT(3) |
487 | #define DWC3_DEVTEN_CONNECTDONEEN BIT(2) |
488 | #define DWC3_DEVTEN_USBRSTEN BIT(1) |
489 | #define DWC3_DEVTEN_DISCONNEVTEN BIT(0) |
490 | |
491 | #define DWC3_DSTS_CONNLANES(n) (((n) >> 30) & 0x3) /* DWC_usb32 only */ |
492 | |
493 | /* Device Status Register */ |
494 | #define DWC3_DSTS_DCNRD BIT(29) |
495 | |
496 | /* This applies for core versions 1.87a and earlier */ |
497 | #define DWC3_DSTS_PWRUPREQ BIT(24) |
498 | |
499 | /* These apply for core versions 1.94a and later */ |
500 | #define BIT(25) |
501 | #define DWC3_DSTS_SSS BIT(24) |
502 | |
503 | #define DWC3_DSTS_COREIDLE BIT(23) |
504 | #define DWC3_DSTS_DEVCTRLHLT BIT(22) |
505 | |
506 | #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) |
507 | #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) |
508 | |
509 | #define DWC3_DSTS_RXFIFOEMPTY BIT(17) |
510 | |
511 | #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) |
512 | #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) |
513 | |
514 | #define DWC3_DSTS_CONNECTSPD (7 << 0) |
515 | |
516 | #define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */ |
517 | #define DWC3_DSTS_SUPERSPEED (4 << 0) |
518 | #define DWC3_DSTS_HIGHSPEED (0 << 0) |
519 | #define DWC3_DSTS_FULLSPEED BIT(0) |
520 | |
521 | /* Device Generic Command Register */ |
522 | #define DWC3_DGCMD_SET_LMP 0x01 |
523 | #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 |
524 | #define DWC3_DGCMD_XMIT_FUNCTION 0x03 |
525 | |
526 | /* These apply for core versions 1.94a and later */ |
527 | #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 |
528 | #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 |
529 | |
530 | #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 |
531 | #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a |
532 | #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c |
533 | #define DWC3_DGCMD_SET_ENDPOINT_PRIME 0x0d |
534 | #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 |
535 | #define DWC3_DGCMD_DEV_NOTIFICATION 0x07 |
536 | |
537 | #define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F) |
538 | #define DWC3_DGCMD_CMDACT BIT(10) |
539 | #define DWC3_DGCMD_CMDIOC BIT(8) |
540 | |
541 | /* Device Generic Command Parameter Register */ |
542 | #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT BIT(0) |
543 | #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) |
544 | #define DWC3_DGCMDPAR_RX_FIFO (0 << 5) |
545 | #define DWC3_DGCMDPAR_TX_FIFO BIT(5) |
546 | #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) |
547 | #define DWC3_DGCMDPAR_LOOPBACK_ENA BIT(0) |
548 | #define DWC3_DGCMDPAR_DN_FUNC_WAKE BIT(0) |
549 | #define DWC3_DGCMDPAR_INTF_SEL(n) ((n) << 4) |
550 | |
551 | /* Device Endpoint Command Register */ |
552 | #define DWC3_DEPCMD_PARAM_SHIFT 16 |
553 | #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) |
554 | #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) |
555 | #define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F) |
556 | #define DWC3_DEPCMD_HIPRI_FORCERM BIT(11) |
557 | #define DWC3_DEPCMD_CLEARPENDIN BIT(11) |
558 | #define DWC3_DEPCMD_CMDACT BIT(10) |
559 | #define DWC3_DEPCMD_CMDIOC BIT(8) |
560 | |
561 | #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) |
562 | #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) |
563 | #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) |
564 | #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) |
565 | #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) |
566 | #define DWC3_DEPCMD_SETSTALL (0x04 << 0) |
567 | /* This applies for core versions 1.90a and earlier */ |
568 | #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) |
569 | /* This applies for core versions 1.94a and later */ |
570 | #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) |
571 | #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) |
572 | #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) |
573 | |
574 | #define DWC3_DEPCMD_CMD(x) ((x) & 0xf) |
575 | |
576 | /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ |
577 | #define DWC3_DALEPENA_EP(n) BIT(n) |
578 | |
579 | /* DWC_usb32 DCFG1 config */ |
580 | #define DWC3_DCFG1_DIS_MST_ENH BIT(1) |
581 | |
582 | #define DWC3_DEPCMD_TYPE_CONTROL 0 |
583 | #define DWC3_DEPCMD_TYPE_ISOC 1 |
584 | #define DWC3_DEPCMD_TYPE_BULK 2 |
585 | #define DWC3_DEPCMD_TYPE_INTR 3 |
586 | |
587 | #define DWC3_DEV_IMOD_COUNT_SHIFT 16 |
588 | #define DWC3_DEV_IMOD_COUNT_MASK (0xffff << 16) |
589 | #define DWC3_DEV_IMOD_INTERVAL_SHIFT 0 |
590 | #define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0) |
591 | |
592 | /* OTG Configuration Register */ |
593 | #define DWC3_OCFG_DISPWRCUTTOFF BIT(5) |
594 | #define DWC3_OCFG_HIBDISMASK BIT(4) |
595 | #define DWC3_OCFG_SFTRSTMASK BIT(3) |
596 | #define DWC3_OCFG_OTGVERSION BIT(2) |
597 | #define DWC3_OCFG_HNPCAP BIT(1) |
598 | #define DWC3_OCFG_SRPCAP BIT(0) |
599 | |
600 | /* OTG CTL Register */ |
601 | #define DWC3_OCTL_OTG3GOERR BIT(7) |
602 | #define DWC3_OCTL_PERIMODE BIT(6) |
603 | #define DWC3_OCTL_PRTPWRCTL BIT(5) |
604 | #define DWC3_OCTL_HNPREQ BIT(4) |
605 | #define DWC3_OCTL_SESREQ BIT(3) |
606 | #define DWC3_OCTL_TERMSELIDPULSE BIT(2) |
607 | #define DWC3_OCTL_DEVSETHNPEN BIT(1) |
608 | #define DWC3_OCTL_HSTSETHNPEN BIT(0) |
609 | |
610 | /* OTG Event Register */ |
611 | #define DWC3_OEVT_DEVICEMODE BIT(31) |
612 | #define DWC3_OEVT_XHCIRUNSTPSET BIT(27) |
613 | #define DWC3_OEVT_DEVRUNSTPSET BIT(26) |
614 | #define DWC3_OEVT_HIBENTRY BIT(25) |
615 | #define DWC3_OEVT_CONIDSTSCHNG BIT(24) |
616 | #define DWC3_OEVT_HRRCONFNOTIF BIT(23) |
617 | #define DWC3_OEVT_HRRINITNOTIF BIT(22) |
618 | #define DWC3_OEVT_ADEVIDLE BIT(21) |
619 | #define DWC3_OEVT_ADEVBHOSTEND BIT(20) |
620 | #define DWC3_OEVT_ADEVHOST BIT(19) |
621 | #define DWC3_OEVT_ADEVHNPCHNG BIT(18) |
622 | #define DWC3_OEVT_ADEVSRPDET BIT(17) |
623 | #define DWC3_OEVT_ADEVSESSENDDET BIT(16) |
624 | #define DWC3_OEVT_BDEVBHOSTEND BIT(11) |
625 | #define DWC3_OEVT_BDEVHNPCHNG BIT(10) |
626 | #define DWC3_OEVT_BDEVSESSVLDDET BIT(9) |
627 | #define DWC3_OEVT_BDEVVBUSCHNG BIT(8) |
628 | #define DWC3_OEVT_BSESSVLD BIT(3) |
629 | #define DWC3_OEVT_HSTNEGSTS BIT(2) |
630 | #define DWC3_OEVT_SESREQSTS BIT(1) |
631 | #define DWC3_OEVT_ERROR BIT(0) |
632 | |
633 | /* OTG Event Enable Register */ |
634 | #define DWC3_OEVTEN_XHCIRUNSTPSETEN BIT(27) |
635 | #define DWC3_OEVTEN_DEVRUNSTPSETEN BIT(26) |
636 | #define DWC3_OEVTEN_HIBENTRYEN BIT(25) |
637 | #define DWC3_OEVTEN_CONIDSTSCHNGEN BIT(24) |
638 | #define DWC3_OEVTEN_HRRCONFNOTIFEN BIT(23) |
639 | #define DWC3_OEVTEN_HRRINITNOTIFEN BIT(22) |
640 | #define DWC3_OEVTEN_ADEVIDLEEN BIT(21) |
641 | #define DWC3_OEVTEN_ADEVBHOSTENDEN BIT(20) |
642 | #define DWC3_OEVTEN_ADEVHOSTEN BIT(19) |
643 | #define DWC3_OEVTEN_ADEVHNPCHNGEN BIT(18) |
644 | #define DWC3_OEVTEN_ADEVSRPDETEN BIT(17) |
645 | #define DWC3_OEVTEN_ADEVSESSENDDETEN BIT(16) |
646 | #define DWC3_OEVTEN_BDEVBHOSTENDEN BIT(11) |
647 | #define DWC3_OEVTEN_BDEVHNPCHNGEN BIT(10) |
648 | #define DWC3_OEVTEN_BDEVSESSVLDDETEN BIT(9) |
649 | #define DWC3_OEVTEN_BDEVVBUSCHNGEN BIT(8) |
650 | |
651 | /* OTG Status Register */ |
652 | #define DWC3_OSTS_DEVRUNSTP BIT(13) |
653 | #define DWC3_OSTS_XHCIRUNSTP BIT(12) |
654 | #define DWC3_OSTS_PERIPHERALSTATE BIT(4) |
655 | #define DWC3_OSTS_XHCIPRTPOWER BIT(3) |
656 | #define DWC3_OSTS_BSESVLD BIT(2) |
657 | #define DWC3_OSTS_VBUSVLD BIT(1) |
658 | #define DWC3_OSTS_CONIDSTS BIT(0) |
659 | |
660 | /* Structures */ |
661 | |
662 | struct dwc3_trb; |
663 | |
664 | /** |
665 | * struct dwc3_event_buffer - Software event buffer representation |
666 | * @buf: _THE_ buffer |
667 | * @cache: The buffer cache used in the threaded interrupt |
668 | * @length: size of this buffer |
669 | * @lpos: event offset |
670 | * @count: cache of last read event count register |
671 | * @flags: flags related to this event buffer |
672 | * @dma: dma_addr_t |
673 | * @dwc: pointer to DWC controller |
674 | */ |
675 | struct dwc3_event_buffer { |
676 | void *buf; |
677 | void *cache; |
678 | unsigned int length; |
679 | unsigned int lpos; |
680 | unsigned int count; |
681 | unsigned int flags; |
682 | |
683 | #define DWC3_EVENT_PENDING BIT(0) |
684 | |
685 | dma_addr_t dma; |
686 | |
687 | struct dwc3 *dwc; |
688 | }; |
689 | |
690 | #define DWC3_EP_FLAG_STALLED BIT(0) |
691 | #define DWC3_EP_FLAG_WEDGED BIT(1) |
692 | |
693 | #define DWC3_EP_DIRECTION_TX true |
694 | #define DWC3_EP_DIRECTION_RX false |
695 | |
696 | #define DWC3_TRB_NUM 256 |
697 | |
698 | /** |
699 | * struct dwc3_ep - device side endpoint representation |
700 | * @endpoint: usb endpoint |
701 | * @cancelled_list: list of cancelled requests for this endpoint |
702 | * @pending_list: list of pending requests for this endpoint |
703 | * @started_list: list of started requests on this endpoint |
704 | * @regs: pointer to first endpoint register |
705 | * @trb_pool: array of transaction buffers |
706 | * @trb_pool_dma: dma address of @trb_pool |
707 | * @trb_enqueue: enqueue 'pointer' into TRB array |
708 | * @trb_dequeue: dequeue 'pointer' into TRB array |
709 | * @dwc: pointer to DWC controller |
710 | * @saved_state: ep state saved during hibernation |
711 | * @flags: endpoint flags (wedged, stalled, ...) |
712 | * @number: endpoint number (1 - 15) |
713 | * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK |
714 | * @resource_index: Resource transfer index |
715 | * @frame_number: set to the frame number we want this transfer to start (ISOC) |
716 | * @interval: the interval on which the ISOC transfer is started |
717 | * @name: a human readable name e.g. ep1out-bulk |
718 | * @direction: true for TX, false for RX |
719 | * @stream_capable: true when streams are enabled |
720 | * @combo_num: the test combination BIT[15:14] of the frame number to test |
721 | * isochronous START TRANSFER command failure workaround |
722 | * @start_cmd_status: the status of testing START TRANSFER command with |
723 | * combo_num = 'b00 |
724 | */ |
725 | struct dwc3_ep { |
726 | struct usb_ep endpoint; |
727 | struct list_head cancelled_list; |
728 | struct list_head pending_list; |
729 | struct list_head started_list; |
730 | |
731 | void __iomem *regs; |
732 | |
733 | struct dwc3_trb *trb_pool; |
734 | dma_addr_t trb_pool_dma; |
735 | struct dwc3 *dwc; |
736 | |
737 | u32 saved_state; |
738 | unsigned int flags; |
739 | #define DWC3_EP_ENABLED BIT(0) |
740 | #define DWC3_EP_STALL BIT(1) |
741 | #define DWC3_EP_WEDGE BIT(2) |
742 | #define DWC3_EP_TRANSFER_STARTED BIT(3) |
743 | #define DWC3_EP_END_TRANSFER_PENDING BIT(4) |
744 | #define DWC3_EP_PENDING_REQUEST BIT(5) |
745 | #define DWC3_EP_DELAY_START BIT(6) |
746 | #define DWC3_EP_WAIT_TRANSFER_COMPLETE BIT(7) |
747 | #define DWC3_EP_IGNORE_NEXT_NOSTREAM BIT(8) |
748 | #define DWC3_EP_FORCE_RESTART_STREAM BIT(9) |
749 | #define DWC3_EP_FIRST_STREAM_PRIMED BIT(10) |
750 | #define DWC3_EP_PENDING_CLEAR_STALL BIT(11) |
751 | #define DWC3_EP_TXFIFO_RESIZED BIT(12) |
752 | #define DWC3_EP_DELAY_STOP BIT(13) |
753 | |
754 | /* This last one is specific to EP0 */ |
755 | #define DWC3_EP0_DIR_IN BIT(31) |
756 | |
757 | /* |
758 | * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will |
759 | * use a u8 type here. If anybody decides to increase number of TRBs to |
760 | * anything larger than 256 - I can't see why people would want to do |
761 | * this though - then this type needs to be changed. |
762 | * |
763 | * By using u8 types we ensure that our % operator when incrementing |
764 | * enqueue and dequeue get optimized away by the compiler. |
765 | */ |
766 | u8 trb_enqueue; |
767 | u8 trb_dequeue; |
768 | |
769 | u8 number; |
770 | u8 type; |
771 | u8 resource_index; |
772 | u32 frame_number; |
773 | u32 interval; |
774 | |
775 | char name[20]; |
776 | |
777 | unsigned direction:1; |
778 | unsigned stream_capable:1; |
779 | |
780 | /* For isochronous START TRANSFER workaround only */ |
781 | u8 combo_num; |
782 | int start_cmd_status; |
783 | }; |
784 | |
785 | enum dwc3_phy { |
786 | DWC3_PHY_UNKNOWN = 0, |
787 | DWC3_PHY_USB3, |
788 | DWC3_PHY_USB2, |
789 | }; |
790 | |
791 | enum dwc3_ep0_next { |
792 | DWC3_EP0_UNKNOWN = 0, |
793 | DWC3_EP0_COMPLETE, |
794 | DWC3_EP0_NRDY_DATA, |
795 | DWC3_EP0_NRDY_STATUS, |
796 | }; |
797 | |
798 | enum dwc3_ep0_state { |
799 | EP0_UNCONNECTED = 0, |
800 | EP0_SETUP_PHASE, |
801 | EP0_DATA_PHASE, |
802 | EP0_STATUS_PHASE, |
803 | }; |
804 | |
805 | enum dwc3_link_state { |
806 | /* In SuperSpeed */ |
807 | DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ |
808 | DWC3_LINK_STATE_U1 = 0x01, |
809 | DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ |
810 | DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ |
811 | DWC3_LINK_STATE_SS_DIS = 0x04, |
812 | DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ |
813 | DWC3_LINK_STATE_SS_INACT = 0x06, |
814 | DWC3_LINK_STATE_POLL = 0x07, |
815 | DWC3_LINK_STATE_RECOV = 0x08, |
816 | DWC3_LINK_STATE_HRESET = 0x09, |
817 | DWC3_LINK_STATE_CMPLY = 0x0a, |
818 | DWC3_LINK_STATE_LPBK = 0x0b, |
819 | DWC3_LINK_STATE_RESET = 0x0e, |
820 | DWC3_LINK_STATE_RESUME = 0x0f, |
821 | DWC3_LINK_STATE_MASK = 0x0f, |
822 | }; |
823 | |
824 | /* TRB Length, PCM and Status */ |
825 | #define DWC3_TRB_SIZE_MASK (0x00ffffff) |
826 | #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) |
827 | #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) |
828 | #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) |
829 | |
830 | #define DWC3_TRBSTS_OK 0 |
831 | #define DWC3_TRBSTS_MISSED_ISOC 1 |
832 | #define DWC3_TRBSTS_SETUP_PENDING 2 |
833 | #define DWC3_TRB_STS_XFER_IN_PROG 4 |
834 | |
835 | /* TRB Control */ |
836 | #define DWC3_TRB_CTRL_HWO BIT(0) |
837 | #define DWC3_TRB_CTRL_LST BIT(1) |
838 | #define DWC3_TRB_CTRL_CHN BIT(2) |
839 | #define DWC3_TRB_CTRL_CSP BIT(3) |
840 | #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) |
841 | #define DWC3_TRB_CTRL_ISP_IMI BIT(10) |
842 | #define DWC3_TRB_CTRL_IOC BIT(11) |
843 | #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) |
844 | #define DWC3_TRB_CTRL_GET_SID_SOFN(n) (((n) & (0xffff << 14)) >> 14) |
845 | |
846 | #define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4)) |
847 | #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) |
848 | #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) |
849 | #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) |
850 | #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) |
851 | #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) |
852 | #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) |
853 | #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) |
854 | #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) |
855 | |
856 | /** |
857 | * struct dwc3_trb - transfer request block (hw format) |
858 | * @bpl: DW0-3 |
859 | * @bph: DW4-7 |
860 | * @size: DW8-B |
861 | * @ctrl: DWC-F |
862 | */ |
863 | struct dwc3_trb { |
864 | u32 bpl; |
865 | u32 bph; |
866 | u32 size; |
867 | u32 ctrl; |
868 | } __packed; |
869 | |
870 | /** |
871 | * struct dwc3_hwparams - copy of HWPARAMS registers |
872 | * @hwparams0: GHWPARAMS0 |
873 | * @hwparams1: GHWPARAMS1 |
874 | * @hwparams2: GHWPARAMS2 |
875 | * @hwparams3: GHWPARAMS3 |
876 | * @hwparams4: GHWPARAMS4 |
877 | * @hwparams5: GHWPARAMS5 |
878 | * @hwparams6: GHWPARAMS6 |
879 | * @hwparams7: GHWPARAMS7 |
880 | * @hwparams8: GHWPARAMS8 |
881 | * @hwparams9: GHWPARAMS9 |
882 | */ |
883 | struct dwc3_hwparams { |
884 | u32 hwparams0; |
885 | u32 hwparams1; |
886 | u32 hwparams2; |
887 | u32 hwparams3; |
888 | u32 hwparams4; |
889 | u32 hwparams5; |
890 | u32 hwparams6; |
891 | u32 hwparams7; |
892 | u32 hwparams8; |
893 | u32 hwparams9; |
894 | }; |
895 | |
896 | /* HWPARAMS0 */ |
897 | #define DWC3_MODE(n) ((n) & 0x7) |
898 | |
899 | /* HWPARAMS1 */ |
900 | #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) |
901 | |
902 | /* HWPARAMS3 */ |
903 | #define DWC3_NUM_IN_EPS_MASK (0x1f << 18) |
904 | #define DWC3_NUM_EPS_MASK (0x3f << 12) |
905 | #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ |
906 | (DWC3_NUM_EPS_MASK)) >> 12) |
907 | #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ |
908 | (DWC3_NUM_IN_EPS_MASK)) >> 18) |
909 | |
910 | /* HWPARAMS7 */ |
911 | #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) |
912 | |
913 | /* HWPARAMS9 */ |
914 | #define DWC3_MST_CAPABLE(p) (!!((p)->hwparams9 & \ |
915 | DWC3_GHWPARAMS9_DEV_MST)) |
916 | |
917 | /** |
918 | * struct dwc3_request - representation of a transfer request |
919 | * @request: struct usb_request to be transferred |
920 | * @list: a list_head used for request queueing |
921 | * @dep: struct dwc3_ep owning this request |
922 | * @sg: pointer to first incomplete sg |
923 | * @start_sg: pointer to the sg which should be queued next |
924 | * @num_pending_sgs: counter to pending sgs |
925 | * @num_queued_sgs: counter to the number of sgs which already got queued |
926 | * @remaining: amount of data remaining |
927 | * @status: internal dwc3 request status tracking |
928 | * @epnum: endpoint number to which this request refers |
929 | * @trb: pointer to struct dwc3_trb |
930 | * @trb_dma: DMA address of @trb |
931 | * @num_trbs: number of TRBs used by this request |
932 | * @needs_extra_trb: true when request needs one extra TRB (either due to ZLP |
933 | * or unaligned OUT) |
934 | * @direction: IN or OUT direction flag |
935 | * @mapped: true when request has been dma-mapped |
936 | */ |
937 | struct dwc3_request { |
938 | struct usb_request request; |
939 | struct list_head list; |
940 | struct dwc3_ep *dep; |
941 | struct scatterlist *sg; |
942 | struct scatterlist *start_sg; |
943 | |
944 | unsigned int num_pending_sgs; |
945 | unsigned int num_queued_sgs; |
946 | unsigned int remaining; |
947 | |
948 | unsigned int status; |
949 | #define DWC3_REQUEST_STATUS_QUEUED 0 |
950 | #define DWC3_REQUEST_STATUS_STARTED 1 |
951 | #define DWC3_REQUEST_STATUS_DISCONNECTED 2 |
952 | #define DWC3_REQUEST_STATUS_DEQUEUED 3 |
953 | #define DWC3_REQUEST_STATUS_STALLED 4 |
954 | #define DWC3_REQUEST_STATUS_COMPLETED 5 |
955 | #define DWC3_REQUEST_STATUS_UNKNOWN -1 |
956 | |
957 | u8 epnum; |
958 | struct dwc3_trb *trb; |
959 | dma_addr_t trb_dma; |
960 | |
961 | unsigned int num_trbs; |
962 | |
963 | unsigned int :1; |
964 | unsigned int direction:1; |
965 | unsigned int mapped:1; |
966 | }; |
967 | |
968 | /* |
969 | * struct dwc3_scratchpad_array - hibernation scratchpad array |
970 | * (format defined by hw) |
971 | */ |
972 | struct dwc3_scratchpad_array { |
973 | __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; |
974 | }; |
975 | |
976 | /** |
977 | * struct dwc3 - representation of our controller |
978 | * @drd_work: workqueue used for role swapping |
979 | * @ep0_trb: trb which is used for the ctrl_req |
980 | * @bounce: address of bounce buffer |
981 | * @setup_buf: used while precessing STD USB requests |
982 | * @ep0_trb_addr: dma address of @ep0_trb |
983 | * @bounce_addr: dma address of @bounce |
984 | * @ep0_usb_req: dummy req used while handling STD USB requests |
985 | * @ep0_in_setup: one control transfer is completed and enter setup phase |
986 | * @lock: for synchronizing |
987 | * @mutex: for mode switching |
988 | * @dev: pointer to our struct device |
989 | * @sysdev: pointer to the DMA-capable device |
990 | * @xhci: pointer to our xHCI child |
991 | * @xhci_resources: struct resources for our @xhci child |
992 | * @ev_buf: struct dwc3_event_buffer pointer |
993 | * @eps: endpoint array |
994 | * @gadget: device side representation of the peripheral controller |
995 | * @gadget_driver: pointer to the gadget driver |
996 | * @bus_clk: clock for accessing the registers |
997 | * @ref_clk: reference clock |
998 | * @susp_clk: clock used when the SS phy is in low power (S3) state |
999 | * @utmi_clk: clock used for USB2 PHY communication |
1000 | * @pipe_clk: clock used for USB3 PHY communication |
1001 | * @reset: reset control |
1002 | * @regs: base address for our registers |
1003 | * @regs_size: address space size |
1004 | * @fladj: frame length adjustment |
1005 | * @ref_clk_per: reference clock period configuration |
1006 | * @irq_gadget: peripheral controller's IRQ number |
1007 | * @otg_irq: IRQ number for OTG IRQs |
1008 | * @current_otg_role: current role of operation while using the OTG block |
1009 | * @desired_otg_role: desired role of operation while using the OTG block |
1010 | * @otg_restart_host: flag that OTG controller needs to restart host |
1011 | * @u1u2: only used on revisions <1.83a for workaround |
1012 | * @maximum_speed: maximum speed requested (mainly for testing purposes) |
1013 | * @max_ssp_rate: SuperSpeed Plus maximum signaling rate and lane count |
1014 | * @gadget_max_speed: maximum gadget speed requested |
1015 | * @gadget_ssp_rate: Gadget driver's maximum supported SuperSpeed Plus signaling |
1016 | * rate and lane count. |
1017 | * @ip: controller's ID |
1018 | * @revision: controller's version of an IP |
1019 | * @version_type: VERSIONTYPE register contents, a sub release of a revision |
1020 | * @dr_mode: requested mode of operation |
1021 | * @current_dr_role: current role of operation when in dual-role mode |
1022 | * @desired_dr_role: desired role of operation when in dual-role mode |
1023 | * @edev: extcon handle |
1024 | * @edev_nb: extcon notifier |
1025 | * @hsphy_mode: UTMI phy mode, one of following: |
1026 | * - USBPHY_INTERFACE_MODE_UTMI |
1027 | * - USBPHY_INTERFACE_MODE_UTMIW |
1028 | * @role_sw: usb_role_switch handle |
1029 | * @role_switch_default_mode: default operation mode of controller while |
1030 | * usb role is USB_ROLE_NONE. |
1031 | * @usb_psy: pointer to power supply interface. |
1032 | * @usb2_phy: pointer to USB2 PHY |
1033 | * @usb3_phy: pointer to USB3 PHY |
1034 | * @usb2_generic_phy: pointer to USB2 PHY |
1035 | * @usb3_generic_phy: pointer to USB3 PHY |
1036 | * @phys_ready: flag to indicate that PHYs are ready |
1037 | * @ulpi: pointer to ulpi interface |
1038 | * @ulpi_ready: flag to indicate that ULPI is initialized |
1039 | * @u2sel: parameter from Set SEL request. |
1040 | * @u2pel: parameter from Set SEL request. |
1041 | * @u1sel: parameter from Set SEL request. |
1042 | * @u1pel: parameter from Set SEL request. |
1043 | * @num_eps: number of endpoints |
1044 | * @ep0_next_event: hold the next expected event |
1045 | * @ep0state: state of endpoint zero |
1046 | * @link_state: link state |
1047 | * @speed: device speed (super, high, full, low) |
1048 | * @hwparams: copy of hwparams registers |
1049 | * @regset: debugfs pointer to regdump file |
1050 | * @dbg_lsp_select: current debug lsp mux register selection |
1051 | * @test_mode: true when we're entering a USB test mode |
1052 | * @test_mode_nr: test feature selector |
1053 | * @lpm_nyet_threshold: LPM NYET response threshold |
1054 | * @hird_threshold: HIRD threshold |
1055 | * @rx_thr_num_pkt: USB receive packet count |
1056 | * @rx_max_burst: max USB receive burst size |
1057 | * @tx_thr_num_pkt: USB transmit packet count |
1058 | * @tx_max_burst: max USB transmit burst size |
1059 | * @rx_thr_num_pkt_prd: periodic ESS receive packet count |
1060 | * @rx_max_burst_prd: max periodic ESS receive burst size |
1061 | * @tx_thr_num_pkt_prd: periodic ESS transmit packet count |
1062 | * @tx_max_burst_prd: max periodic ESS transmit burst size |
1063 | * @tx_fifo_resize_max_num: max number of fifos allocated during txfifo resize |
1064 | * @clear_stall_protocol: endpoint number that requires a delayed status phase |
1065 | * @hsphy_interface: "utmi" or "ulpi" |
1066 | * @connected: true when we're connected to a host, false otherwise |
1067 | * @softconnect: true when gadget connect is called, false when disconnect runs |
1068 | * @delayed_status: true when gadget driver asks for delayed status |
1069 | * @ep0_bounced: true when we used bounce buffer |
1070 | * @ep0_expect_in: true when we expect a DATA IN transfer |
1071 | * @sysdev_is_parent: true when dwc3 device has a parent driver |
1072 | * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that |
1073 | * there's now way for software to detect this in runtime. |
1074 | * @is_utmi_l1_suspend: the core asserts output signal |
1075 | * 0 - utmi_sleep_n |
1076 | * 1 - utmi_l1_suspend_n |
1077 | * @is_fpga: true when we are using the FPGA board |
1078 | * @pending_events: true when we have pending IRQs to be handled |
1079 | * @do_fifo_resize: true when txfifo resizing is enabled for dwc3 endpoints |
1080 | * @pullups_connected: true when Run/Stop bit is set |
1081 | * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround |
1082 | * @three_stage_setup: set if we perform a three phase setup |
1083 | * @dis_start_transfer_quirk: set if start_transfer failure SW workaround is |
1084 | * not needed for DWC_usb31 version 1.70a-ea06 and below |
1085 | * @usb3_lpm_capable: set if hadrware supports Link Power Management |
1086 | * @usb2_lpm_disable: set to disable usb2 lpm for host |
1087 | * @usb2_gadget_lpm_disable: set to disable usb2 lpm for gadget |
1088 | * @disable_scramble_quirk: set if we enable the disable scramble quirk |
1089 | * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk |
1090 | * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk |
1091 | * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk |
1092 | * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk |
1093 | * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk |
1094 | * @lfps_filter_quirk: set if we enable LFPS filter quirk |
1095 | * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk |
1096 | * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy |
1097 | * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy |
1098 | * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG, |
1099 | * disabling the suspend signal to the PHY. |
1100 | * @dis_u1_entry_quirk: set if link entering into U1 state needs to be disabled. |
1101 | * @dis_u2_entry_quirk: set if link entering into U2 state needs to be disabled. |
1102 | * @dis_rxdet_inp3_quirk: set if we disable Rx.Detect in P3 |
1103 | * @async_callbacks: if set, indicate that async callbacks will be used. |
1104 | * |
1105 | * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists |
1106 | * in GUSB2PHYCFG, specify that USB2 PHY doesn't |
1107 | * provide a free-running PHY clock. |
1108 | * @dis_del_phy_power_chg_quirk: set if we disable delay phy power |
1109 | * change quirk. |
1110 | * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate |
1111 | * check during HS transmit. |
1112 | * @resume_hs_terminations: Set if we enable quirk for fixing improper crc |
1113 | * generation after resume from suspend. |
1114 | * @ulpi_ext_vbus_drv: Set to confiure the upli chip to drives CPEN pin |
1115 | * VBUS with an external supply. |
1116 | * @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed |
1117 | * instances in park mode. |
1118 | * @parkmode_disable_hs_quirk: set if we need to disable all HishSpeed |
1119 | * instances in park mode. |
1120 | * @gfladj_refclk_lpm_sel: set if we need to enable SOF/ITP counter |
1121 | * running based on ref_clk |
1122 | * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk |
1123 | * @tx_de_emphasis: Tx de-emphasis value |
1124 | * 0 - -6dB de-emphasis |
1125 | * 1 - -3.5dB de-emphasis |
1126 | * 2 - No de-emphasis |
1127 | * 3 - Reserved |
1128 | * @dis_metastability_quirk: set to disable metastability quirk. |
1129 | * @dis_split_quirk: set to disable split boundary. |
1130 | * @wakeup_configured: set if the device is configured for remote wakeup. |
1131 | * @suspended: set to track suspend event due to U3/L2. |
1132 | * @imod_interval: set the interrupt moderation interval in 250ns |
1133 | * increments or 0 to disable. |
1134 | * @max_cfg_eps: current max number of IN eps used across all USB configs. |
1135 | * @last_fifo_depth: last fifo depth used to determine next fifo ram start |
1136 | * address. |
1137 | * @num_ep_resized: carries the current number endpoints which have had its tx |
1138 | * fifo resized. |
1139 | * @debug_root: root debugfs directory for this device to put its files in. |
1140 | */ |
1141 | struct dwc3 { |
1142 | struct work_struct drd_work; |
1143 | struct dwc3_trb *ep0_trb; |
1144 | void *bounce; |
1145 | u8 *setup_buf; |
1146 | dma_addr_t ep0_trb_addr; |
1147 | dma_addr_t bounce_addr; |
1148 | struct dwc3_request ep0_usb_req; |
1149 | struct completion ep0_in_setup; |
1150 | |
1151 | /* device lock */ |
1152 | spinlock_t lock; |
1153 | |
1154 | /* mode switching lock */ |
1155 | struct mutex mutex; |
1156 | |
1157 | struct device *dev; |
1158 | struct device *sysdev; |
1159 | |
1160 | struct platform_device *xhci; |
1161 | struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; |
1162 | |
1163 | struct dwc3_event_buffer *ev_buf; |
1164 | struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; |
1165 | |
1166 | struct usb_gadget *gadget; |
1167 | struct usb_gadget_driver *gadget_driver; |
1168 | |
1169 | struct clk *bus_clk; |
1170 | struct clk *ref_clk; |
1171 | struct clk *susp_clk; |
1172 | struct clk *utmi_clk; |
1173 | struct clk *pipe_clk; |
1174 | |
1175 | struct reset_control *reset; |
1176 | |
1177 | struct usb_phy *usb2_phy; |
1178 | struct usb_phy *usb3_phy; |
1179 | |
1180 | struct phy *usb2_generic_phy; |
1181 | struct phy *usb3_generic_phy; |
1182 | |
1183 | bool phys_ready; |
1184 | |
1185 | struct ulpi *ulpi; |
1186 | bool ulpi_ready; |
1187 | |
1188 | void __iomem *regs; |
1189 | size_t regs_size; |
1190 | |
1191 | enum usb_dr_mode dr_mode; |
1192 | u32 current_dr_role; |
1193 | u32 desired_dr_role; |
1194 | struct extcon_dev *edev; |
1195 | struct notifier_block edev_nb; |
1196 | enum usb_phy_interface hsphy_mode; |
1197 | struct usb_role_switch *role_sw; |
1198 | enum usb_dr_mode role_switch_default_mode; |
1199 | |
1200 | struct power_supply *usb_psy; |
1201 | |
1202 | u32 fladj; |
1203 | u32 ref_clk_per; |
1204 | u32 irq_gadget; |
1205 | u32 otg_irq; |
1206 | u32 current_otg_role; |
1207 | u32 desired_otg_role; |
1208 | bool otg_restart_host; |
1209 | u32 u1u2; |
1210 | u32 maximum_speed; |
1211 | u32 gadget_max_speed; |
1212 | enum usb_ssp_rate max_ssp_rate; |
1213 | enum usb_ssp_rate gadget_ssp_rate; |
1214 | |
1215 | u32 ip; |
1216 | |
1217 | #define DWC3_IP 0x5533 |
1218 | #define DWC31_IP 0x3331 |
1219 | #define DWC32_IP 0x3332 |
1220 | |
1221 | u32 revision; |
1222 | |
1223 | #define DWC3_REVISION_ANY 0x0 |
1224 | #define DWC3_REVISION_173A 0x5533173a |
1225 | #define DWC3_REVISION_175A 0x5533175a |
1226 | #define DWC3_REVISION_180A 0x5533180a |
1227 | #define DWC3_REVISION_183A 0x5533183a |
1228 | #define DWC3_REVISION_185A 0x5533185a |
1229 | #define DWC3_REVISION_187A 0x5533187a |
1230 | #define DWC3_REVISION_188A 0x5533188a |
1231 | #define DWC3_REVISION_190A 0x5533190a |
1232 | #define DWC3_REVISION_194A 0x5533194a |
1233 | #define DWC3_REVISION_200A 0x5533200a |
1234 | #define DWC3_REVISION_202A 0x5533202a |
1235 | #define DWC3_REVISION_210A 0x5533210a |
1236 | #define DWC3_REVISION_220A 0x5533220a |
1237 | #define DWC3_REVISION_230A 0x5533230a |
1238 | #define DWC3_REVISION_240A 0x5533240a |
1239 | #define DWC3_REVISION_250A 0x5533250a |
1240 | #define DWC3_REVISION_260A 0x5533260a |
1241 | #define DWC3_REVISION_270A 0x5533270a |
1242 | #define DWC3_REVISION_280A 0x5533280a |
1243 | #define DWC3_REVISION_290A 0x5533290a |
1244 | #define DWC3_REVISION_300A 0x5533300a |
1245 | #define DWC3_REVISION_310A 0x5533310a |
1246 | #define DWC3_REVISION_330A 0x5533330a |
1247 | |
1248 | #define DWC31_REVISION_ANY 0x0 |
1249 | #define DWC31_REVISION_110A 0x3131302a |
1250 | #define DWC31_REVISION_120A 0x3132302a |
1251 | #define DWC31_REVISION_160A 0x3136302a |
1252 | #define DWC31_REVISION_170A 0x3137302a |
1253 | #define DWC31_REVISION_180A 0x3138302a |
1254 | #define DWC31_REVISION_190A 0x3139302a |
1255 | |
1256 | #define DWC32_REVISION_ANY 0x0 |
1257 | #define DWC32_REVISION_100A 0x3130302a |
1258 | |
1259 | u32 version_type; |
1260 | |
1261 | #define DWC31_VERSIONTYPE_ANY 0x0 |
1262 | #define DWC31_VERSIONTYPE_EA01 0x65613031 |
1263 | #define DWC31_VERSIONTYPE_EA02 0x65613032 |
1264 | #define DWC31_VERSIONTYPE_EA03 0x65613033 |
1265 | #define DWC31_VERSIONTYPE_EA04 0x65613034 |
1266 | #define DWC31_VERSIONTYPE_EA05 0x65613035 |
1267 | #define DWC31_VERSIONTYPE_EA06 0x65613036 |
1268 | |
1269 | enum dwc3_ep0_next ep0_next_event; |
1270 | enum dwc3_ep0_state ep0state; |
1271 | enum dwc3_link_state link_state; |
1272 | |
1273 | u16 u2sel; |
1274 | u16 u2pel; |
1275 | u8 u1sel; |
1276 | u8 u1pel; |
1277 | |
1278 | u8 speed; |
1279 | |
1280 | u8 num_eps; |
1281 | |
1282 | struct dwc3_hwparams hwparams; |
1283 | struct debugfs_regset32 *regset; |
1284 | |
1285 | u32 dbg_lsp_select; |
1286 | |
1287 | u8 test_mode; |
1288 | u8 test_mode_nr; |
1289 | u8 lpm_nyet_threshold; |
1290 | u8 hird_threshold; |
1291 | u8 rx_thr_num_pkt; |
1292 | u8 rx_max_burst; |
1293 | u8 tx_thr_num_pkt; |
1294 | u8 tx_max_burst; |
1295 | u8 rx_thr_num_pkt_prd; |
1296 | u8 rx_max_burst_prd; |
1297 | u8 tx_thr_num_pkt_prd; |
1298 | u8 tx_max_burst_prd; |
1299 | u8 tx_fifo_resize_max_num; |
1300 | u8 clear_stall_protocol; |
1301 | |
1302 | const char *hsphy_interface; |
1303 | |
1304 | unsigned connected:1; |
1305 | unsigned softconnect:1; |
1306 | unsigned delayed_status:1; |
1307 | unsigned ep0_bounced:1; |
1308 | unsigned ep0_expect_in:1; |
1309 | unsigned sysdev_is_parent:1; |
1310 | unsigned has_lpm_erratum:1; |
1311 | unsigned is_utmi_l1_suspend:1; |
1312 | unsigned is_fpga:1; |
1313 | unsigned pending_events:1; |
1314 | unsigned do_fifo_resize:1; |
1315 | unsigned pullups_connected:1; |
1316 | unsigned setup_packet_pending:1; |
1317 | unsigned three_stage_setup:1; |
1318 | unsigned dis_start_transfer_quirk:1; |
1319 | unsigned usb3_lpm_capable:1; |
1320 | unsigned usb2_lpm_disable:1; |
1321 | unsigned usb2_gadget_lpm_disable:1; |
1322 | |
1323 | unsigned disable_scramble_quirk:1; |
1324 | unsigned u2exit_lfps_quirk:1; |
1325 | unsigned u2ss_inp3_quirk:1; |
1326 | unsigned req_p1p2p3_quirk:1; |
1327 | unsigned del_p1p2p3_quirk:1; |
1328 | unsigned del_phy_power_chg_quirk:1; |
1329 | unsigned lfps_filter_quirk:1; |
1330 | unsigned rx_detect_poll_quirk:1; |
1331 | unsigned dis_u3_susphy_quirk:1; |
1332 | unsigned dis_u2_susphy_quirk:1; |
1333 | unsigned dis_enblslpm_quirk:1; |
1334 | unsigned dis_u1_entry_quirk:1; |
1335 | unsigned dis_u2_entry_quirk:1; |
1336 | unsigned dis_rxdet_inp3_quirk:1; |
1337 | unsigned dis_u2_freeclk_exists_quirk:1; |
1338 | unsigned dis_del_phy_power_chg_quirk:1; |
1339 | unsigned dis_tx_ipgap_linecheck_quirk:1; |
1340 | unsigned resume_hs_terminations:1; |
1341 | unsigned ulpi_ext_vbus_drv:1; |
1342 | unsigned parkmode_disable_ss_quirk:1; |
1343 | unsigned parkmode_disable_hs_quirk:1; |
1344 | unsigned gfladj_refclk_lpm_sel:1; |
1345 | |
1346 | unsigned tx_de_emphasis_quirk:1; |
1347 | unsigned tx_de_emphasis:2; |
1348 | |
1349 | unsigned dis_metastability_quirk:1; |
1350 | |
1351 | unsigned dis_split_quirk:1; |
1352 | unsigned async_callbacks:1; |
1353 | unsigned wakeup_configured:1; |
1354 | unsigned suspended:1; |
1355 | |
1356 | u16 imod_interval; |
1357 | |
1358 | int max_cfg_eps; |
1359 | int last_fifo_depth; |
1360 | int num_ep_resized; |
1361 | struct dentry *debug_root; |
1362 | }; |
1363 | |
1364 | #define INCRX_BURST_MODE 0 |
1365 | #define INCRX_UNDEF_LENGTH_BURST_MODE 1 |
1366 | |
1367 | #define work_to_dwc(w) (container_of((w), struct dwc3, drd_work)) |
1368 | |
1369 | /* -------------------------------------------------------------------------- */ |
1370 | |
1371 | struct dwc3_event_type { |
1372 | u32 is_devspec:1; |
1373 | u32 type:7; |
1374 | u32 reserved8_31:24; |
1375 | } __packed; |
1376 | |
1377 | #define DWC3_DEPEVT_XFERCOMPLETE 0x01 |
1378 | #define DWC3_DEPEVT_XFERINPROGRESS 0x02 |
1379 | #define DWC3_DEPEVT_XFERNOTREADY 0x03 |
1380 | #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 |
1381 | #define DWC3_DEPEVT_STREAMEVT 0x06 |
1382 | #define DWC3_DEPEVT_EPCMDCMPLT 0x07 |
1383 | |
1384 | /** |
1385 | * struct dwc3_event_depevt - Device Endpoint Events |
1386 | * @one_bit: indicates this is an endpoint event (not used) |
1387 | * @endpoint_number: number of the endpoint |
1388 | * @endpoint_event: The event we have: |
1389 | * 0x00 - Reserved |
1390 | * 0x01 - XferComplete |
1391 | * 0x02 - XferInProgress |
1392 | * 0x03 - XferNotReady |
1393 | * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) |
1394 | * 0x05 - Reserved |
1395 | * 0x06 - StreamEvt |
1396 | * 0x07 - EPCmdCmplt |
1397 | * @reserved11_10: Reserved, don't use. |
1398 | * @status: Indicates the status of the event. Refer to databook for |
1399 | * more information. |
1400 | * @parameters: Parameters of the current event. Refer to databook for |
1401 | * more information. |
1402 | */ |
1403 | struct dwc3_event_depevt { |
1404 | u32 one_bit:1; |
1405 | u32 endpoint_number:5; |
1406 | u32 endpoint_event:4; |
1407 | u32 reserved11_10:2; |
1408 | u32 status:4; |
1409 | |
1410 | /* Within XferNotReady */ |
1411 | #define DEPEVT_STATUS_TRANSFER_ACTIVE BIT(3) |
1412 | |
1413 | /* Within XferComplete or XferInProgress */ |
1414 | #define DEPEVT_STATUS_BUSERR BIT(0) |
1415 | #define DEPEVT_STATUS_SHORT BIT(1) |
1416 | #define DEPEVT_STATUS_IOC BIT(2) |
1417 | #define DEPEVT_STATUS_LST BIT(3) /* XferComplete */ |
1418 | #define DEPEVT_STATUS_MISSED_ISOC BIT(3) /* XferInProgress */ |
1419 | |
1420 | /* Stream event only */ |
1421 | #define DEPEVT_STREAMEVT_FOUND 1 |
1422 | #define DEPEVT_STREAMEVT_NOTFOUND 2 |
1423 | |
1424 | /* Stream event parameter */ |
1425 | #define DEPEVT_STREAM_PRIME 0xfffe |
1426 | #define DEPEVT_STREAM_NOSTREAM 0x0 |
1427 | |
1428 | /* Control-only Status */ |
1429 | #define DEPEVT_STATUS_CONTROL_DATA 1 |
1430 | #define DEPEVT_STATUS_CONTROL_STATUS 2 |
1431 | #define DEPEVT_STATUS_CONTROL_PHASE(n) ((n) & 3) |
1432 | |
1433 | /* In response to Start Transfer */ |
1434 | #define DEPEVT_TRANSFER_NO_RESOURCE 1 |
1435 | #define DEPEVT_TRANSFER_BUS_EXPIRY 2 |
1436 | |
1437 | u32 parameters:16; |
1438 | |
1439 | /* For Command Complete Events */ |
1440 | #define DEPEVT_PARAMETER_CMD(n) (((n) & (0xf << 8)) >> 8) |
1441 | } __packed; |
1442 | |
1443 | /** |
1444 | * struct dwc3_event_devt - Device Events |
1445 | * @one_bit: indicates this is a non-endpoint event (not used) |
1446 | * @device_event: indicates it's a device event. Should read as 0x00 |
1447 | * @type: indicates the type of device event. |
1448 | * 0 - DisconnEvt |
1449 | * 1 - USBRst |
1450 | * 2 - ConnectDone |
1451 | * 3 - ULStChng |
1452 | * 4 - WkUpEvt |
1453 | * 5 - Reserved |
1454 | * 6 - Suspend (EOPF on revisions 2.10a and prior) |
1455 | * 7 - SOF |
1456 | * 8 - Reserved |
1457 | * 9 - ErrticErr |
1458 | * 10 - CmdCmplt |
1459 | * 11 - EvntOverflow |
1460 | * 12 - VndrDevTstRcved |
1461 | * @reserved15_12: Reserved, not used |
1462 | * @event_info: Information about this event |
1463 | * @reserved31_25: Reserved, not used |
1464 | */ |
1465 | struct dwc3_event_devt { |
1466 | u32 one_bit:1; |
1467 | u32 device_event:7; |
1468 | u32 type:4; |
1469 | u32 reserved15_12:4; |
1470 | u32 event_info:9; |
1471 | u32 reserved31_25:7; |
1472 | } __packed; |
1473 | |
1474 | /** |
1475 | * struct dwc3_event_gevt - Other Core Events |
1476 | * @one_bit: indicates this is a non-endpoint event (not used) |
1477 | * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. |
1478 | * @phy_port_number: self-explanatory |
1479 | * @reserved31_12: Reserved, not used. |
1480 | */ |
1481 | struct dwc3_event_gevt { |
1482 | u32 one_bit:1; |
1483 | u32 device_event:7; |
1484 | u32 phy_port_number:4; |
1485 | u32 reserved31_12:20; |
1486 | } __packed; |
1487 | |
1488 | /** |
1489 | * union dwc3_event - representation of Event Buffer contents |
1490 | * @raw: raw 32-bit event |
1491 | * @type: the type of the event |
1492 | * @depevt: Device Endpoint Event |
1493 | * @devt: Device Event |
1494 | * @gevt: Global Event |
1495 | */ |
1496 | union dwc3_event { |
1497 | u32 raw; |
1498 | struct dwc3_event_type type; |
1499 | struct dwc3_event_depevt depevt; |
1500 | struct dwc3_event_devt devt; |
1501 | struct dwc3_event_gevt gevt; |
1502 | }; |
1503 | |
1504 | /** |
1505 | * struct dwc3_gadget_ep_cmd_params - representation of endpoint command |
1506 | * parameters |
1507 | * @param2: third parameter |
1508 | * @param1: second parameter |
1509 | * @param0: first parameter |
1510 | */ |
1511 | struct dwc3_gadget_ep_cmd_params { |
1512 | u32 param2; |
1513 | u32 param1; |
1514 | u32 param0; |
1515 | }; |
1516 | |
1517 | /* |
1518 | * DWC3 Features to be used as Driver Data |
1519 | */ |
1520 | |
1521 | #define DWC3_HAS_PERIPHERAL BIT(0) |
1522 | #define DWC3_HAS_XHCI BIT(1) |
1523 | #define DWC3_HAS_OTG BIT(3) |
1524 | |
1525 | /* prototypes */ |
1526 | void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode); |
1527 | void dwc3_set_mode(struct dwc3 *dwc, u32 mode); |
1528 | u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type); |
1529 | |
1530 | #define DWC3_IP_IS(_ip) \ |
1531 | (dwc->ip == _ip##_IP) |
1532 | |
1533 | #define DWC3_VER_IS(_ip, _ver) \ |
1534 | (DWC3_IP_IS(_ip) && dwc->revision == _ip##_REVISION_##_ver) |
1535 | |
1536 | #define DWC3_VER_IS_PRIOR(_ip, _ver) \ |
1537 | (DWC3_IP_IS(_ip) && dwc->revision < _ip##_REVISION_##_ver) |
1538 | |
1539 | #define DWC3_VER_IS_WITHIN(_ip, _from, _to) \ |
1540 | (DWC3_IP_IS(_ip) && \ |
1541 | dwc->revision >= _ip##_REVISION_##_from && \ |
1542 | (!(_ip##_REVISION_##_to) || \ |
1543 | dwc->revision <= _ip##_REVISION_##_to)) |
1544 | |
1545 | #define DWC3_VER_TYPE_IS_WITHIN(_ip, _ver, _from, _to) \ |
1546 | (DWC3_VER_IS(_ip, _ver) && \ |
1547 | dwc->version_type >= _ip##_VERSIONTYPE_##_from && \ |
1548 | (!(_ip##_VERSIONTYPE_##_to) || \ |
1549 | dwc->version_type <= _ip##_VERSIONTYPE_##_to)) |
1550 | |
1551 | /** |
1552 | * dwc3_mdwidth - get MDWIDTH value in bits |
1553 | * @dwc: pointer to our context structure |
1554 | * |
1555 | * Return MDWIDTH configuration value in bits. |
1556 | */ |
1557 | static inline u32 dwc3_mdwidth(struct dwc3 *dwc) |
1558 | { |
1559 | u32 mdwidth; |
1560 | |
1561 | mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0); |
1562 | if (DWC3_IP_IS(DWC32)) |
1563 | mdwidth += DWC3_GHWPARAMS6_MDWIDTH(dwc->hwparams.hwparams6); |
1564 | |
1565 | return mdwidth; |
1566 | } |
1567 | |
1568 | bool dwc3_has_imod(struct dwc3 *dwc); |
1569 | |
1570 | int dwc3_event_buffers_setup(struct dwc3 *dwc); |
1571 | void dwc3_event_buffers_cleanup(struct dwc3 *dwc); |
1572 | |
1573 | int dwc3_core_soft_reset(struct dwc3 *dwc); |
1574 | |
1575 | #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) |
1576 | int dwc3_host_init(struct dwc3 *dwc); |
1577 | void dwc3_host_exit(struct dwc3 *dwc); |
1578 | #else |
1579 | static inline int dwc3_host_init(struct dwc3 *dwc) |
1580 | { return 0; } |
1581 | static inline void dwc3_host_exit(struct dwc3 *dwc) |
1582 | { } |
1583 | #endif |
1584 | |
1585 | #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) |
1586 | int dwc3_gadget_init(struct dwc3 *dwc); |
1587 | void dwc3_gadget_exit(struct dwc3 *dwc); |
1588 | int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode); |
1589 | int dwc3_gadget_get_link_state(struct dwc3 *dwc); |
1590 | int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); |
1591 | int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd, |
1592 | struct dwc3_gadget_ep_cmd_params *params); |
1593 | int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd, |
1594 | u32 param); |
1595 | void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc); |
1596 | void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep, int status); |
1597 | #else |
1598 | static inline int dwc3_gadget_init(struct dwc3 *dwc) |
1599 | { return 0; } |
1600 | static inline void dwc3_gadget_exit(struct dwc3 *dwc) |
1601 | { } |
1602 | static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) |
1603 | { return 0; } |
1604 | static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc) |
1605 | { return 0; } |
1606 | static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc, |
1607 | enum dwc3_link_state state) |
1608 | { return 0; } |
1609 | |
1610 | static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd, |
1611 | struct dwc3_gadget_ep_cmd_params *params) |
1612 | { return 0; } |
1613 | static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, |
1614 | int cmd, u32 param) |
1615 | { return 0; } |
1616 | static inline void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc) |
1617 | { } |
1618 | #endif |
1619 | |
1620 | #if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) |
1621 | int dwc3_drd_init(struct dwc3 *dwc); |
1622 | void dwc3_drd_exit(struct dwc3 *dwc); |
1623 | void dwc3_otg_init(struct dwc3 *dwc); |
1624 | void dwc3_otg_exit(struct dwc3 *dwc); |
1625 | void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus); |
1626 | void dwc3_otg_host_init(struct dwc3 *dwc); |
1627 | #else |
1628 | static inline int dwc3_drd_init(struct dwc3 *dwc) |
1629 | { return 0; } |
1630 | static inline void dwc3_drd_exit(struct dwc3 *dwc) |
1631 | { } |
1632 | static inline void dwc3_otg_init(struct dwc3 *dwc) |
1633 | { } |
1634 | static inline void dwc3_otg_exit(struct dwc3 *dwc) |
1635 | { } |
1636 | static inline void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus) |
1637 | { } |
1638 | static inline void dwc3_otg_host_init(struct dwc3 *dwc) |
1639 | { } |
1640 | #endif |
1641 | |
1642 | /* power management interface */ |
1643 | #if !IS_ENABLED(CONFIG_USB_DWC3_HOST) |
1644 | int dwc3_gadget_suspend(struct dwc3 *dwc); |
1645 | int dwc3_gadget_resume(struct dwc3 *dwc); |
1646 | void dwc3_gadget_process_pending_events(struct dwc3 *dwc); |
1647 | #else |
1648 | static inline int dwc3_gadget_suspend(struct dwc3 *dwc) |
1649 | { |
1650 | return 0; |
1651 | } |
1652 | |
1653 | static inline int dwc3_gadget_resume(struct dwc3 *dwc) |
1654 | { |
1655 | return 0; |
1656 | } |
1657 | |
1658 | static inline void dwc3_gadget_process_pending_events(struct dwc3 *dwc) |
1659 | { |
1660 | } |
1661 | #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */ |
1662 | |
1663 | #if IS_ENABLED(CONFIG_USB_DWC3_ULPI) |
1664 | int dwc3_ulpi_init(struct dwc3 *dwc); |
1665 | void dwc3_ulpi_exit(struct dwc3 *dwc); |
1666 | #else |
1667 | static inline int dwc3_ulpi_init(struct dwc3 *dwc) |
1668 | { return 0; } |
1669 | static inline void dwc3_ulpi_exit(struct dwc3 *dwc) |
1670 | { } |
1671 | #endif |
1672 | |
1673 | #endif /* __DRIVERS_USB_DWC3_CORE_H */ |
1674 | |