1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#include <linux/kernel.h>
12#include <linux/slab.h>
13#include <linux/spinlock.h>
14#include <linux/platform_device.h>
15#include <linux/pm_runtime.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/list.h>
19#include <linux/dma-mapping.h>
20
21#include <linux/usb/ch9.h>
22#include <linux/usb/gadget.h>
23#include <linux/usb/composite.h>
24
25#include "core.h"
26#include "debug.h"
27#include "gadget.h"
28#include "io.h"
29
30static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
31static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
32 struct dwc3_ep *dep, struct dwc3_request *req);
33static int dwc3_ep0_delegate_req(struct dwc3 *dwc,
34 struct usb_ctrlrequest *ctrl);
35
36static void dwc3_ep0_prepare_one_trb(struct dwc3_ep *dep,
37 dma_addr_t buf_dma, u32 len, u32 type, bool chain)
38{
39 struct dwc3_trb *trb;
40 struct dwc3 *dwc;
41
42 dwc = dep->dwc;
43 trb = &dwc->ep0_trb[dep->trb_enqueue];
44
45 if (chain)
46 dep->trb_enqueue++;
47
48 trb->bpl = lower_32_bits(buf_dma);
49 trb->bph = upper_32_bits(buf_dma);
50 trb->size = len;
51 trb->ctrl = type;
52
53 trb->ctrl |= (DWC3_TRB_CTRL_HWO
54 | DWC3_TRB_CTRL_ISP_IMI);
55
56 if (chain)
57 trb->ctrl |= DWC3_TRB_CTRL_CHN;
58 else
59 trb->ctrl |= (DWC3_TRB_CTRL_IOC
60 | DWC3_TRB_CTRL_LST);
61
62 trace_dwc3_prepare_trb(dep, trb);
63}
64
65static int dwc3_ep0_start_trans(struct dwc3_ep *dep)
66{
67 struct dwc3_gadget_ep_cmd_params params;
68 struct dwc3 *dwc;
69 int ret;
70
71 if (dep->flags & DWC3_EP_TRANSFER_STARTED)
72 return 0;
73
74 dwc = dep->dwc;
75
76 memset(&params, 0, sizeof(params));
77 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
78 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
79
80 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, params: &params);
81 if (ret < 0)
82 return ret;
83
84 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
85
86 return 0;
87}
88
89static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
90 struct dwc3_request *req)
91{
92 struct dwc3 *dwc = dep->dwc;
93
94 req->request.actual = 0;
95 req->request.status = -EINPROGRESS;
96 req->epnum = dep->number;
97
98 list_add_tail(new: &req->list, head: &dep->pending_list);
99
100 /*
101 * Gadget driver might not be quick enough to queue a request
102 * before we get a Transfer Not Ready event on this endpoint.
103 *
104 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
105 * flag is set, it's telling us that as soon as Gadget queues the
106 * required request, we should kick the transfer here because the
107 * IRQ we were waiting for is long gone.
108 */
109 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
110 unsigned int direction;
111
112 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
113
114 if (dwc->ep0state != EP0_DATA_PHASE) {
115 dev_WARN(dwc->dev, "Unexpected pending request\n");
116 return 0;
117 }
118
119 __dwc3_ep0_do_control_data(dwc, dep: dwc->eps[direction], req);
120
121 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
122 DWC3_EP0_DIR_IN);
123
124 return 0;
125 }
126
127 /*
128 * In case gadget driver asked us to delay the STATUS phase,
129 * handle it here.
130 */
131 if (dwc->delayed_status) {
132 unsigned int direction;
133
134 direction = !dwc->ep0_expect_in;
135 dwc->delayed_status = false;
136 usb_gadget_set_state(gadget: dwc->gadget, state: USB_STATE_CONFIGURED);
137
138 if (dwc->ep0state == EP0_STATUS_PHASE)
139 __dwc3_ep0_do_control_status(dwc, dep: dwc->eps[direction]);
140
141 return 0;
142 }
143
144 /*
145 * Unfortunately we have uncovered a limitation wrt the Data Phase.
146 *
147 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
148 * come before issueing Start Transfer command, but if we do, we will
149 * miss situations where the host starts another SETUP phase instead of
150 * the DATA phase. Such cases happen at least on TD.7.6 of the Link
151 * Layer Compliance Suite.
152 *
153 * The problem surfaces due to the fact that in case of back-to-back
154 * SETUP packets there will be no XferNotReady(DATA) generated and we
155 * will be stuck waiting for XferNotReady(DATA) forever.
156 *
157 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
158 * it tells us to start Data Phase right away. It also mentions that if
159 * we receive a SETUP phase instead of the DATA phase, core will issue
160 * XferComplete for the DATA phase, before actually initiating it in
161 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
162 * can only be used to print some debugging logs, as the core expects
163 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
164 * just so it completes right away, without transferring anything and,
165 * only then, we can go back to the SETUP phase.
166 *
167 * Because of this scenario, SNPS decided to change the programming
168 * model of control transfers and support on-demand transfers only for
169 * the STATUS phase. To fix the issue we have now, we will always wait
170 * for gadget driver to queue the DATA phase's struct usb_request, then
171 * start it right away.
172 *
173 * If we're actually in a 2-stage transfer, we will wait for
174 * XferNotReady(STATUS).
175 */
176 if (dwc->three_stage_setup) {
177 unsigned int direction;
178
179 direction = dwc->ep0_expect_in;
180 dwc->ep0state = EP0_DATA_PHASE;
181
182 __dwc3_ep0_do_control_data(dwc, dep: dwc->eps[direction], req);
183
184 dep->flags &= ~DWC3_EP0_DIR_IN;
185 }
186
187 return 0;
188}
189
190int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
191 gfp_t gfp_flags)
192{
193 struct dwc3_request *req = to_dwc3_request(request);
194 struct dwc3_ep *dep = to_dwc3_ep(ep);
195 struct dwc3 *dwc = dep->dwc;
196
197 unsigned long flags;
198
199 int ret;
200
201 spin_lock_irqsave(&dwc->lock, flags);
202 if (!dep->endpoint.desc || !dwc->pullups_connected || !dwc->connected) {
203 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
204 dep->name);
205 ret = -ESHUTDOWN;
206 goto out;
207 }
208
209 /* we share one TRB for ep0/1 */
210 if (!list_empty(head: &dep->pending_list)) {
211 ret = -EBUSY;
212 goto out;
213 }
214
215 ret = __dwc3_gadget_ep0_queue(dep, req);
216
217out:
218 spin_unlock_irqrestore(lock: &dwc->lock, flags);
219
220 return ret;
221}
222
223void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
224{
225 struct dwc3_ep *dep;
226
227 /* reinitialize physical ep1 */
228 dep = dwc->eps[1];
229 dep->flags = DWC3_EP_ENABLED;
230
231 /* stall is always issued on EP0 */
232 dep = dwc->eps[0];
233 __dwc3_gadget_ep_set_halt(dep, value: 1, protocol: false);
234 dep->flags = DWC3_EP_ENABLED;
235 dwc->delayed_status = false;
236
237 if (!list_empty(head: &dep->pending_list)) {
238 struct dwc3_request *req;
239
240 req = next_request(list: &dep->pending_list);
241 dwc3_gadget_giveback(dep, req, status: -ECONNRESET);
242 }
243
244 dwc->eps[0]->trb_enqueue = 0;
245 dwc->eps[1]->trb_enqueue = 0;
246 dwc->ep0state = EP0_SETUP_PHASE;
247 dwc3_ep0_out_start(dwc);
248}
249
250int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
251{
252 struct dwc3_ep *dep = to_dwc3_ep(ep);
253 struct dwc3 *dwc = dep->dwc;
254
255 dwc3_ep0_stall_and_restart(dwc);
256
257 return 0;
258}
259
260int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
261{
262 struct dwc3_ep *dep = to_dwc3_ep(ep);
263 struct dwc3 *dwc = dep->dwc;
264 unsigned long flags;
265 int ret;
266
267 spin_lock_irqsave(&dwc->lock, flags);
268 ret = __dwc3_gadget_ep0_set_halt(ep, value);
269 spin_unlock_irqrestore(lock: &dwc->lock, flags);
270
271 return ret;
272}
273
274void dwc3_ep0_out_start(struct dwc3 *dwc)
275{
276 struct dwc3_ep *dep;
277 int ret;
278 int i;
279
280 complete(&dwc->ep0_in_setup);
281
282 dep = dwc->eps[0];
283 dwc3_ep0_prepare_one_trb(dep, buf_dma: dwc->ep0_trb_addr, len: 8,
284 DWC3_TRBCTL_CONTROL_SETUP, chain: false);
285 ret = dwc3_ep0_start_trans(dep);
286 WARN_ON(ret < 0);
287 for (i = 2; i < DWC3_ENDPOINTS_NUM; i++) {
288 struct dwc3_ep *dwc3_ep;
289
290 dwc3_ep = dwc->eps[i];
291 if (!dwc3_ep)
292 continue;
293
294 if (!(dwc3_ep->flags & DWC3_EP_DELAY_STOP))
295 continue;
296
297 dwc3_ep->flags &= ~DWC3_EP_DELAY_STOP;
298 if (dwc->connected)
299 dwc3_stop_active_transfer(dep: dwc3_ep, force: true, interrupt: true);
300 else
301 dwc3_remove_requests(dwc, dep: dwc3_ep, status: -ESHUTDOWN);
302 }
303}
304
305static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
306{
307 struct dwc3_ep *dep;
308 u32 windex = le16_to_cpu(wIndex_le);
309 u32 epnum;
310
311 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
312 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
313 epnum |= 1;
314
315 dep = dwc->eps[epnum];
316 if (dep == NULL)
317 return NULL;
318
319 if (dep->flags & DWC3_EP_ENABLED)
320 return dep;
321
322 return NULL;
323}
324
325static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
326{
327}
328/*
329 * ch 9.4.5
330 */
331static int dwc3_ep0_handle_status(struct dwc3 *dwc,
332 struct usb_ctrlrequest *ctrl)
333{
334 struct dwc3_ep *dep;
335 u32 recip;
336 u32 value;
337 u32 reg;
338 u16 usb_status = 0;
339 __le16 *response_pkt;
340
341 /* We don't support PTM_STATUS */
342 value = le16_to_cpu(ctrl->wValue);
343 if (value != 0)
344 return -EINVAL;
345
346 recip = ctrl->bRequestType & USB_RECIP_MASK;
347 switch (recip) {
348 case USB_RECIP_DEVICE:
349 /*
350 * LTM will be set once we know how to set this in HW.
351 */
352 usb_status |= dwc->gadget->is_selfpowered;
353
354 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
355 (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
356 reg = dwc3_readl(base: dwc->regs, DWC3_DCTL);
357 if (reg & DWC3_DCTL_INITU1ENA)
358 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
359 if (reg & DWC3_DCTL_INITU2ENA)
360 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
361 } else {
362 usb_status |= dwc->gadget->wakeup_armed <<
363 USB_DEVICE_REMOTE_WAKEUP;
364 }
365
366 break;
367
368 case USB_RECIP_INTERFACE:
369 /*
370 * Function Remote Wake Capable D0
371 * Function Remote Wakeup D1
372 */
373 return dwc3_ep0_delegate_req(dwc, ctrl);
374
375 case USB_RECIP_ENDPOINT:
376 dep = dwc3_wIndex_to_dep(dwc, wIndex_le: ctrl->wIndex);
377 if (!dep)
378 return -EINVAL;
379
380 if (dep->flags & DWC3_EP_STALL)
381 usb_status = 1 << USB_ENDPOINT_HALT;
382 break;
383 default:
384 return -EINVAL;
385 }
386
387 response_pkt = (__le16 *) dwc->setup_buf;
388 *response_pkt = cpu_to_le16(usb_status);
389
390 dep = dwc->eps[0];
391 dwc->ep0_usb_req.dep = dep;
392 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
393 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
394 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
395
396 return __dwc3_gadget_ep0_queue(dep, req: &dwc->ep0_usb_req);
397}
398
399static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state,
400 int set)
401{
402 u32 reg;
403
404 if (state != USB_STATE_CONFIGURED)
405 return -EINVAL;
406 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
407 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
408 return -EINVAL;
409 if (set && dwc->dis_u1_entry_quirk)
410 return -EINVAL;
411
412 reg = dwc3_readl(base: dwc->regs, DWC3_DCTL);
413 if (set)
414 reg |= DWC3_DCTL_INITU1ENA;
415 else
416 reg &= ~DWC3_DCTL_INITU1ENA;
417 dwc3_writel(base: dwc->regs, DWC3_DCTL, value: reg);
418
419 return 0;
420}
421
422static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state,
423 int set)
424{
425 u32 reg;
426
427
428 if (state != USB_STATE_CONFIGURED)
429 return -EINVAL;
430 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
431 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
432 return -EINVAL;
433 if (set && dwc->dis_u2_entry_quirk)
434 return -EINVAL;
435
436 reg = dwc3_readl(base: dwc->regs, DWC3_DCTL);
437 if (set)
438 reg |= DWC3_DCTL_INITU2ENA;
439 else
440 reg &= ~DWC3_DCTL_INITU2ENA;
441 dwc3_writel(base: dwc->regs, DWC3_DCTL, value: reg);
442
443 return 0;
444}
445
446static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state,
447 u32 wIndex, int set)
448{
449 if ((wIndex & 0xff) != 0)
450 return -EINVAL;
451 if (!set)
452 return -EINVAL;
453
454 switch (wIndex >> 8) {
455 case USB_TEST_J:
456 case USB_TEST_K:
457 case USB_TEST_SE0_NAK:
458 case USB_TEST_PACKET:
459 case USB_TEST_FORCE_ENABLE:
460 dwc->test_mode_nr = wIndex >> 8;
461 dwc->test_mode = true;
462 break;
463 default:
464 return -EINVAL;
465 }
466
467 return 0;
468}
469
470static int dwc3_ep0_handle_device(struct dwc3 *dwc,
471 struct usb_ctrlrequest *ctrl, int set)
472{
473 enum usb_device_state state;
474 u32 wValue;
475 u32 wIndex;
476 int ret = 0;
477
478 wValue = le16_to_cpu(ctrl->wValue);
479 wIndex = le16_to_cpu(ctrl->wIndex);
480 state = dwc->gadget->state;
481
482 switch (wValue) {
483 case USB_DEVICE_REMOTE_WAKEUP:
484 if (dwc->wakeup_configured)
485 dwc->gadget->wakeup_armed = set;
486 else
487 ret = -EINVAL;
488 break;
489 /*
490 * 9.4.1 says only for SS, in AddressState only for
491 * default control pipe
492 */
493 case USB_DEVICE_U1_ENABLE:
494 ret = dwc3_ep0_handle_u1(dwc, state, set);
495 break;
496 case USB_DEVICE_U2_ENABLE:
497 ret = dwc3_ep0_handle_u2(dwc, state, set);
498 break;
499 case USB_DEVICE_LTM_ENABLE:
500 ret = -EINVAL;
501 break;
502 case USB_DEVICE_TEST_MODE:
503 ret = dwc3_ep0_handle_test(dwc, state, wIndex, set);
504 break;
505 default:
506 ret = -EINVAL;
507 }
508
509 return ret;
510}
511
512static int dwc3_ep0_handle_intf(struct dwc3 *dwc,
513 struct usb_ctrlrequest *ctrl, int set)
514{
515 u32 wValue;
516 int ret = 0;
517
518 wValue = le16_to_cpu(ctrl->wValue);
519
520 switch (wValue) {
521 case USB_INTRF_FUNC_SUSPEND:
522 ret = dwc3_ep0_delegate_req(dwc, ctrl);
523 break;
524 default:
525 ret = -EINVAL;
526 }
527
528 return ret;
529}
530
531static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc,
532 struct usb_ctrlrequest *ctrl, int set)
533{
534 struct dwc3_ep *dep;
535 u32 wValue;
536 int ret;
537
538 wValue = le16_to_cpu(ctrl->wValue);
539
540 switch (wValue) {
541 case USB_ENDPOINT_HALT:
542 dep = dwc3_wIndex_to_dep(dwc, wIndex_le: ctrl->wIndex);
543 if (!dep)
544 return -EINVAL;
545
546 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
547 break;
548
549 ret = __dwc3_gadget_ep_set_halt(dep, value: set, protocol: true);
550 if (ret)
551 return -EINVAL;
552
553 /* ClearFeature(Halt) may need delayed status */
554 if (!set && (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
555 return USB_GADGET_DELAYED_STATUS;
556
557 break;
558 default:
559 return -EINVAL;
560 }
561
562 return 0;
563}
564
565static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
566 struct usb_ctrlrequest *ctrl, int set)
567{
568 u32 recip;
569 int ret;
570
571 recip = ctrl->bRequestType & USB_RECIP_MASK;
572
573 switch (recip) {
574 case USB_RECIP_DEVICE:
575 ret = dwc3_ep0_handle_device(dwc, ctrl, set);
576 break;
577 case USB_RECIP_INTERFACE:
578 ret = dwc3_ep0_handle_intf(dwc, ctrl, set);
579 break;
580 case USB_RECIP_ENDPOINT:
581 ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set);
582 break;
583 default:
584 ret = -EINVAL;
585 }
586
587 return ret;
588}
589
590static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
591{
592 enum usb_device_state state = dwc->gadget->state;
593 u32 addr;
594 u32 reg;
595
596 addr = le16_to_cpu(ctrl->wValue);
597 if (addr > 127) {
598 dev_err(dwc->dev, "invalid device address %d\n", addr);
599 return -EINVAL;
600 }
601
602 if (state == USB_STATE_CONFIGURED) {
603 dev_err(dwc->dev, "can't SetAddress() from Configured State\n");
604 return -EINVAL;
605 }
606
607 reg = dwc3_readl(base: dwc->regs, DWC3_DCFG);
608 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
609 reg |= DWC3_DCFG_DEVADDR(addr);
610 dwc3_writel(base: dwc->regs, DWC3_DCFG, value: reg);
611
612 if (addr)
613 usb_gadget_set_state(gadget: dwc->gadget, state: USB_STATE_ADDRESS);
614 else
615 usb_gadget_set_state(gadget: dwc->gadget, state: USB_STATE_DEFAULT);
616
617 return 0;
618}
619
620static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
621{
622 int ret = -EINVAL;
623
624 if (dwc->async_callbacks) {
625 spin_unlock(lock: &dwc->lock);
626 ret = dwc->gadget_driver->setup(dwc->gadget, ctrl);
627 spin_lock(lock: &dwc->lock);
628 }
629 return ret;
630}
631
632static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
633{
634 enum usb_device_state state = dwc->gadget->state;
635 u32 cfg;
636 int ret;
637 u32 reg;
638
639 cfg = le16_to_cpu(ctrl->wValue);
640
641 switch (state) {
642 case USB_STATE_DEFAULT:
643 return -EINVAL;
644
645 case USB_STATE_ADDRESS:
646 dwc3_gadget_clear_tx_fifos(dwc);
647
648 ret = dwc3_ep0_delegate_req(dwc, ctrl);
649 /* if the cfg matches and the cfg is non zero */
650 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
651
652 /*
653 * only change state if set_config has already
654 * been processed. If gadget driver returns
655 * USB_GADGET_DELAYED_STATUS, we will wait
656 * to change the state on the next usb_ep_queue()
657 */
658 if (ret == 0)
659 usb_gadget_set_state(gadget: dwc->gadget,
660 state: USB_STATE_CONFIGURED);
661
662 /*
663 * Enable transition to U1/U2 state when
664 * nothing is pending from application.
665 */
666 reg = dwc3_readl(base: dwc->regs, DWC3_DCTL);
667 if (!dwc->dis_u1_entry_quirk)
668 reg |= DWC3_DCTL_ACCEPTU1ENA;
669 if (!dwc->dis_u2_entry_quirk)
670 reg |= DWC3_DCTL_ACCEPTU2ENA;
671 dwc3_writel(base: dwc->regs, DWC3_DCTL, value: reg);
672 }
673 break;
674
675 case USB_STATE_CONFIGURED:
676 ret = dwc3_ep0_delegate_req(dwc, ctrl);
677 if (!cfg && !ret)
678 usb_gadget_set_state(gadget: dwc->gadget,
679 state: USB_STATE_ADDRESS);
680 break;
681 default:
682 ret = -EINVAL;
683 }
684 return ret;
685}
686
687static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
688{
689 struct dwc3_ep *dep = to_dwc3_ep(ep);
690 struct dwc3 *dwc = dep->dwc;
691
692 u32 param = 0;
693 u32 reg;
694
695 struct timing {
696 u8 u1sel;
697 u8 u1pel;
698 __le16 u2sel;
699 __le16 u2pel;
700 } __packed timing;
701
702 int ret;
703
704 memcpy(&timing, req->buf, sizeof(timing));
705
706 dwc->u1sel = timing.u1sel;
707 dwc->u1pel = timing.u1pel;
708 dwc->u2sel = le16_to_cpu(timing.u2sel);
709 dwc->u2pel = le16_to_cpu(timing.u2pel);
710
711 reg = dwc3_readl(base: dwc->regs, DWC3_DCTL);
712 if (reg & DWC3_DCTL_INITU2ENA)
713 param = dwc->u2pel;
714 if (reg & DWC3_DCTL_INITU1ENA)
715 param = dwc->u1pel;
716
717 /*
718 * According to Synopsys Databook, if parameter is
719 * greater than 125, a value of zero should be
720 * programmed in the register.
721 */
722 if (param > 125)
723 param = 0;
724
725 /* now that we have the time, issue DGCMD Set Sel */
726 ret = dwc3_send_gadget_generic_command(dwc,
727 DWC3_DGCMD_SET_PERIODIC_PAR, param);
728 WARN_ON(ret < 0);
729}
730
731static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
732{
733 struct dwc3_ep *dep;
734 enum usb_device_state state = dwc->gadget->state;
735 u16 wLength;
736
737 if (state == USB_STATE_DEFAULT)
738 return -EINVAL;
739
740 wLength = le16_to_cpu(ctrl->wLength);
741
742 if (wLength != 6) {
743 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
744 wLength);
745 return -EINVAL;
746 }
747
748 /*
749 * To handle Set SEL we need to receive 6 bytes from Host. So let's
750 * queue a usb_request for 6 bytes.
751 *
752 * Remember, though, this controller can't handle non-wMaxPacketSize
753 * aligned transfers on the OUT direction, so we queue a request for
754 * wMaxPacketSize instead.
755 */
756 dep = dwc->eps[0];
757 dwc->ep0_usb_req.dep = dep;
758 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
759 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
760 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
761
762 return __dwc3_gadget_ep0_queue(dep, req: &dwc->ep0_usb_req);
763}
764
765static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
766{
767 u16 wLength;
768 u16 wValue;
769 u16 wIndex;
770
771 wValue = le16_to_cpu(ctrl->wValue);
772 wLength = le16_to_cpu(ctrl->wLength);
773 wIndex = le16_to_cpu(ctrl->wIndex);
774
775 if (wIndex || wLength)
776 return -EINVAL;
777
778 dwc->gadget->isoch_delay = wValue;
779
780 return 0;
781}
782
783static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
784{
785 int ret;
786
787 switch (ctrl->bRequest) {
788 case USB_REQ_GET_STATUS:
789 ret = dwc3_ep0_handle_status(dwc, ctrl);
790 break;
791 case USB_REQ_CLEAR_FEATURE:
792 ret = dwc3_ep0_handle_feature(dwc, ctrl, set: 0);
793 break;
794 case USB_REQ_SET_FEATURE:
795 ret = dwc3_ep0_handle_feature(dwc, ctrl, set: 1);
796 break;
797 case USB_REQ_SET_ADDRESS:
798 ret = dwc3_ep0_set_address(dwc, ctrl);
799 break;
800 case USB_REQ_SET_CONFIGURATION:
801 ret = dwc3_ep0_set_config(dwc, ctrl);
802 break;
803 case USB_REQ_SET_SEL:
804 ret = dwc3_ep0_set_sel(dwc, ctrl);
805 break;
806 case USB_REQ_SET_ISOCH_DELAY:
807 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
808 break;
809 default:
810 ret = dwc3_ep0_delegate_req(dwc, ctrl);
811 break;
812 }
813
814 return ret;
815}
816
817static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
818 const struct dwc3_event_depevt *event)
819{
820 struct usb_ctrlrequest *ctrl = (void *) dwc->ep0_trb;
821 int ret = -EINVAL;
822 u32 len;
823
824 if (!dwc->gadget_driver || !dwc->softconnect || !dwc->connected)
825 goto out;
826
827 trace_dwc3_ctrl_req(ctrl);
828
829 len = le16_to_cpu(ctrl->wLength);
830 if (!len) {
831 dwc->three_stage_setup = false;
832 dwc->ep0_expect_in = false;
833 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
834 } else {
835 dwc->three_stage_setup = true;
836 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
837 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
838 }
839
840 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
841 ret = dwc3_ep0_std_request(dwc, ctrl);
842 else
843 ret = dwc3_ep0_delegate_req(dwc, ctrl);
844
845 if (ret == USB_GADGET_DELAYED_STATUS)
846 dwc->delayed_status = true;
847
848out:
849 if (ret < 0)
850 dwc3_ep0_stall_and_restart(dwc);
851}
852
853static void dwc3_ep0_complete_data(struct dwc3 *dwc,
854 const struct dwc3_event_depevt *event)
855{
856 struct dwc3_request *r;
857 struct usb_request *ur;
858 struct dwc3_trb *trb;
859 struct dwc3_ep *ep0;
860 u32 transferred = 0;
861 u32 status;
862 u32 length;
863 u8 epnum;
864
865 epnum = event->endpoint_number;
866 ep0 = dwc->eps[0];
867
868 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
869 trb = dwc->ep0_trb;
870 trace_dwc3_complete_trb(dep: ep0, trb);
871
872 r = next_request(list: &ep0->pending_list);
873 if (!r)
874 return;
875
876 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
877 if (status == DWC3_TRBSTS_SETUP_PENDING) {
878 dwc->setup_packet_pending = true;
879 if (r)
880 dwc3_gadget_giveback(dep: ep0, req: r, status: -ECONNRESET);
881
882 return;
883 }
884
885 ur = &r->request;
886
887 length = trb->size & DWC3_TRB_SIZE_MASK;
888 transferred = ur->length - length;
889 ur->actual += transferred;
890
891 if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
892 ur->length && ur->zero) || dwc->ep0_bounced) {
893 trb++;
894 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
895 trace_dwc3_complete_trb(dep: ep0, trb);
896
897 if (r->direction)
898 dwc->eps[1]->trb_enqueue = 0;
899 else
900 dwc->eps[0]->trb_enqueue = 0;
901
902 dwc->ep0_bounced = false;
903 }
904
905 if ((epnum & 1) && ur->actual < ur->length)
906 dwc3_ep0_stall_and_restart(dwc);
907 else
908 dwc3_gadget_giveback(dep: ep0, req: r, status: 0);
909}
910
911static void dwc3_ep0_complete_status(struct dwc3 *dwc,
912 const struct dwc3_event_depevt *event)
913{
914 struct dwc3_request *r;
915 struct dwc3_ep *dep;
916 struct dwc3_trb *trb;
917 u32 status;
918
919 dep = dwc->eps[0];
920 trb = dwc->ep0_trb;
921
922 trace_dwc3_complete_trb(dep, trb);
923
924 if (!list_empty(head: &dep->pending_list)) {
925 r = next_request(list: &dep->pending_list);
926
927 dwc3_gadget_giveback(dep, req: r, status: 0);
928 }
929
930 if (dwc->test_mode) {
931 int ret;
932
933 ret = dwc3_gadget_set_test_mode(dwc, mode: dwc->test_mode_nr);
934 if (ret < 0) {
935 dev_err(dwc->dev, "invalid test #%d\n",
936 dwc->test_mode_nr);
937 dwc3_ep0_stall_and_restart(dwc);
938 return;
939 }
940 }
941
942 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
943 if (status == DWC3_TRBSTS_SETUP_PENDING)
944 dwc->setup_packet_pending = true;
945
946 dwc->ep0state = EP0_SETUP_PHASE;
947 dwc3_ep0_out_start(dwc);
948}
949
950static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
951 const struct dwc3_event_depevt *event)
952{
953 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
954
955 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
956 dep->resource_index = 0;
957 dwc->setup_packet_pending = false;
958
959 switch (dwc->ep0state) {
960 case EP0_SETUP_PHASE:
961 dwc3_ep0_inspect_setup(dwc, event);
962 break;
963
964 case EP0_DATA_PHASE:
965 dwc3_ep0_complete_data(dwc, event);
966 break;
967
968 case EP0_STATUS_PHASE:
969 dwc3_ep0_complete_status(dwc, event);
970 break;
971 default:
972 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
973 }
974}
975
976static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
977 struct dwc3_ep *dep, struct dwc3_request *req)
978{
979 unsigned int trb_length = 0;
980 int ret;
981
982 req->direction = !!dep->number;
983
984 if (req->request.length == 0) {
985 if (!req->direction)
986 trb_length = dep->endpoint.maxpacket;
987
988 dwc3_ep0_prepare_one_trb(dep, buf_dma: dwc->bounce_addr, len: trb_length,
989 DWC3_TRBCTL_CONTROL_DATA, chain: false);
990 ret = dwc3_ep0_start_trans(dep);
991 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
992 && (dep->number == 0)) {
993 u32 maxpacket;
994 u32 rem;
995
996 ret = usb_gadget_map_request_by_dev(dev: dwc->sysdev,
997 req: &req->request, is_in: dep->number);
998 if (ret)
999 return;
1000
1001 maxpacket = dep->endpoint.maxpacket;
1002 rem = req->request.length % maxpacket;
1003 dwc->ep0_bounced = true;
1004
1005 /* prepare normal TRB */
1006 dwc3_ep0_prepare_one_trb(dep, buf_dma: req->request.dma,
1007 len: req->request.length,
1008 DWC3_TRBCTL_CONTROL_DATA,
1009 chain: true);
1010
1011 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
1012
1013 /* Now prepare one extra TRB to align transfer size */
1014 dwc3_ep0_prepare_one_trb(dep, buf_dma: dwc->bounce_addr,
1015 len: maxpacket - rem,
1016 DWC3_TRBCTL_CONTROL_DATA,
1017 chain: false);
1018 ret = dwc3_ep0_start_trans(dep);
1019 } else if (IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) &&
1020 req->request.length && req->request.zero) {
1021
1022 ret = usb_gadget_map_request_by_dev(dev: dwc->sysdev,
1023 req: &req->request, is_in: dep->number);
1024 if (ret)
1025 return;
1026
1027 /* prepare normal TRB */
1028 dwc3_ep0_prepare_one_trb(dep, buf_dma: req->request.dma,
1029 len: req->request.length,
1030 DWC3_TRBCTL_CONTROL_DATA,
1031 chain: true);
1032
1033 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
1034
1035 if (!req->direction)
1036 trb_length = dep->endpoint.maxpacket;
1037
1038 /* Now prepare one extra TRB to align transfer size */
1039 dwc3_ep0_prepare_one_trb(dep, buf_dma: dwc->bounce_addr,
1040 len: trb_length, DWC3_TRBCTL_CONTROL_DATA,
1041 chain: false);
1042 ret = dwc3_ep0_start_trans(dep);
1043 } else {
1044 ret = usb_gadget_map_request_by_dev(dev: dwc->sysdev,
1045 req: &req->request, is_in: dep->number);
1046 if (ret)
1047 return;
1048
1049 dwc3_ep0_prepare_one_trb(dep, buf_dma: req->request.dma,
1050 len: req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1051 chain: false);
1052
1053 req->trb = &dwc->ep0_trb[dep->trb_enqueue];
1054
1055 ret = dwc3_ep0_start_trans(dep);
1056 }
1057
1058 WARN_ON(ret < 0);
1059}
1060
1061static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1062{
1063 struct dwc3 *dwc = dep->dwc;
1064 u32 type;
1065
1066 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1067 : DWC3_TRBCTL_CONTROL_STATUS2;
1068
1069 dwc3_ep0_prepare_one_trb(dep, buf_dma: dwc->ep0_trb_addr, len: 0, type, chain: false);
1070 return dwc3_ep0_start_trans(dep);
1071}
1072
1073static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1074{
1075 WARN_ON(dwc3_ep0_start_control_status(dep));
1076}
1077
1078static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1079 const struct dwc3_event_depevt *event)
1080{
1081 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
1082
1083 __dwc3_ep0_do_control_status(dwc, dep);
1084}
1085
1086void dwc3_ep0_send_delayed_status(struct dwc3 *dwc)
1087{
1088 unsigned int direction = !dwc->ep0_expect_in;
1089
1090 dwc->delayed_status = false;
1091 dwc->clear_stall_protocol = 0;
1092
1093 if (dwc->ep0state != EP0_STATUS_PHASE)
1094 return;
1095
1096 __dwc3_ep0_do_control_status(dwc, dep: dwc->eps[direction]);
1097}
1098
1099void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1100{
1101 struct dwc3_gadget_ep_cmd_params params;
1102 u32 cmd;
1103 int ret;
1104
1105 /*
1106 * For status/DATA OUT stage, TRB will be queued on ep0 out
1107 * endpoint for which resource index is zero. Hence allow
1108 * queuing ENDXFER command for ep0 out endpoint.
1109 */
1110 if (!dep->resource_index && dep->number)
1111 return;
1112
1113 cmd = DWC3_DEPCMD_ENDTRANSFER;
1114 cmd |= DWC3_DEPCMD_CMDIOC;
1115 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1116 memset(&params, 0, sizeof(params));
1117 ret = dwc3_send_gadget_ep_cmd(dep, cmd, params: &params);
1118 WARN_ON_ONCE(ret);
1119 dep->resource_index = 0;
1120}
1121
1122static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1123 const struct dwc3_event_depevt *event)
1124{
1125 switch (event->status) {
1126 case DEPEVT_STATUS_CONTROL_DATA:
1127 if (!dwc->softconnect || !dwc->connected)
1128 return;
1129 /*
1130 * We already have a DATA transfer in the controller's cache,
1131 * if we receive a XferNotReady(DATA) we will ignore it, unless
1132 * it's for the wrong direction.
1133 *
1134 * In that case, we must issue END_TRANSFER command to the Data
1135 * Phase we already have started and issue SetStall on the
1136 * control endpoint.
1137 */
1138 if (dwc->ep0_expect_in != event->endpoint_number) {
1139 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
1140
1141 dev_err(dwc->dev, "unexpected direction for Data Phase\n");
1142 dwc3_ep0_end_control_data(dwc, dep);
1143 dwc3_ep0_stall_and_restart(dwc);
1144 return;
1145 }
1146
1147 break;
1148
1149 case DEPEVT_STATUS_CONTROL_STATUS:
1150 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1151 return;
1152
1153 if (dwc->setup_packet_pending) {
1154 dwc3_ep0_stall_and_restart(dwc);
1155 return;
1156 }
1157
1158 dwc->ep0state = EP0_STATUS_PHASE;
1159
1160 if (dwc->delayed_status) {
1161 struct dwc3_ep *dep = dwc->eps[0];
1162
1163 WARN_ON_ONCE(event->endpoint_number != 1);
1164 /*
1165 * We should handle the delay STATUS phase here if the
1166 * request for handling delay STATUS has been queued
1167 * into the list.
1168 */
1169 if (!list_empty(head: &dep->pending_list)) {
1170 dwc->delayed_status = false;
1171 usb_gadget_set_state(gadget: dwc->gadget,
1172 state: USB_STATE_CONFIGURED);
1173 dwc3_ep0_do_control_status(dwc, event);
1174 }
1175
1176 return;
1177 }
1178
1179 dwc3_ep0_do_control_status(dwc, event);
1180 }
1181}
1182
1183void dwc3_ep0_interrupt(struct dwc3 *dwc,
1184 const struct dwc3_event_depevt *event)
1185{
1186 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
1187 u8 cmd;
1188
1189 switch (event->endpoint_event) {
1190 case DWC3_DEPEVT_XFERCOMPLETE:
1191 dwc3_ep0_xfer_complete(dwc, event);
1192 break;
1193
1194 case DWC3_DEPEVT_XFERNOTREADY:
1195 dwc3_ep0_xfernotready(dwc, event);
1196 break;
1197
1198 case DWC3_DEPEVT_XFERINPROGRESS:
1199 case DWC3_DEPEVT_RXTXFIFOEVT:
1200 case DWC3_DEPEVT_STREAMEVT:
1201 break;
1202 case DWC3_DEPEVT_EPCMDCMPLT:
1203 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
1204
1205 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
1206 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
1207 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
1208 }
1209 break;
1210 default:
1211 dev_err(dwc->dev, "unknown endpoint event %d\n", event->endpoint_event);
1212 break;
1213 }
1214}
1215

source code of linux/drivers/usb/dwc3/ep0.c