1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * xhci-dbc.h - xHCI debug capability early driver |
4 | * |
5 | * Copyright (C) 2016 Intel Corporation |
6 | * |
7 | * Author: Lu Baolu <baolu.lu@linux.intel.com> |
8 | */ |
9 | |
10 | #ifndef __LINUX_XHCI_DBC_H |
11 | #define __LINUX_XHCI_DBC_H |
12 | |
13 | #include <linux/types.h> |
14 | #include <linux/usb/ch9.h> |
15 | |
16 | /* |
17 | * xHCI Debug Capability Register interfaces: |
18 | */ |
19 | struct xdbc_regs { |
20 | __le32 capability; |
21 | __le32 doorbell; |
22 | __le32 ersts; /* Event Ring Segment Table Size*/ |
23 | __le32 __reserved_0; /* 0c~0f reserved bits */ |
24 | __le64 erstba; /* Event Ring Segment Table Base Address */ |
25 | __le64 erdp; /* Event Ring Dequeue Pointer */ |
26 | __le32 control; |
27 | __le32 status; |
28 | __le32 portsc; /* Port status and control */ |
29 | __le32 __reserved_1; /* 2b~28 reserved bits */ |
30 | __le64 dccp; /* Debug Capability Context Pointer */ |
31 | __le32 devinfo1; /* Device Descriptor Info Register 1 */ |
32 | __le32 devinfo2; /* Device Descriptor Info Register 2 */ |
33 | }; |
34 | |
35 | #define DEBUG_MAX_BURST(p) (((p) >> 16) & 0xff) |
36 | |
37 | #define CTRL_DBC_RUN BIT(0) |
38 | #define CTRL_PORT_ENABLE BIT(1) |
39 | #define CTRL_HALT_OUT_TR BIT(2) |
40 | #define CTRL_HALT_IN_TR BIT(3) |
41 | #define CTRL_DBC_RUN_CHANGE BIT(4) |
42 | #define CTRL_DBC_ENABLE BIT(31) |
43 | |
44 | #define DCST_DEBUG_PORT(p) (((p) >> 24) & 0xff) |
45 | |
46 | #define PORTSC_CONN_STATUS BIT(0) |
47 | #define PORTSC_CONN_CHANGE BIT(17) |
48 | #define PORTSC_RESET_CHANGE BIT(21) |
49 | #define PORTSC_LINK_CHANGE BIT(22) |
50 | #define PORTSC_CONFIG_CHANGE BIT(23) |
51 | |
52 | /* |
53 | * xHCI Debug Capability data structures: |
54 | */ |
55 | struct xdbc_trb { |
56 | __le32 field[4]; |
57 | }; |
58 | |
59 | struct xdbc_erst_entry { |
60 | __le64 seg_addr; |
61 | __le32 seg_size; |
62 | __le32 __reserved_0; |
63 | }; |
64 | |
65 | struct xdbc_info_context { |
66 | __le64 string0; |
67 | __le64 manufacturer; |
68 | __le64 product; |
69 | __le64 serial; |
70 | __le32 length; |
71 | __le32 __reserved_0[7]; |
72 | }; |
73 | |
74 | struct xdbc_ep_context { |
75 | __le32 ep_info1; |
76 | __le32 ep_info2; |
77 | __le64 deq; |
78 | __le32 tx_info; |
79 | __le32 __reserved_0[11]; |
80 | }; |
81 | |
82 | struct xdbc_context { |
83 | struct xdbc_info_context info; |
84 | struct xdbc_ep_context out; |
85 | struct xdbc_ep_context in; |
86 | }; |
87 | |
88 | #define XDBC_INFO_CONTEXT_SIZE 48 |
89 | #define XDBC_MAX_STRING_LENGTH 64 |
90 | #define XDBC_STRING_MANUFACTURER "Linux Foundation" |
91 | #define XDBC_STRING_PRODUCT "Linux USB GDB Target" |
92 | #define XDBC_STRING_SERIAL "0001" |
93 | |
94 | struct xdbc_strings { |
95 | char string0[XDBC_MAX_STRING_LENGTH]; |
96 | char manufacturer[XDBC_MAX_STRING_LENGTH]; |
97 | char product[XDBC_MAX_STRING_LENGTH]; |
98 | char serial[XDBC_MAX_STRING_LENGTH]; |
99 | }; |
100 | |
101 | #define XDBC_PROTOCOL 1 /* GNU Remote Debug Command Set */ |
102 | #define XDBC_VENDOR_ID 0x1d6b /* Linux Foundation 0x1d6b */ |
103 | #define XDBC_PRODUCT_ID 0x0011 /* __le16 idProduct; device 0011 */ |
104 | #define XDBC_DEVICE_REV 0x0010 /* 0.10 */ |
105 | |
106 | /* |
107 | * xHCI Debug Capability software state structures: |
108 | */ |
109 | struct xdbc_segment { |
110 | struct xdbc_trb *trbs; |
111 | dma_addr_t dma; |
112 | }; |
113 | |
114 | #define XDBC_TRBS_PER_SEGMENT 256 |
115 | |
116 | struct xdbc_ring { |
117 | struct xdbc_segment *segment; |
118 | struct xdbc_trb *enqueue; |
119 | struct xdbc_trb *dequeue; |
120 | u32 cycle_state; |
121 | }; |
122 | |
123 | /* |
124 | * These are the "Endpoint ID" (also known as "Context Index") values for the |
125 | * OUT Transfer Ring and the IN Transfer Ring of a Debug Capability Context data |
126 | * structure. |
127 | * According to the "eXtensible Host Controller Interface for Universal Serial |
128 | * Bus (xHCI)" specification, section "7.6.3.2 Endpoint Contexts and Transfer |
129 | * Rings", these should be 0 and 1, and those are the values AMD machines give |
130 | * you; but Intel machines seem to use the formula from section "4.5.1 Device |
131 | * Context Index", which is supposed to be used for the Device Context only. |
132 | * Luckily the values from Intel don't overlap with those from AMD, so we can |
133 | * just test for both. |
134 | */ |
135 | #define XDBC_EPID_OUT 0 |
136 | #define XDBC_EPID_IN 1 |
137 | #define XDBC_EPID_OUT_INTEL 2 |
138 | #define XDBC_EPID_IN_INTEL 3 |
139 | |
140 | struct xdbc_state { |
141 | u16 vendor; |
142 | u16 device; |
143 | u32 bus; |
144 | u32 dev; |
145 | u32 func; |
146 | void __iomem *xhci_base; |
147 | u64 xhci_start; |
148 | size_t xhci_length; |
149 | int port_number; |
150 | |
151 | /* DbC register base */ |
152 | struct xdbc_regs __iomem *xdbc_reg; |
153 | |
154 | /* DbC table page */ |
155 | dma_addr_t table_dma; |
156 | void *table_base; |
157 | |
158 | /* event ring segment table */ |
159 | dma_addr_t erst_dma; |
160 | size_t erst_size; |
161 | void *erst_base; |
162 | |
163 | /* event ring segments */ |
164 | struct xdbc_ring evt_ring; |
165 | struct xdbc_segment evt_seg; |
166 | |
167 | /* debug capability contexts */ |
168 | dma_addr_t dbcc_dma; |
169 | size_t dbcc_size; |
170 | void *dbcc_base; |
171 | |
172 | /* descriptor strings */ |
173 | dma_addr_t string_dma; |
174 | size_t string_size; |
175 | void *string_base; |
176 | |
177 | /* bulk OUT endpoint */ |
178 | struct xdbc_ring out_ring; |
179 | struct xdbc_segment out_seg; |
180 | void *out_buf; |
181 | dma_addr_t out_dma; |
182 | |
183 | /* bulk IN endpoint */ |
184 | struct xdbc_ring in_ring; |
185 | struct xdbc_segment in_seg; |
186 | void *in_buf; |
187 | dma_addr_t in_dma; |
188 | |
189 | u32 flags; |
190 | |
191 | /* spinlock for early_xdbc_write() reentrancy */ |
192 | raw_spinlock_t lock; |
193 | }; |
194 | |
195 | #define XDBC_PCI_MAX_BUSES 256 |
196 | #define XDBC_PCI_MAX_DEVICES 32 |
197 | #define XDBC_PCI_MAX_FUNCTION 8 |
198 | |
199 | #define XDBC_TABLE_ENTRY_SIZE 64 |
200 | #define XDBC_ERST_ENTRY_NUM 1 |
201 | #define XDBC_DBCC_ENTRY_NUM 3 |
202 | #define XDBC_STRING_ENTRY_NUM 4 |
203 | |
204 | /* Bits definitions for xdbc_state.flags: */ |
205 | #define XDBC_FLAGS_INITIALIZED BIT(0) |
206 | #define XDBC_FLAGS_IN_STALL BIT(1) |
207 | #define XDBC_FLAGS_OUT_STALL BIT(2) |
208 | #define XDBC_FLAGS_IN_PROCESS BIT(3) |
209 | #define XDBC_FLAGS_OUT_PROCESS BIT(4) |
210 | #define XDBC_FLAGS_CONFIGURED BIT(5) |
211 | |
212 | #define XDBC_MAX_PACKET 1024 |
213 | |
214 | /* Door bell target: */ |
215 | #define OUT_EP_DOORBELL 0 |
216 | #define IN_EP_DOORBELL 1 |
217 | #define DOOR_BELL_TARGET(p) (((p) & 0xff) << 8) |
218 | |
219 | #define xdbc_read64(regs) xhci_read_64(NULL, (regs)) |
220 | #define xdbc_write64(val, regs) xhci_write_64(NULL, (val), (regs)) |
221 | |
222 | #endif /* __LINUX_XHCI_DBC_H */ |
223 | |