| 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
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| 2 | /* Copyright (C) 2005-2010,2012 Freescale Semiconductor, Inc. |
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| 3 | * Copyright (c) 2005 MontaVista Software |
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| 4 | */ |
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| 5 | #ifndef _EHCI_FSL_H |
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| 6 | #define _EHCI_FSL_H |
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| 7 | |
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| 8 | /* offsets for the non-ehci registers in the FSL SOC USB controller */ |
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| 9 | #define FSL_SOC_USB_SBUSCFG 0x90 |
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| 10 | #define SBUSCFG_INCR8 0x02 /* INCR8, specified */ |
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| 11 | #define FSL_SOC_USB_ULPIVP 0x170 |
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| 12 | #define FSL_SOC_USB_PORTSC1 0x184 |
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| 13 | #define PORT_PTS_MSK (3<<30) |
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| 14 | #define PORT_PTS_UTMI (0<<30) |
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| 15 | #define PORT_PTS_ULPI (2<<30) |
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| 16 | #define PORT_PTS_SERIAL (3<<30) |
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| 17 | #define PORT_PTS_PTW (1<<28) |
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| 18 | #define FSL_SOC_USB_PORTSC2 0x188 |
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| 19 | #define FSL_SOC_USB_USBMODE 0x1a8 |
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| 20 | #define USBMODE_CM_MASK (3 << 0) /* controller mode mask */ |
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| 21 | #define USBMODE_CM_HOST (3 << 0) /* controller mode: host */ |
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| 22 | #define USBMODE_ES (1 << 2) /* (Big) Endian Select */ |
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| 23 | |
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| 24 | #define FSL_SOC_USB_USBGENCTRL 0x200 |
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| 25 | #define USBGENCTRL_PPP (1 << 3) |
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| 26 | #define USBGENCTRL_PFP (1 << 2) |
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| 27 | #define FSL_SOC_USB_ISIPHYCTRL 0x204 |
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| 28 | #define ISIPHYCTRL_PXE (1) |
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| 29 | #define ISIPHYCTRL_PHYE (1 << 4) |
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| 30 | |
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| 31 | #define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */ |
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| 32 | #define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */ |
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| 33 | #define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */ |
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| 34 | #define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */ |
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| 35 | #define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */ |
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| 36 | #define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */ |
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| 37 | #define CTRL_UTMI_PHY_EN (1<<9) |
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| 38 | #define CTRL_PHY_CLK_VALID (1 << 17) |
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| 39 | #define SNOOP_SIZE_2GB 0x1e |
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| 40 | |
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| 41 | /* control Register Bit Masks */ |
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| 42 | #define CONTROL_REGISTER_W1C_MASK 0x00020000 /* W1C: PHY_CLK_VALID */ |
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| 43 | #define ULPI_INT_EN (1<<0) |
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| 44 | #define WU_INT_EN (1<<1) |
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| 45 | #define USB_CTRL_USB_EN (1<<2) |
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| 46 | #define LINE_STATE_FILTER__EN (1<<3) |
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| 47 | #define KEEP_OTG_ON (1<<4) |
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| 48 | #define OTG_PORT (1<<5) |
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| 49 | #define PLL_RESET (1<<8) |
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| 50 | #define UTMI_PHY_EN (1<<9) |
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| 51 | #define ULPI_PHY_CLK_SEL (1<<10) |
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| 52 | #define PHY_CLK_VALID (1<<17) |
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| 53 | |
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| 54 | /* Retry count for checking UTMI PHY CLK validity */ |
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| 55 | #define UTMI_PHY_CLK_VALID_CHK_RETRY 5 |
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| 56 | #endif /* _EHCI_FSL_H */ |
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| 57 | |
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