1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author:
5 * Zhigang.Wei <zhigang.wei@mediatek.com>
6 * Chunfeng.Yun <chunfeng.yun@mediatek.com>
7 */
8
9#ifndef _XHCI_MTK_H_
10#define _XHCI_MTK_H_
11
12#include <linux/clk.h>
13#include <linux/hashtable.h>
14#include <linux/regulator/consumer.h>
15
16#include "xhci.h"
17
18#define BULK_CLKS_NUM 6
19#define BULK_VREGS_NUM 2
20
21/* support at most 64 ep, use 32 size hash table */
22#define SCH_EP_HASH_BITS 5
23
24/**
25 * To simplify scheduler algorithm, set a upper limit for ESIT,
26 * if a synchromous ep's ESIT is larger than @XHCI_MTK_MAX_ESIT,
27 * round down to the limit value, that means allocating more
28 * bandwidth to it.
29 */
30#define XHCI_MTK_MAX_ESIT (1 << 6)
31#define XHCI_MTK_BW_INDEX(x) ((x) & (XHCI_MTK_MAX_ESIT - 1))
32
33#define UFRAMES_PER_FRAME 8
34#define XHCI_MTK_FRAMES_CNT (XHCI_MTK_MAX_ESIT / UFRAMES_PER_FRAME)
35
36/**
37 * @fs_bus_bw_out: save bandwidth used by FS/LS OUT eps in each uframes
38 * @fs_bus_bw_in: save bandwidth used by FS/LS IN eps in each uframes
39 * @ls_bus_bw: save bandwidth used by LS eps in each uframes
40 * @fs_frame_bw: save bandwidth used by FS/LS eps in each FS frames
41 * @ep_list: Endpoints using this TT
42 */
43struct mu3h_sch_tt {
44 u16 fs_bus_bw_out[XHCI_MTK_MAX_ESIT];
45 u16 fs_bus_bw_in[XHCI_MTK_MAX_ESIT];
46 u8 ls_bus_bw[XHCI_MTK_MAX_ESIT];
47 u16 fs_frame_bw[XHCI_MTK_FRAMES_CNT];
48 struct list_head ep_list;
49};
50
51/**
52 * struct mu3h_sch_bw_info: schedule information for bandwidth domain
53 *
54 * @bus_bw: array to keep track of bandwidth already used at each uframes
55 *
56 * treat a HS root port as a bandwidth domain, but treat a SS root port as
57 * two bandwidth domains, one for IN eps and another for OUT eps.
58 */
59struct mu3h_sch_bw_info {
60 u32 bus_bw[XHCI_MTK_MAX_ESIT];
61};
62
63/**
64 * struct mu3h_sch_ep_info: schedule information for endpoint
65 *
66 * @esit: unit is 125us, equal to 2 << Interval field in ep-context
67 * @num_esit: number of @esit in a period
68 * @num_budget_microframes: number of continuous uframes
69 * (@repeat==1) scheduled within the interval
70 * @hentry: hash table entry
71 * @endpoint: linked into bandwidth domain which it belongs to
72 * @tt_endpoint: linked into mu3h_sch_tt's list which it belongs to
73 * @bw_info: bandwidth domain which this endpoint belongs
74 * @sch_tt: mu3h_sch_tt linked into
75 * @ep_type: endpoint type
76 * @maxpkt: max packet size of endpoint
77 * @ep: address of usb_host_endpoint struct
78 * @allocated: the bandwidth is aready allocated from bus_bw
79 * @offset: which uframe of the interval that transfer should be
80 * scheduled first time within the interval
81 * @repeat: the time gap between two uframes that transfers are
82 * scheduled within a interval. in the simple algorithm, only
83 * assign 0 or 1 to it; 0 means using only one uframe in a
84 * interval, and 1 means using @num_budget_microframes
85 * continuous uframes
86 * @pkts: number of packets to be transferred in the scheduled uframes
87 * @cs_count: number of CS that host will trigger
88 * @burst_mode: burst mode for scheduling. 0: normal burst mode,
89 * distribute the bMaxBurst+1 packets for a single burst
90 * according to @pkts and @repeat, repeate the burst multiple
91 * times; 1: distribute the (bMaxBurst+1)*(Mult+1) packets
92 * according to @pkts and @repeat. normal mode is used by
93 * default
94 * @bw_budget_table: table to record bandwidth budget per microframe
95 */
96struct mu3h_sch_ep_info {
97 u32 esit;
98 u32 num_esit;
99 u32 num_budget_microframes;
100 struct list_head endpoint;
101 struct hlist_node hentry;
102 struct list_head tt_endpoint;
103 struct mu3h_sch_bw_info *bw_info;
104 struct mu3h_sch_tt *sch_tt;
105 u32 ep_type;
106 u32 maxpkt;
107 struct usb_host_endpoint *ep;
108 enum usb_device_speed speed;
109 bool allocated;
110 /*
111 * mtk xHCI scheduling information put into reserved DWs
112 * in ep context
113 */
114 u32 offset;
115 u32 repeat;
116 u32 pkts;
117 u32 cs_count;
118 u32 burst_mode;
119 u32 bw_budget_table[];
120};
121
122#define MU3C_U3_PORT_MAX 4
123#define MU3C_U2_PORT_MAX 5
124
125/**
126 * struct mu3c_ippc_regs: MTK ssusb ip port control registers
127 * @ip_pw_ctr0~3: ip power and clock control registers
128 * @ip_pw_sts1~2: ip power and clock status registers
129 * @ip_xhci_cap: ip xHCI capability register
130 * @u3_ctrl_p[x]: ip usb3 port x control register, only low 4bytes are used
131 * @u2_ctrl_p[x]: ip usb2 port x control register, only low 4bytes are used
132 * @u2_phy_pll: usb2 phy pll control register
133 */
134struct mu3c_ippc_regs {
135 __le32 ip_pw_ctr0;
136 __le32 ip_pw_ctr1;
137 __le32 ip_pw_ctr2;
138 __le32 ip_pw_ctr3;
139 __le32 ip_pw_sts1;
140 __le32 ip_pw_sts2;
141 __le32 reserved0[3];
142 __le32 ip_xhci_cap;
143 __le32 reserved1[2];
144 __le64 u3_ctrl_p[MU3C_U3_PORT_MAX];
145 __le64 u2_ctrl_p[MU3C_U2_PORT_MAX];
146 __le32 reserved2;
147 __le32 u2_phy_pll;
148 __le32 reserved3[33]; /* 0x80 ~ 0xff */
149};
150
151struct xhci_hcd_mtk {
152 struct device *dev;
153 struct usb_hcd *hcd;
154 struct mu3h_sch_bw_info *sch_array;
155 struct list_head bw_ep_chk_list;
156 DECLARE_HASHTABLE(sch_ep_hash, SCH_EP_HASH_BITS);
157 struct mu3c_ippc_regs __iomem *ippc_regs;
158 int num_u2_ports;
159 int num_u3_ports;
160 int u2p_dis_msk;
161 int u3p_dis_msk;
162 struct clk_bulk_data clks[BULK_CLKS_NUM];
163 struct regulator_bulk_data supplies[BULK_VREGS_NUM];
164 unsigned int has_ippc:1;
165 unsigned int lpm_support:1;
166 unsigned int u2_lpm_disable:1;
167 /* usb remote wakeup */
168 unsigned int uwk_en:1;
169 struct regmap *uwk;
170 u32 uwk_reg_base;
171 u32 uwk_vers;
172};
173
174static inline struct xhci_hcd_mtk *hcd_to_mtk(struct usb_hcd *hcd)
175{
176 return dev_get_drvdata(dev: hcd->self.controller);
177}
178
179int xhci_mtk_sch_init(struct xhci_hcd_mtk *mtk);
180void xhci_mtk_sch_exit(struct xhci_hcd_mtk *mtk);
181int xhci_mtk_add_ep(struct usb_hcd *hcd, struct usb_device *udev,
182 struct usb_host_endpoint *ep);
183int xhci_mtk_drop_ep(struct usb_hcd *hcd, struct usb_device *udev,
184 struct usb_host_endpoint *ep);
185int xhci_mtk_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
186void xhci_mtk_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
187
188#endif /* _XHCI_MTK_H_ */
189

source code of linux/drivers/usb/host/xhci-mtk.h