1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * NVIDIA Tegra xHCI host controller driver |
4 | * |
5 | * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. |
6 | * Copyright (C) 2014 Google, Inc. |
7 | */ |
8 | |
9 | #include <linux/clk.h> |
10 | #include <linux/delay.h> |
11 | #include <linux/dma-mapping.h> |
12 | #include <linux/firmware.h> |
13 | #include <linux/interrupt.h> |
14 | #include <linux/iopoll.h> |
15 | #include <linux/kernel.h> |
16 | #include <linux/module.h> |
17 | #include <linux/of.h> |
18 | #include <linux/of_irq.h> |
19 | #include <linux/phy/phy.h> |
20 | #include <linux/phy/tegra/xusb.h> |
21 | #include <linux/platform_device.h> |
22 | #include <linux/usb/ch9.h> |
23 | #include <linux/pm.h> |
24 | #include <linux/pm_domain.h> |
25 | #include <linux/pm_runtime.h> |
26 | #include <linux/regulator/consumer.h> |
27 | #include <linux/reset.h> |
28 | #include <linux/slab.h> |
29 | #include <linux/usb/otg.h> |
30 | #include <linux/usb/phy.h> |
31 | #include <linux/usb/role.h> |
32 | #include <soc/tegra/pmc.h> |
33 | |
34 | #include "xhci.h" |
35 | |
36 | #define TEGRA_XHCI_SS_HIGH_SPEED 120000000 |
37 | #define TEGRA_XHCI_SS_LOW_SPEED 12000000 |
38 | |
39 | /* FPCI CFG registers */ |
40 | #define XUSB_CFG_1 0x004 |
41 | #define XUSB_IO_SPACE_EN BIT(0) |
42 | #define XUSB_MEM_SPACE_EN BIT(1) |
43 | #define XUSB_BUS_MASTER_EN BIT(2) |
44 | #define XUSB_CFG_4 0x010 |
45 | #define XUSB_BASE_ADDR_SHIFT 15 |
46 | #define XUSB_BASE_ADDR_MASK 0x1ffff |
47 | #define XUSB_CFG_7 0x01c |
48 | #define XUSB_BASE2_ADDR_SHIFT 16 |
49 | #define XUSB_BASE2_ADDR_MASK 0xffff |
50 | #define XUSB_CFG_16 0x040 |
51 | #define XUSB_CFG_24 0x060 |
52 | #define XUSB_CFG_AXI_CFG 0x0f8 |
53 | #define XUSB_CFG_ARU_C11_CSBRANGE 0x41c |
54 | #define XUSB_CFG_ARU_CONTEXT 0x43c |
55 | #define XUSB_CFG_ARU_CONTEXT_HS_PLS 0x478 |
56 | #define XUSB_CFG_ARU_CONTEXT_FS_PLS 0x47c |
57 | #define XUSB_CFG_ARU_CONTEXT_HSFS_SPEED 0x480 |
58 | #define XUSB_CFG_ARU_CONTEXT_HSFS_PP 0x484 |
59 | #define XUSB_CFG_CSB_BASE_ADDR 0x800 |
60 | |
61 | /* FPCI mailbox registers */ |
62 | /* XUSB_CFG_ARU_MBOX_CMD */ |
63 | #define MBOX_DEST_FALC BIT(27) |
64 | #define MBOX_DEST_PME BIT(28) |
65 | #define MBOX_DEST_SMI BIT(29) |
66 | #define MBOX_DEST_XHCI BIT(30) |
67 | #define MBOX_INT_EN BIT(31) |
68 | /* XUSB_CFG_ARU_MBOX_DATA_IN and XUSB_CFG_ARU_MBOX_DATA_OUT */ |
69 | #define CMD_DATA_SHIFT 0 |
70 | #define CMD_DATA_MASK 0xffffff |
71 | #define CMD_TYPE_SHIFT 24 |
72 | #define CMD_TYPE_MASK 0xff |
73 | /* XUSB_CFG_ARU_MBOX_OWNER */ |
74 | #define MBOX_OWNER_NONE 0 |
75 | #define MBOX_OWNER_FW 1 |
76 | #define MBOX_OWNER_SW 2 |
77 | #define XUSB_CFG_ARU_SMI_INTR 0x428 |
78 | #define MBOX_SMI_INTR_FW_HANG BIT(1) |
79 | #define MBOX_SMI_INTR_EN BIT(3) |
80 | |
81 | /* BAR2 registers */ |
82 | #define XUSB_BAR2_ARU_MBOX_CMD 0x004 |
83 | #define XUSB_BAR2_ARU_MBOX_DATA_IN 0x008 |
84 | #define XUSB_BAR2_ARU_MBOX_DATA_OUT 0x00c |
85 | #define XUSB_BAR2_ARU_MBOX_OWNER 0x010 |
86 | #define XUSB_BAR2_ARU_SMI_INTR 0x014 |
87 | #define XUSB_BAR2_ARU_SMI_ARU_FW_SCRATCH_DATA0 0x01c |
88 | #define XUSB_BAR2_ARU_IFRDMA_CFG0 0x0e0 |
89 | #define XUSB_BAR2_ARU_IFRDMA_CFG1 0x0e4 |
90 | #define XUSB_BAR2_ARU_IFRDMA_STREAMID_FIELD 0x0e8 |
91 | #define XUSB_BAR2_ARU_C11_CSBRANGE 0x9c |
92 | #define XUSB_BAR2_ARU_FW_SCRATCH 0x1000 |
93 | #define XUSB_BAR2_CSB_BASE_ADDR 0x2000 |
94 | |
95 | /* IPFS registers */ |
96 | #define IPFS_XUSB_HOST_MSI_BAR_SZ_0 0x0c0 |
97 | #define IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0 0x0c4 |
98 | #define IPFS_XUSB_HOST_MSI_FPCI_BAR_ST_0 0x0c8 |
99 | #define IPFS_XUSB_HOST_MSI_VEC0_0 0x100 |
100 | #define IPFS_XUSB_HOST_MSI_EN_VEC0_0 0x140 |
101 | #define IPFS_XUSB_HOST_CONFIGURATION_0 0x180 |
102 | #define IPFS_EN_FPCI BIT(0) |
103 | #define IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0 0x184 |
104 | #define IPFS_XUSB_HOST_INTR_MASK_0 0x188 |
105 | #define IPFS_IP_INT_MASK BIT(16) |
106 | #define IPFS_XUSB_HOST_INTR_ENABLE_0 0x198 |
107 | #define IPFS_XUSB_HOST_UFPCI_CONFIG_0 0x19c |
108 | #define IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0 0x1bc |
109 | #define IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0 0x1dc |
110 | |
111 | #define CSB_PAGE_SELECT_MASK 0x7fffff |
112 | #define CSB_PAGE_SELECT_SHIFT 9 |
113 | #define CSB_PAGE_OFFSET_MASK 0x1ff |
114 | #define CSB_PAGE_SELECT(addr) ((addr) >> (CSB_PAGE_SELECT_SHIFT) & \ |
115 | CSB_PAGE_SELECT_MASK) |
116 | #define CSB_PAGE_OFFSET(addr) ((addr) & CSB_PAGE_OFFSET_MASK) |
117 | |
118 | /* Falcon CSB registers */ |
119 | #define XUSB_FALC_CPUCTL 0x100 |
120 | #define CPUCTL_STARTCPU BIT(1) |
121 | #define CPUCTL_STATE_HALTED BIT(4) |
122 | #define CPUCTL_STATE_STOPPED BIT(5) |
123 | #define XUSB_FALC_BOOTVEC 0x104 |
124 | #define XUSB_FALC_DMACTL 0x10c |
125 | #define XUSB_FALC_IMFILLRNG1 0x154 |
126 | #define IMFILLRNG1_TAG_MASK 0xffff |
127 | #define IMFILLRNG1_TAG_LO_SHIFT 0 |
128 | #define IMFILLRNG1_TAG_HI_SHIFT 16 |
129 | #define XUSB_FALC_IMFILLCTL 0x158 |
130 | |
131 | /* CSB ARU registers */ |
132 | #define XUSB_CSB_ARU_SCRATCH0 0x100100 |
133 | |
134 | /* MP CSB registers */ |
135 | #define XUSB_CSB_MP_ILOAD_ATTR 0x101a00 |
136 | #define XUSB_CSB_MP_ILOAD_BASE_LO 0x101a04 |
137 | #define XUSB_CSB_MP_ILOAD_BASE_HI 0x101a08 |
138 | #define XUSB_CSB_MP_L2IMEMOP_SIZE 0x101a10 |
139 | #define L2IMEMOP_SIZE_SRC_OFFSET_SHIFT 8 |
140 | #define L2IMEMOP_SIZE_SRC_OFFSET_MASK 0x3ff |
141 | #define L2IMEMOP_SIZE_SRC_COUNT_SHIFT 24 |
142 | #define L2IMEMOP_SIZE_SRC_COUNT_MASK 0xff |
143 | #define XUSB_CSB_MP_L2IMEMOP_TRIG 0x101a14 |
144 | #define L2IMEMOP_ACTION_SHIFT 24 |
145 | #define L2IMEMOP_INVALIDATE_ALL (0x40 << L2IMEMOP_ACTION_SHIFT) |
146 | #define L2IMEMOP_LOAD_LOCKED_RESULT (0x11 << L2IMEMOP_ACTION_SHIFT) |
147 | #define XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT 0x101a18 |
148 | #define L2IMEMOP_RESULT_VLD BIT(31) |
149 | #define XUSB_CSB_MP_APMAP 0x10181c |
150 | #define APMAP_BOOTPATH BIT(31) |
151 | |
152 | #define IMEM_BLOCK_SIZE 256 |
153 | |
154 | #define FW_IOCTL_TYPE_SHIFT 24 |
155 | #define FW_IOCTL_CFGTBL_READ 17 |
156 | |
157 | struct { |
158 | __le32 ; |
159 | __le32 ; |
160 | __le32 ; |
161 | __le32 ; |
162 | __le32 ; |
163 | __le16 ; |
164 | __le16 ; |
165 | __le32 ; |
166 | __le32 ; |
167 | __le32 ; |
168 | __le32 main_fnaddr; |
169 | __le32 ; |
170 | __le32 ; |
171 | __le32 ; |
172 | __le32 ; |
173 | __le32 ; |
174 | __le32 ; |
175 | __le32 ; |
176 | __le32 ; |
177 | __le32 ; |
178 | u8 ; |
179 | u8 [3]; |
180 | __le32 ; |
181 | __le32 ; |
182 | __le32 ; |
183 | __le32 [2]; |
184 | __le32 ; |
185 | u8 [8]; |
186 | __le32 ; |
187 | u8 ; |
188 | u8 [139]; /* Pad to 256 bytes */ |
189 | }; |
190 | |
191 | struct tegra_xusb_phy_type { |
192 | const char *name; |
193 | unsigned int num; |
194 | }; |
195 | |
196 | struct tegra_xusb_mbox_regs { |
197 | u16 cmd; |
198 | u16 data_in; |
199 | u16 data_out; |
200 | u16 owner; |
201 | u16 smi_intr; |
202 | }; |
203 | |
204 | struct tegra_xusb_context_soc { |
205 | struct { |
206 | const unsigned int *offsets; |
207 | unsigned int num_offsets; |
208 | } ipfs; |
209 | |
210 | struct { |
211 | const unsigned int *offsets; |
212 | unsigned int num_offsets; |
213 | } fpci; |
214 | }; |
215 | |
216 | struct tegra_xusb; |
217 | struct tegra_xusb_soc_ops { |
218 | u32 (*mbox_reg_readl)(struct tegra_xusb *tegra, unsigned int offset); |
219 | void (*mbox_reg_writel)(struct tegra_xusb *tegra, u32 value, unsigned int offset); |
220 | u32 (*csb_reg_readl)(struct tegra_xusb *tegra, unsigned int offset); |
221 | void (*csb_reg_writel)(struct tegra_xusb *tegra, u32 value, unsigned int offset); |
222 | }; |
223 | |
224 | struct tegra_xusb_soc { |
225 | const char *firmware; |
226 | const char * const *supply_names; |
227 | unsigned int num_supplies; |
228 | const struct tegra_xusb_phy_type *phy_types; |
229 | unsigned int num_types; |
230 | const struct tegra_xusb_context_soc *context; |
231 | |
232 | struct { |
233 | struct { |
234 | unsigned int offset; |
235 | unsigned int count; |
236 | } usb2, ulpi, hsic, usb3; |
237 | } ports; |
238 | |
239 | struct tegra_xusb_mbox_regs mbox; |
240 | const struct tegra_xusb_soc_ops *ops; |
241 | |
242 | bool scale_ss_clock; |
243 | bool has_ipfs; |
244 | bool lpm_support; |
245 | bool otg_reset_sspi; |
246 | |
247 | bool has_bar2; |
248 | }; |
249 | |
250 | struct tegra_xusb_context { |
251 | u32 *ipfs; |
252 | u32 *fpci; |
253 | }; |
254 | |
255 | struct tegra_xusb { |
256 | struct device *dev; |
257 | void __iomem *regs; |
258 | struct usb_hcd *hcd; |
259 | |
260 | struct mutex lock; |
261 | |
262 | int xhci_irq; |
263 | int mbox_irq; |
264 | int padctl_irq; |
265 | |
266 | void __iomem *ipfs_base; |
267 | void __iomem *fpci_base; |
268 | void __iomem *bar2_base; |
269 | struct resource *bar2; |
270 | |
271 | const struct tegra_xusb_soc *soc; |
272 | |
273 | struct regulator_bulk_data *supplies; |
274 | |
275 | struct tegra_xusb_padctl *padctl; |
276 | |
277 | struct clk *host_clk; |
278 | struct clk *falcon_clk; |
279 | struct clk *ss_clk; |
280 | struct clk *ss_src_clk; |
281 | struct clk *hs_src_clk; |
282 | struct clk *fs_src_clk; |
283 | struct clk *pll_u_480m; |
284 | struct clk *clk_m; |
285 | struct clk *pll_e; |
286 | |
287 | struct reset_control *host_rst; |
288 | struct reset_control *ss_rst; |
289 | |
290 | struct device *genpd_dev_host; |
291 | struct device *genpd_dev_ss; |
292 | bool use_genpd; |
293 | |
294 | struct phy **phys; |
295 | unsigned int num_phys; |
296 | |
297 | struct usb_phy **usbphy; |
298 | unsigned int num_usb_phys; |
299 | int otg_usb2_port; |
300 | int otg_usb3_port; |
301 | bool host_mode; |
302 | struct notifier_block id_nb; |
303 | struct work_struct id_work; |
304 | |
305 | /* Firmware loading related */ |
306 | struct { |
307 | size_t size; |
308 | void *virt; |
309 | dma_addr_t phys; |
310 | } fw; |
311 | |
312 | bool suspended; |
313 | struct tegra_xusb_context context; |
314 | u8 lp0_utmi_pad_mask; |
315 | }; |
316 | |
317 | static struct hc_driver __read_mostly tegra_xhci_hc_driver; |
318 | |
319 | static inline u32 fpci_readl(struct tegra_xusb *tegra, unsigned int offset) |
320 | { |
321 | return readl(addr: tegra->fpci_base + offset); |
322 | } |
323 | |
324 | static inline void fpci_writel(struct tegra_xusb *tegra, u32 value, |
325 | unsigned int offset) |
326 | { |
327 | writel(val: value, addr: tegra->fpci_base + offset); |
328 | } |
329 | |
330 | static inline u32 ipfs_readl(struct tegra_xusb *tegra, unsigned int offset) |
331 | { |
332 | return readl(addr: tegra->ipfs_base + offset); |
333 | } |
334 | |
335 | static inline void ipfs_writel(struct tegra_xusb *tegra, u32 value, |
336 | unsigned int offset) |
337 | { |
338 | writel(val: value, addr: tegra->ipfs_base + offset); |
339 | } |
340 | |
341 | static inline u32 bar2_readl(struct tegra_xusb *tegra, unsigned int offset) |
342 | { |
343 | return readl(addr: tegra->bar2_base + offset); |
344 | } |
345 | |
346 | static inline void bar2_writel(struct tegra_xusb *tegra, u32 value, |
347 | unsigned int offset) |
348 | { |
349 | writel(val: value, addr: tegra->bar2_base + offset); |
350 | } |
351 | |
352 | static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset) |
353 | { |
354 | const struct tegra_xusb_soc_ops *ops = tegra->soc->ops; |
355 | |
356 | return ops->csb_reg_readl(tegra, offset); |
357 | } |
358 | |
359 | static void csb_writel(struct tegra_xusb *tegra, u32 value, |
360 | unsigned int offset) |
361 | { |
362 | const struct tegra_xusb_soc_ops *ops = tegra->soc->ops; |
363 | |
364 | ops->csb_reg_writel(tegra, value, offset); |
365 | } |
366 | |
367 | static u32 fpci_csb_readl(struct tegra_xusb *tegra, unsigned int offset) |
368 | { |
369 | u32 page = CSB_PAGE_SELECT(offset); |
370 | u32 ofs = CSB_PAGE_OFFSET(offset); |
371 | |
372 | fpci_writel(tegra, value: page, XUSB_CFG_ARU_C11_CSBRANGE); |
373 | |
374 | return fpci_readl(tegra, XUSB_CFG_CSB_BASE_ADDR + ofs); |
375 | } |
376 | |
377 | static void fpci_csb_writel(struct tegra_xusb *tegra, u32 value, |
378 | unsigned int offset) |
379 | { |
380 | u32 page = CSB_PAGE_SELECT(offset); |
381 | u32 ofs = CSB_PAGE_OFFSET(offset); |
382 | |
383 | fpci_writel(tegra, value: page, XUSB_CFG_ARU_C11_CSBRANGE); |
384 | fpci_writel(tegra, value, XUSB_CFG_CSB_BASE_ADDR + ofs); |
385 | } |
386 | |
387 | static u32 bar2_csb_readl(struct tegra_xusb *tegra, unsigned int offset) |
388 | { |
389 | u32 page = CSB_PAGE_SELECT(offset); |
390 | u32 ofs = CSB_PAGE_OFFSET(offset); |
391 | |
392 | bar2_writel(tegra, value: page, XUSB_BAR2_ARU_C11_CSBRANGE); |
393 | |
394 | return bar2_readl(tegra, XUSB_BAR2_CSB_BASE_ADDR + ofs); |
395 | } |
396 | |
397 | static void bar2_csb_writel(struct tegra_xusb *tegra, u32 value, |
398 | unsigned int offset) |
399 | { |
400 | u32 page = CSB_PAGE_SELECT(offset); |
401 | u32 ofs = CSB_PAGE_OFFSET(offset); |
402 | |
403 | bar2_writel(tegra, value: page, XUSB_BAR2_ARU_C11_CSBRANGE); |
404 | bar2_writel(tegra, value, XUSB_BAR2_CSB_BASE_ADDR + ofs); |
405 | } |
406 | |
407 | static int tegra_xusb_set_ss_clk(struct tegra_xusb *tegra, |
408 | unsigned long rate) |
409 | { |
410 | unsigned long new_parent_rate, old_parent_rate; |
411 | struct clk *clk = tegra->ss_src_clk; |
412 | unsigned int div; |
413 | int err; |
414 | |
415 | if (clk_get_rate(clk) == rate) |
416 | return 0; |
417 | |
418 | switch (rate) { |
419 | case TEGRA_XHCI_SS_HIGH_SPEED: |
420 | /* |
421 | * Reparent to PLLU_480M. Set divider first to avoid |
422 | * overclocking. |
423 | */ |
424 | old_parent_rate = clk_get_rate(clk: clk_get_parent(clk)); |
425 | new_parent_rate = clk_get_rate(clk: tegra->pll_u_480m); |
426 | div = new_parent_rate / rate; |
427 | |
428 | err = clk_set_rate(clk, rate: old_parent_rate / div); |
429 | if (err) |
430 | return err; |
431 | |
432 | err = clk_set_parent(clk, parent: tegra->pll_u_480m); |
433 | if (err) |
434 | return err; |
435 | |
436 | /* |
437 | * The rate should already be correct, but set it again just |
438 | * to be sure. |
439 | */ |
440 | err = clk_set_rate(clk, rate); |
441 | if (err) |
442 | return err; |
443 | |
444 | break; |
445 | |
446 | case TEGRA_XHCI_SS_LOW_SPEED: |
447 | /* Reparent to CLK_M */ |
448 | err = clk_set_parent(clk, parent: tegra->clk_m); |
449 | if (err) |
450 | return err; |
451 | |
452 | err = clk_set_rate(clk, rate); |
453 | if (err) |
454 | return err; |
455 | |
456 | break; |
457 | |
458 | default: |
459 | dev_err(tegra->dev, "Invalid SS rate: %lu Hz\n" , rate); |
460 | return -EINVAL; |
461 | } |
462 | |
463 | if (clk_get_rate(clk) != rate) { |
464 | dev_err(tegra->dev, "SS clock doesn't match requested rate\n" ); |
465 | return -EINVAL; |
466 | } |
467 | |
468 | return 0; |
469 | } |
470 | |
471 | static unsigned long (u32 value, unsigned int start, |
472 | unsigned int count) |
473 | { |
474 | return (value >> start) & ((1 << count) - 1); |
475 | } |
476 | |
477 | /* Command requests from the firmware */ |
478 | enum tegra_xusb_mbox_cmd { |
479 | MBOX_CMD_MSG_ENABLED = 1, |
480 | MBOX_CMD_INC_FALC_CLOCK, |
481 | MBOX_CMD_DEC_FALC_CLOCK, |
482 | MBOX_CMD_INC_SSPI_CLOCK, |
483 | MBOX_CMD_DEC_SSPI_CLOCK, |
484 | MBOX_CMD_SET_BW, /* no ACK/NAK required */ |
485 | MBOX_CMD_SET_SS_PWR_GATING, |
486 | MBOX_CMD_SET_SS_PWR_UNGATING, |
487 | MBOX_CMD_SAVE_DFE_CTLE_CTX, |
488 | MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */ |
489 | MBOX_CMD_AIRPLANE_MODE_DISABLED, /* unused */ |
490 | MBOX_CMD_START_HSIC_IDLE, |
491 | MBOX_CMD_STOP_HSIC_IDLE, |
492 | MBOX_CMD_DBC_WAKE_STACK, /* unused */ |
493 | MBOX_CMD_HSIC_PRETEND_CONNECT, |
494 | MBOX_CMD_RESET_SSPI, |
495 | MBOX_CMD_DISABLE_SS_LFPS_DETECTION, |
496 | MBOX_CMD_ENABLE_SS_LFPS_DETECTION, |
497 | |
498 | MBOX_CMD_MAX, |
499 | |
500 | /* Response message to above commands */ |
501 | MBOX_CMD_ACK = 128, |
502 | MBOX_CMD_NAK |
503 | }; |
504 | |
505 | struct tegra_xusb_mbox_msg { |
506 | u32 cmd; |
507 | u32 data; |
508 | }; |
509 | |
510 | static inline u32 tegra_xusb_mbox_pack(const struct tegra_xusb_mbox_msg *msg) |
511 | { |
512 | return (msg->cmd & CMD_TYPE_MASK) << CMD_TYPE_SHIFT | |
513 | (msg->data & CMD_DATA_MASK) << CMD_DATA_SHIFT; |
514 | } |
515 | static inline void tegra_xusb_mbox_unpack(struct tegra_xusb_mbox_msg *msg, |
516 | u32 value) |
517 | { |
518 | msg->cmd = (value >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK; |
519 | msg->data = (value >> CMD_DATA_SHIFT) & CMD_DATA_MASK; |
520 | } |
521 | |
522 | static bool tegra_xusb_mbox_cmd_requires_ack(enum tegra_xusb_mbox_cmd cmd) |
523 | { |
524 | switch (cmd) { |
525 | case MBOX_CMD_SET_BW: |
526 | case MBOX_CMD_ACK: |
527 | case MBOX_CMD_NAK: |
528 | return false; |
529 | |
530 | default: |
531 | return true; |
532 | } |
533 | } |
534 | |
535 | static int tegra_xusb_mbox_send(struct tegra_xusb *tegra, |
536 | const struct tegra_xusb_mbox_msg *msg) |
537 | { |
538 | const struct tegra_xusb_soc_ops *ops = tegra->soc->ops; |
539 | bool wait_for_idle = false; |
540 | u32 value; |
541 | |
542 | /* |
543 | * Acquire the mailbox. The firmware still owns the mailbox for |
544 | * ACK/NAK messages. |
545 | */ |
546 | if (!(msg->cmd == MBOX_CMD_ACK || msg->cmd == MBOX_CMD_NAK)) { |
547 | value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner); |
548 | if (value != MBOX_OWNER_NONE) { |
549 | dev_err(tegra->dev, "mailbox is busy\n" ); |
550 | return -EBUSY; |
551 | } |
552 | |
553 | ops->mbox_reg_writel(tegra, MBOX_OWNER_SW, tegra->soc->mbox.owner); |
554 | |
555 | value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner); |
556 | if (value != MBOX_OWNER_SW) { |
557 | dev_err(tegra->dev, "failed to acquire mailbox\n" ); |
558 | return -EBUSY; |
559 | } |
560 | |
561 | wait_for_idle = true; |
562 | } |
563 | |
564 | value = tegra_xusb_mbox_pack(msg); |
565 | ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.data_in); |
566 | |
567 | value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.cmd); |
568 | value |= MBOX_INT_EN | MBOX_DEST_FALC; |
569 | ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.cmd); |
570 | |
571 | if (wait_for_idle) { |
572 | unsigned long timeout = jiffies + msecs_to_jiffies(m: 250); |
573 | |
574 | while (time_before(jiffies, timeout)) { |
575 | value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner); |
576 | if (value == MBOX_OWNER_NONE) |
577 | break; |
578 | |
579 | usleep_range(min: 10, max: 20); |
580 | } |
581 | |
582 | if (time_after(jiffies, timeout)) |
583 | value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner); |
584 | |
585 | if (value != MBOX_OWNER_NONE) |
586 | return -ETIMEDOUT; |
587 | } |
588 | |
589 | return 0; |
590 | } |
591 | |
592 | static irqreturn_t tegra_xusb_mbox_irq(int irq, void *data) |
593 | { |
594 | struct tegra_xusb *tegra = data; |
595 | const struct tegra_xusb_soc_ops *ops = tegra->soc->ops; |
596 | u32 value; |
597 | |
598 | /* clear mailbox interrupts */ |
599 | value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.smi_intr); |
600 | ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.smi_intr); |
601 | |
602 | if (value & MBOX_SMI_INTR_FW_HANG) |
603 | dev_err(tegra->dev, "controller firmware hang\n" ); |
604 | |
605 | return IRQ_WAKE_THREAD; |
606 | } |
607 | |
608 | static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra, |
609 | const struct tegra_xusb_mbox_msg *msg) |
610 | { |
611 | struct tegra_xusb_padctl *padctl = tegra->padctl; |
612 | const struct tegra_xusb_soc *soc = tegra->soc; |
613 | struct device *dev = tegra->dev; |
614 | struct tegra_xusb_mbox_msg rsp; |
615 | unsigned long mask; |
616 | unsigned int port; |
617 | bool idle, enable; |
618 | int err = 0; |
619 | |
620 | memset(&rsp, 0, sizeof(rsp)); |
621 | |
622 | switch (msg->cmd) { |
623 | case MBOX_CMD_INC_FALC_CLOCK: |
624 | case MBOX_CMD_DEC_FALC_CLOCK: |
625 | rsp.data = clk_get_rate(clk: tegra->falcon_clk) / 1000; |
626 | if (rsp.data != msg->data) |
627 | rsp.cmd = MBOX_CMD_NAK; |
628 | else |
629 | rsp.cmd = MBOX_CMD_ACK; |
630 | |
631 | break; |
632 | |
633 | case MBOX_CMD_INC_SSPI_CLOCK: |
634 | case MBOX_CMD_DEC_SSPI_CLOCK: |
635 | if (tegra->soc->scale_ss_clock) { |
636 | err = tegra_xusb_set_ss_clk(tegra, rate: msg->data * 1000); |
637 | if (err < 0) |
638 | rsp.cmd = MBOX_CMD_NAK; |
639 | else |
640 | rsp.cmd = MBOX_CMD_ACK; |
641 | |
642 | rsp.data = clk_get_rate(clk: tegra->ss_src_clk) / 1000; |
643 | } else { |
644 | rsp.cmd = MBOX_CMD_ACK; |
645 | rsp.data = msg->data; |
646 | } |
647 | |
648 | break; |
649 | |
650 | case MBOX_CMD_SET_BW: |
651 | /* |
652 | * TODO: Request bandwidth once EMC scaling is supported. |
653 | * Ignore for now since ACK/NAK is not required for SET_BW |
654 | * messages. |
655 | */ |
656 | break; |
657 | |
658 | case MBOX_CMD_SAVE_DFE_CTLE_CTX: |
659 | err = tegra_xusb_padctl_usb3_save_context(padctl, port: msg->data); |
660 | if (err < 0) { |
661 | dev_err(dev, "failed to save context for USB3#%u: %d\n" , |
662 | msg->data, err); |
663 | rsp.cmd = MBOX_CMD_NAK; |
664 | } else { |
665 | rsp.cmd = MBOX_CMD_ACK; |
666 | } |
667 | |
668 | rsp.data = msg->data; |
669 | break; |
670 | |
671 | case MBOX_CMD_START_HSIC_IDLE: |
672 | case MBOX_CMD_STOP_HSIC_IDLE: |
673 | if (msg->cmd == MBOX_CMD_STOP_HSIC_IDLE) |
674 | idle = false; |
675 | else |
676 | idle = true; |
677 | |
678 | mask = extract_field(value: msg->data, start: 1 + soc->ports.hsic.offset, |
679 | count: soc->ports.hsic.count); |
680 | |
681 | for_each_set_bit(port, &mask, 32) { |
682 | err = tegra_xusb_padctl_hsic_set_idle(padctl, port, |
683 | idle); |
684 | if (err < 0) |
685 | break; |
686 | } |
687 | |
688 | if (err < 0) { |
689 | dev_err(dev, "failed to set HSIC#%u %s: %d\n" , port, |
690 | idle ? "idle" : "busy" , err); |
691 | rsp.cmd = MBOX_CMD_NAK; |
692 | } else { |
693 | rsp.cmd = MBOX_CMD_ACK; |
694 | } |
695 | |
696 | rsp.data = msg->data; |
697 | break; |
698 | |
699 | case MBOX_CMD_DISABLE_SS_LFPS_DETECTION: |
700 | case MBOX_CMD_ENABLE_SS_LFPS_DETECTION: |
701 | if (msg->cmd == MBOX_CMD_DISABLE_SS_LFPS_DETECTION) |
702 | enable = false; |
703 | else |
704 | enable = true; |
705 | |
706 | mask = extract_field(value: msg->data, start: 1 + soc->ports.usb3.offset, |
707 | count: soc->ports.usb3.count); |
708 | |
709 | for_each_set_bit(port, &mask, soc->ports.usb3.count) { |
710 | err = tegra_xusb_padctl_usb3_set_lfps_detect(padctl, |
711 | port, |
712 | enable); |
713 | if (err < 0) |
714 | break; |
715 | |
716 | /* |
717 | * wait 500us for LFPS detector to be disabled before |
718 | * sending ACK |
719 | */ |
720 | if (!enable) |
721 | usleep_range(min: 500, max: 1000); |
722 | } |
723 | |
724 | if (err < 0) { |
725 | dev_err(dev, |
726 | "failed to %s LFPS detection on USB3#%u: %d\n" , |
727 | enable ? "enable" : "disable" , port, err); |
728 | rsp.cmd = MBOX_CMD_NAK; |
729 | } else { |
730 | rsp.cmd = MBOX_CMD_ACK; |
731 | } |
732 | |
733 | rsp.data = msg->data; |
734 | break; |
735 | |
736 | default: |
737 | dev_warn(dev, "unknown message: %#x\n" , msg->cmd); |
738 | break; |
739 | } |
740 | |
741 | if (rsp.cmd) { |
742 | const char *cmd = (rsp.cmd == MBOX_CMD_ACK) ? "ACK" : "NAK" ; |
743 | |
744 | err = tegra_xusb_mbox_send(tegra, msg: &rsp); |
745 | if (err < 0) |
746 | dev_err(dev, "failed to send %s: %d\n" , cmd, err); |
747 | } |
748 | } |
749 | |
750 | static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data) |
751 | { |
752 | struct tegra_xusb *tegra = data; |
753 | const struct tegra_xusb_soc_ops *ops = tegra->soc->ops; |
754 | struct tegra_xusb_mbox_msg msg; |
755 | u32 value; |
756 | |
757 | mutex_lock(&tegra->lock); |
758 | |
759 | if (pm_runtime_suspended(dev: tegra->dev) || tegra->suspended) |
760 | goto out; |
761 | |
762 | value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.data_out); |
763 | tegra_xusb_mbox_unpack(msg: &msg, value); |
764 | |
765 | value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.cmd); |
766 | value &= ~MBOX_DEST_SMI; |
767 | ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.cmd); |
768 | |
769 | /* clear mailbox owner if no ACK/NAK is required */ |
770 | if (!tegra_xusb_mbox_cmd_requires_ack(cmd: msg.cmd)) |
771 | ops->mbox_reg_writel(tegra, MBOX_OWNER_NONE, tegra->soc->mbox.owner); |
772 | |
773 | tegra_xusb_mbox_handle(tegra, msg: &msg); |
774 | |
775 | out: |
776 | mutex_unlock(lock: &tegra->lock); |
777 | return IRQ_HANDLED; |
778 | } |
779 | |
780 | static void tegra_xusb_config(struct tegra_xusb *tegra) |
781 | { |
782 | u32 regs = tegra->hcd->rsrc_start; |
783 | u32 value; |
784 | |
785 | if (tegra->soc->has_ipfs) { |
786 | value = ipfs_readl(tegra, IPFS_XUSB_HOST_CONFIGURATION_0); |
787 | value |= IPFS_EN_FPCI; |
788 | ipfs_writel(tegra, value, IPFS_XUSB_HOST_CONFIGURATION_0); |
789 | |
790 | usleep_range(min: 10, max: 20); |
791 | } |
792 | |
793 | /* Program BAR0 space */ |
794 | value = fpci_readl(tegra, XUSB_CFG_4); |
795 | value &= ~(XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT); |
796 | value |= regs & (XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT); |
797 | fpci_writel(tegra, value, XUSB_CFG_4); |
798 | |
799 | /* Program BAR2 space */ |
800 | if (tegra->bar2) { |
801 | value = fpci_readl(tegra, XUSB_CFG_7); |
802 | value &= ~(XUSB_BASE2_ADDR_MASK << XUSB_BASE2_ADDR_SHIFT); |
803 | value |= tegra->bar2->start & |
804 | (XUSB_BASE2_ADDR_MASK << XUSB_BASE2_ADDR_SHIFT); |
805 | fpci_writel(tegra, value, XUSB_CFG_7); |
806 | } |
807 | |
808 | usleep_range(min: 100, max: 200); |
809 | |
810 | /* Enable bus master */ |
811 | value = fpci_readl(tegra, XUSB_CFG_1); |
812 | value |= XUSB_IO_SPACE_EN | XUSB_MEM_SPACE_EN | XUSB_BUS_MASTER_EN; |
813 | fpci_writel(tegra, value, XUSB_CFG_1); |
814 | |
815 | if (tegra->soc->has_ipfs) { |
816 | /* Enable interrupt assertion */ |
817 | value = ipfs_readl(tegra, IPFS_XUSB_HOST_INTR_MASK_0); |
818 | value |= IPFS_IP_INT_MASK; |
819 | ipfs_writel(tegra, value, IPFS_XUSB_HOST_INTR_MASK_0); |
820 | |
821 | /* Set hysteresis */ |
822 | ipfs_writel(tegra, value: 0x80, IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0); |
823 | } |
824 | } |
825 | |
826 | static int tegra_xusb_clk_enable(struct tegra_xusb *tegra) |
827 | { |
828 | int err; |
829 | |
830 | err = clk_prepare_enable(clk: tegra->pll_e); |
831 | if (err < 0) |
832 | return err; |
833 | |
834 | err = clk_prepare_enable(clk: tegra->host_clk); |
835 | if (err < 0) |
836 | goto disable_plle; |
837 | |
838 | err = clk_prepare_enable(clk: tegra->ss_clk); |
839 | if (err < 0) |
840 | goto disable_host; |
841 | |
842 | err = clk_prepare_enable(clk: tegra->falcon_clk); |
843 | if (err < 0) |
844 | goto disable_ss; |
845 | |
846 | err = clk_prepare_enable(clk: tegra->fs_src_clk); |
847 | if (err < 0) |
848 | goto disable_falc; |
849 | |
850 | err = clk_prepare_enable(clk: tegra->hs_src_clk); |
851 | if (err < 0) |
852 | goto disable_fs_src; |
853 | |
854 | if (tegra->soc->scale_ss_clock) { |
855 | err = tegra_xusb_set_ss_clk(tegra, TEGRA_XHCI_SS_HIGH_SPEED); |
856 | if (err < 0) |
857 | goto disable_hs_src; |
858 | } |
859 | |
860 | return 0; |
861 | |
862 | disable_hs_src: |
863 | clk_disable_unprepare(clk: tegra->hs_src_clk); |
864 | disable_fs_src: |
865 | clk_disable_unprepare(clk: tegra->fs_src_clk); |
866 | disable_falc: |
867 | clk_disable_unprepare(clk: tegra->falcon_clk); |
868 | disable_ss: |
869 | clk_disable_unprepare(clk: tegra->ss_clk); |
870 | disable_host: |
871 | clk_disable_unprepare(clk: tegra->host_clk); |
872 | disable_plle: |
873 | clk_disable_unprepare(clk: tegra->pll_e); |
874 | return err; |
875 | } |
876 | |
877 | static void tegra_xusb_clk_disable(struct tegra_xusb *tegra) |
878 | { |
879 | clk_disable_unprepare(clk: tegra->pll_e); |
880 | clk_disable_unprepare(clk: tegra->host_clk); |
881 | clk_disable_unprepare(clk: tegra->ss_clk); |
882 | clk_disable_unprepare(clk: tegra->falcon_clk); |
883 | clk_disable_unprepare(clk: tegra->fs_src_clk); |
884 | clk_disable_unprepare(clk: tegra->hs_src_clk); |
885 | } |
886 | |
887 | static int tegra_xusb_phy_enable(struct tegra_xusb *tegra) |
888 | { |
889 | unsigned int i; |
890 | int err; |
891 | |
892 | for (i = 0; i < tegra->num_phys; i++) { |
893 | err = phy_init(phy: tegra->phys[i]); |
894 | if (err) |
895 | goto disable_phy; |
896 | |
897 | err = phy_power_on(phy: tegra->phys[i]); |
898 | if (err) { |
899 | phy_exit(phy: tegra->phys[i]); |
900 | goto disable_phy; |
901 | } |
902 | } |
903 | |
904 | return 0; |
905 | |
906 | disable_phy: |
907 | while (i--) { |
908 | phy_power_off(phy: tegra->phys[i]); |
909 | phy_exit(phy: tegra->phys[i]); |
910 | } |
911 | |
912 | return err; |
913 | } |
914 | |
915 | static void tegra_xusb_phy_disable(struct tegra_xusb *tegra) |
916 | { |
917 | unsigned int i; |
918 | |
919 | for (i = 0; i < tegra->num_phys; i++) { |
920 | phy_power_off(phy: tegra->phys[i]); |
921 | phy_exit(phy: tegra->phys[i]); |
922 | } |
923 | } |
924 | |
925 | #ifdef CONFIG_PM_SLEEP |
926 | static int tegra_xusb_init_context(struct tegra_xusb *tegra) |
927 | { |
928 | const struct tegra_xusb_context_soc *soc = tegra->soc->context; |
929 | |
930 | tegra->context.ipfs = devm_kcalloc(dev: tegra->dev, n: soc->ipfs.num_offsets, |
931 | size: sizeof(u32), GFP_KERNEL); |
932 | if (!tegra->context.ipfs) |
933 | return -ENOMEM; |
934 | |
935 | tegra->context.fpci = devm_kcalloc(dev: tegra->dev, n: soc->fpci.num_offsets, |
936 | size: sizeof(u32), GFP_KERNEL); |
937 | if (!tegra->context.fpci) |
938 | return -ENOMEM; |
939 | |
940 | return 0; |
941 | } |
942 | #else |
943 | static inline int tegra_xusb_init_context(struct tegra_xusb *tegra) |
944 | { |
945 | return 0; |
946 | } |
947 | #endif |
948 | |
949 | static int tegra_xusb_request_firmware(struct tegra_xusb *tegra) |
950 | { |
951 | struct tegra_xusb_fw_header *; |
952 | const struct firmware *fw; |
953 | int err; |
954 | |
955 | err = request_firmware(fw: &fw, name: tegra->soc->firmware, device: tegra->dev); |
956 | if (err < 0) { |
957 | dev_err(tegra->dev, "failed to request firmware: %d\n" , err); |
958 | return err; |
959 | } |
960 | |
961 | /* Load Falcon controller with its firmware. */ |
962 | header = (struct tegra_xusb_fw_header *)fw->data; |
963 | tegra->fw.size = le32_to_cpu(header->fwimg_len); |
964 | |
965 | tegra->fw.virt = dma_alloc_coherent(dev: tegra->dev, size: tegra->fw.size, |
966 | dma_handle: &tegra->fw.phys, GFP_KERNEL); |
967 | if (!tegra->fw.virt) { |
968 | dev_err(tegra->dev, "failed to allocate memory for firmware\n" ); |
969 | release_firmware(fw); |
970 | return -ENOMEM; |
971 | } |
972 | |
973 | header = (struct tegra_xusb_fw_header *)tegra->fw.virt; |
974 | memcpy(tegra->fw.virt, fw->data, tegra->fw.size); |
975 | release_firmware(fw); |
976 | |
977 | return 0; |
978 | } |
979 | |
980 | static int tegra_xusb_wait_for_falcon(struct tegra_xusb *tegra) |
981 | { |
982 | struct xhci_cap_regs __iomem *cap_regs; |
983 | struct xhci_op_regs __iomem *op_regs; |
984 | int ret; |
985 | u32 value; |
986 | |
987 | cap_regs = tegra->regs; |
988 | op_regs = tegra->regs + HC_LENGTH(readl(&cap_regs->hc_capbase)); |
989 | |
990 | ret = readl_poll_timeout(&op_regs->status, value, !(value & STS_CNR), 1000, 200000); |
991 | |
992 | if (ret) |
993 | dev_err(tegra->dev, "XHCI Controller not ready. Falcon state: 0x%x\n" , |
994 | csb_readl(tegra, XUSB_FALC_CPUCTL)); |
995 | |
996 | return ret; |
997 | } |
998 | |
999 | static int tegra_xusb_load_firmware_rom(struct tegra_xusb *tegra) |
1000 | { |
1001 | unsigned int code_tag_blocks, code_size_blocks, code_blocks; |
1002 | struct tegra_xusb_fw_header *; |
1003 | struct device *dev = tegra->dev; |
1004 | time64_t timestamp; |
1005 | u64 address; |
1006 | u32 value; |
1007 | int err; |
1008 | |
1009 | header = (struct tegra_xusb_fw_header *)tegra->fw.virt; |
1010 | |
1011 | if (csb_readl(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) { |
1012 | dev_info(dev, "Firmware already loaded, Falcon state %#x\n" , |
1013 | csb_readl(tegra, XUSB_FALC_CPUCTL)); |
1014 | return 0; |
1015 | } |
1016 | |
1017 | /* Program the size of DFI into ILOAD_ATTR. */ |
1018 | csb_writel(tegra, value: tegra->fw.size, XUSB_CSB_MP_ILOAD_ATTR); |
1019 | |
1020 | /* |
1021 | * Boot code of the firmware reads the ILOAD_BASE registers |
1022 | * to get to the start of the DFI in system memory. |
1023 | */ |
1024 | address = tegra->fw.phys + sizeof(*header); |
1025 | csb_writel(tegra, value: address >> 32, XUSB_CSB_MP_ILOAD_BASE_HI); |
1026 | csb_writel(tegra, value: address, XUSB_CSB_MP_ILOAD_BASE_LO); |
1027 | |
1028 | /* Set BOOTPATH to 1 in APMAP. */ |
1029 | csb_writel(tegra, APMAP_BOOTPATH, XUSB_CSB_MP_APMAP); |
1030 | |
1031 | /* Invalidate L2IMEM. */ |
1032 | csb_writel(tegra, L2IMEMOP_INVALIDATE_ALL, XUSB_CSB_MP_L2IMEMOP_TRIG); |
1033 | |
1034 | /* |
1035 | * Initiate fetch of bootcode from system memory into L2IMEM. |
1036 | * Program bootcode location and size in system memory. |
1037 | */ |
1038 | code_tag_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codetag), |
1039 | IMEM_BLOCK_SIZE); |
1040 | code_size_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codesize), |
1041 | IMEM_BLOCK_SIZE); |
1042 | code_blocks = code_tag_blocks + code_size_blocks; |
1043 | |
1044 | value = ((code_tag_blocks & L2IMEMOP_SIZE_SRC_OFFSET_MASK) << |
1045 | L2IMEMOP_SIZE_SRC_OFFSET_SHIFT) | |
1046 | ((code_size_blocks & L2IMEMOP_SIZE_SRC_COUNT_MASK) << |
1047 | L2IMEMOP_SIZE_SRC_COUNT_SHIFT); |
1048 | csb_writel(tegra, value, XUSB_CSB_MP_L2IMEMOP_SIZE); |
1049 | |
1050 | /* Trigger L2IMEM load operation. */ |
1051 | csb_writel(tegra, L2IMEMOP_LOAD_LOCKED_RESULT, |
1052 | XUSB_CSB_MP_L2IMEMOP_TRIG); |
1053 | |
1054 | /* Setup Falcon auto-fill. */ |
1055 | csb_writel(tegra, value: code_size_blocks, XUSB_FALC_IMFILLCTL); |
1056 | |
1057 | value = ((code_tag_blocks & IMFILLRNG1_TAG_MASK) << |
1058 | IMFILLRNG1_TAG_LO_SHIFT) | |
1059 | ((code_blocks & IMFILLRNG1_TAG_MASK) << |
1060 | IMFILLRNG1_TAG_HI_SHIFT); |
1061 | csb_writel(tegra, value, XUSB_FALC_IMFILLRNG1); |
1062 | |
1063 | csb_writel(tegra, value: 0, XUSB_FALC_DMACTL); |
1064 | |
1065 | /* wait for RESULT_VLD to get set */ |
1066 | #define tegra_csb_readl(offset) csb_readl(tegra, offset) |
1067 | err = readx_poll_timeout(tegra_csb_readl, |
1068 | XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT, value, |
1069 | value & L2IMEMOP_RESULT_VLD, 100, 10000); |
1070 | if (err < 0) { |
1071 | dev_err(dev, "DMA controller not ready %#010x\n" , value); |
1072 | return err; |
1073 | } |
1074 | #undef tegra_csb_readl |
1075 | |
1076 | csb_writel(tegra, le32_to_cpu(header->boot_codetag), |
1077 | XUSB_FALC_BOOTVEC); |
1078 | |
1079 | /* Boot Falcon CPU and wait for USBSTS_CNR to get cleared. */ |
1080 | csb_writel(tegra, CPUCTL_STARTCPU, XUSB_FALC_CPUCTL); |
1081 | |
1082 | if (tegra_xusb_wait_for_falcon(tegra)) |
1083 | return -EIO; |
1084 | |
1085 | timestamp = le32_to_cpu(header->fwimg_created_time); |
1086 | |
1087 | dev_info(dev, "Firmware timestamp: %ptTs UTC\n" , ×tamp); |
1088 | |
1089 | return 0; |
1090 | } |
1091 | |
1092 | static u32 (struct tegra_xusb *tegra, u32 offset) |
1093 | { |
1094 | /* |
1095 | * We only accept reading the firmware config table |
1096 | * The offset should not exceed the fw header structure |
1097 | */ |
1098 | if (offset >= sizeof(struct tegra_xusb_fw_header)) |
1099 | return 0; |
1100 | |
1101 | bar2_writel(tegra, value: (FW_IOCTL_CFGTBL_READ << FW_IOCTL_TYPE_SHIFT) | offset, |
1102 | XUSB_BAR2_ARU_FW_SCRATCH); |
1103 | return bar2_readl(tegra, XUSB_BAR2_ARU_SMI_ARU_FW_SCRATCH_DATA0); |
1104 | } |
1105 | |
1106 | static int tegra_xusb_init_ifr_firmware(struct tegra_xusb *tegra) |
1107 | { |
1108 | time64_t timestamp; |
1109 | |
1110 | if (tegra_xusb_wait_for_falcon(tegra)) |
1111 | return -EIO; |
1112 | |
1113 | #define offsetof_32(X, Y) ((u8)(offsetof(X, Y) / sizeof(__le32))) |
1114 | timestamp = tegra_xusb_read_firmware_header(tegra, offsetof_32(struct tegra_xusb_fw_header, |
1115 | fwimg_created_time) << 2); |
1116 | |
1117 | dev_info(tegra->dev, "Firmware timestamp: %ptTs UTC\n" , ×tamp); |
1118 | |
1119 | return 0; |
1120 | } |
1121 | |
1122 | static int tegra_xusb_load_firmware(struct tegra_xusb *tegra) |
1123 | { |
1124 | if (!tegra->soc->firmware) |
1125 | return tegra_xusb_init_ifr_firmware(tegra); |
1126 | else |
1127 | return tegra_xusb_load_firmware_rom(tegra); |
1128 | } |
1129 | |
1130 | static void tegra_xusb_powerdomain_remove(struct device *dev, |
1131 | struct tegra_xusb *tegra) |
1132 | { |
1133 | if (!tegra->use_genpd) |
1134 | return; |
1135 | |
1136 | if (!IS_ERR_OR_NULL(ptr: tegra->genpd_dev_ss)) |
1137 | dev_pm_domain_detach(dev: tegra->genpd_dev_ss, power_off: true); |
1138 | if (!IS_ERR_OR_NULL(ptr: tegra->genpd_dev_host)) |
1139 | dev_pm_domain_detach(dev: tegra->genpd_dev_host, power_off: true); |
1140 | } |
1141 | |
1142 | static int tegra_xusb_powerdomain_init(struct device *dev, |
1143 | struct tegra_xusb *tegra) |
1144 | { |
1145 | int err; |
1146 | |
1147 | tegra->genpd_dev_host = dev_pm_domain_attach_by_name(dev, name: "xusb_host" ); |
1148 | if (IS_ERR(ptr: tegra->genpd_dev_host)) { |
1149 | err = PTR_ERR(ptr: tegra->genpd_dev_host); |
1150 | dev_err(dev, "failed to get host pm-domain: %d\n" , err); |
1151 | return err; |
1152 | } |
1153 | |
1154 | tegra->genpd_dev_ss = dev_pm_domain_attach_by_name(dev, name: "xusb_ss" ); |
1155 | if (IS_ERR(ptr: tegra->genpd_dev_ss)) { |
1156 | err = PTR_ERR(ptr: tegra->genpd_dev_ss); |
1157 | dev_err(dev, "failed to get superspeed pm-domain: %d\n" , err); |
1158 | return err; |
1159 | } |
1160 | |
1161 | tegra->use_genpd = true; |
1162 | |
1163 | return 0; |
1164 | } |
1165 | |
1166 | static int tegra_xusb_unpowergate_partitions(struct tegra_xusb *tegra) |
1167 | { |
1168 | struct device *dev = tegra->dev; |
1169 | int rc; |
1170 | |
1171 | if (tegra->use_genpd) { |
1172 | rc = pm_runtime_resume_and_get(dev: tegra->genpd_dev_ss); |
1173 | if (rc < 0) { |
1174 | dev_err(dev, "failed to enable XUSB SS partition\n" ); |
1175 | return rc; |
1176 | } |
1177 | |
1178 | rc = pm_runtime_resume_and_get(dev: tegra->genpd_dev_host); |
1179 | if (rc < 0) { |
1180 | dev_err(dev, "failed to enable XUSB Host partition\n" ); |
1181 | pm_runtime_put_sync(dev: tegra->genpd_dev_ss); |
1182 | return rc; |
1183 | } |
1184 | } else { |
1185 | rc = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBA, |
1186 | clk: tegra->ss_clk, |
1187 | rst: tegra->ss_rst); |
1188 | if (rc < 0) { |
1189 | dev_err(dev, "failed to enable XUSB SS partition\n" ); |
1190 | return rc; |
1191 | } |
1192 | |
1193 | rc = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC, |
1194 | clk: tegra->host_clk, |
1195 | rst: tegra->host_rst); |
1196 | if (rc < 0) { |
1197 | dev_err(dev, "failed to enable XUSB Host partition\n" ); |
1198 | tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA); |
1199 | return rc; |
1200 | } |
1201 | } |
1202 | |
1203 | return 0; |
1204 | } |
1205 | |
1206 | static int tegra_xusb_powergate_partitions(struct tegra_xusb *tegra) |
1207 | { |
1208 | struct device *dev = tegra->dev; |
1209 | int rc; |
1210 | |
1211 | if (tegra->use_genpd) { |
1212 | rc = pm_runtime_put_sync(dev: tegra->genpd_dev_host); |
1213 | if (rc < 0) { |
1214 | dev_err(dev, "failed to disable XUSB Host partition\n" ); |
1215 | return rc; |
1216 | } |
1217 | |
1218 | rc = pm_runtime_put_sync(dev: tegra->genpd_dev_ss); |
1219 | if (rc < 0) { |
1220 | dev_err(dev, "failed to disable XUSB SS partition\n" ); |
1221 | pm_runtime_get_sync(dev: tegra->genpd_dev_host); |
1222 | return rc; |
1223 | } |
1224 | } else { |
1225 | rc = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC); |
1226 | if (rc < 0) { |
1227 | dev_err(dev, "failed to disable XUSB Host partition\n" ); |
1228 | return rc; |
1229 | } |
1230 | |
1231 | rc = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA); |
1232 | if (rc < 0) { |
1233 | dev_err(dev, "failed to disable XUSB SS partition\n" ); |
1234 | tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC, |
1235 | clk: tegra->host_clk, |
1236 | rst: tegra->host_rst); |
1237 | return rc; |
1238 | } |
1239 | } |
1240 | |
1241 | return 0; |
1242 | } |
1243 | |
1244 | static int __tegra_xusb_enable_firmware_messages(struct tegra_xusb *tegra) |
1245 | { |
1246 | struct tegra_xusb_mbox_msg msg; |
1247 | int err; |
1248 | |
1249 | /* Enable firmware messages from controller. */ |
1250 | msg.cmd = MBOX_CMD_MSG_ENABLED; |
1251 | msg.data = 0; |
1252 | |
1253 | err = tegra_xusb_mbox_send(tegra, msg: &msg); |
1254 | if (err < 0) |
1255 | dev_err(tegra->dev, "failed to enable messages: %d\n" , err); |
1256 | |
1257 | return err; |
1258 | } |
1259 | |
1260 | static irqreturn_t tegra_xusb_padctl_irq(int irq, void *data) |
1261 | { |
1262 | struct tegra_xusb *tegra = data; |
1263 | |
1264 | mutex_lock(&tegra->lock); |
1265 | |
1266 | if (tegra->suspended) { |
1267 | mutex_unlock(lock: &tegra->lock); |
1268 | return IRQ_HANDLED; |
1269 | } |
1270 | |
1271 | mutex_unlock(lock: &tegra->lock); |
1272 | |
1273 | pm_runtime_resume(dev: tegra->dev); |
1274 | |
1275 | return IRQ_HANDLED; |
1276 | } |
1277 | |
1278 | static int tegra_xusb_enable_firmware_messages(struct tegra_xusb *tegra) |
1279 | { |
1280 | int err; |
1281 | |
1282 | mutex_lock(&tegra->lock); |
1283 | err = __tegra_xusb_enable_firmware_messages(tegra); |
1284 | mutex_unlock(lock: &tegra->lock); |
1285 | |
1286 | return err; |
1287 | } |
1288 | |
1289 | static void tegra_xhci_set_port_power(struct tegra_xusb *tegra, bool main, |
1290 | bool set) |
1291 | { |
1292 | struct xhci_hcd *xhci = hcd_to_xhci(hcd: tegra->hcd); |
1293 | struct usb_hcd *hcd = main ? xhci->main_hcd : xhci->shared_hcd; |
1294 | unsigned int wait = (!main && !set) ? 1000 : 10; |
1295 | u16 typeReq = set ? SetPortFeature : ClearPortFeature; |
1296 | u16 wIndex = main ? tegra->otg_usb2_port + 1 : tegra->otg_usb3_port + 1; |
1297 | u32 status; |
1298 | u32 stat_power = main ? USB_PORT_STAT_POWER : USB_SS_PORT_STAT_POWER; |
1299 | u32 status_val = set ? stat_power : 0; |
1300 | |
1301 | dev_dbg(tegra->dev, "%s():%s %s port power\n" , __func__, |
1302 | set ? "set" : "clear" , main ? "HS" : "SS" ); |
1303 | |
1304 | hcd->driver->hub_control(hcd, typeReq, USB_PORT_FEAT_POWER, wIndex, |
1305 | NULL, 0); |
1306 | |
1307 | do { |
1308 | tegra_xhci_hc_driver.hub_control(hcd, GetPortStatus, 0, wIndex, |
1309 | (char *) &status, sizeof(status)); |
1310 | if (status_val == (status & stat_power)) |
1311 | break; |
1312 | |
1313 | if (!main && !set) |
1314 | usleep_range(min: 600, max: 700); |
1315 | else |
1316 | usleep_range(min: 10, max: 20); |
1317 | } while (--wait > 0); |
1318 | |
1319 | if (status_val != (status & stat_power)) |
1320 | dev_info(tegra->dev, "failed to %s %s PP %d\n" , |
1321 | set ? "set" : "clear" , |
1322 | main ? "HS" : "SS" , status); |
1323 | } |
1324 | |
1325 | static struct phy *tegra_xusb_get_phy(struct tegra_xusb *tegra, char *name, |
1326 | int port) |
1327 | { |
1328 | unsigned int i, phy_count = 0; |
1329 | |
1330 | for (i = 0; i < tegra->soc->num_types; i++) { |
1331 | if (!strncmp(tegra->soc->phy_types[i].name, name, |
1332 | strlen(name))) |
1333 | return tegra->phys[phy_count+port]; |
1334 | |
1335 | phy_count += tegra->soc->phy_types[i].num; |
1336 | } |
1337 | |
1338 | return NULL; |
1339 | } |
1340 | |
1341 | static void tegra_xhci_id_work(struct work_struct *work) |
1342 | { |
1343 | struct tegra_xusb *tegra = container_of(work, struct tegra_xusb, |
1344 | id_work); |
1345 | struct xhci_hcd *xhci = hcd_to_xhci(hcd: tegra->hcd); |
1346 | struct tegra_xusb_mbox_msg msg; |
1347 | struct phy *phy = tegra_xusb_get_phy(tegra, name: "usb2" , |
1348 | port: tegra->otg_usb2_port); |
1349 | u32 status; |
1350 | int ret; |
1351 | |
1352 | dev_dbg(tegra->dev, "host mode %s\n" , tegra->host_mode ? "on" : "off" ); |
1353 | |
1354 | mutex_lock(&tegra->lock); |
1355 | |
1356 | if (tegra->host_mode) |
1357 | phy_set_mode_ext(phy, mode: PHY_MODE_USB_OTG, submode: USB_ROLE_HOST); |
1358 | else |
1359 | phy_set_mode_ext(phy, mode: PHY_MODE_USB_OTG, submode: USB_ROLE_NONE); |
1360 | |
1361 | mutex_unlock(lock: &tegra->lock); |
1362 | |
1363 | tegra->otg_usb3_port = tegra_xusb_padctl_get_usb3_companion(padctl: tegra->padctl, |
1364 | port: tegra->otg_usb2_port); |
1365 | |
1366 | if (tegra->host_mode) { |
1367 | /* switch to host mode */ |
1368 | if (tegra->otg_usb3_port >= 0) { |
1369 | if (tegra->soc->otg_reset_sspi) { |
1370 | /* set PP=0 */ |
1371 | tegra_xhci_hc_driver.hub_control( |
1372 | xhci->shared_hcd, GetPortStatus, |
1373 | 0, tegra->otg_usb3_port+1, |
1374 | (char *) &status, sizeof(status)); |
1375 | if (status & USB_SS_PORT_STAT_POWER) |
1376 | tegra_xhci_set_port_power(tegra, main: false, |
1377 | set: false); |
1378 | |
1379 | /* reset OTG port SSPI */ |
1380 | msg.cmd = MBOX_CMD_RESET_SSPI; |
1381 | msg.data = tegra->otg_usb3_port+1; |
1382 | |
1383 | ret = tegra_xusb_mbox_send(tegra, msg: &msg); |
1384 | if (ret < 0) { |
1385 | dev_info(tegra->dev, |
1386 | "failed to RESET_SSPI %d\n" , |
1387 | ret); |
1388 | } |
1389 | } |
1390 | |
1391 | tegra_xhci_set_port_power(tegra, main: false, set: true); |
1392 | } |
1393 | |
1394 | tegra_xhci_set_port_power(tegra, main: true, set: true); |
1395 | |
1396 | } else { |
1397 | if (tegra->otg_usb3_port >= 0) |
1398 | tegra_xhci_set_port_power(tegra, main: false, set: false); |
1399 | |
1400 | tegra_xhci_set_port_power(tegra, main: true, set: false); |
1401 | } |
1402 | } |
1403 | |
1404 | #if IS_ENABLED(CONFIG_PM) || IS_ENABLED(CONFIG_PM_SLEEP) |
1405 | static bool is_usb2_otg_phy(struct tegra_xusb *tegra, unsigned int index) |
1406 | { |
1407 | return (tegra->usbphy[index] != NULL); |
1408 | } |
1409 | |
1410 | static bool is_usb3_otg_phy(struct tegra_xusb *tegra, unsigned int index) |
1411 | { |
1412 | struct tegra_xusb_padctl *padctl = tegra->padctl; |
1413 | unsigned int i; |
1414 | int port; |
1415 | |
1416 | for (i = 0; i < tegra->num_usb_phys; i++) { |
1417 | if (is_usb2_otg_phy(tegra, index: i)) { |
1418 | port = tegra_xusb_padctl_get_usb3_companion(padctl, port: i); |
1419 | if ((port >= 0) && (index == (unsigned int)port)) |
1420 | return true; |
1421 | } |
1422 | } |
1423 | |
1424 | return false; |
1425 | } |
1426 | |
1427 | static bool is_host_mode_phy(struct tegra_xusb *tegra, unsigned int phy_type, unsigned int index) |
1428 | { |
1429 | if (strcmp(tegra->soc->phy_types[phy_type].name, "hsic" ) == 0) |
1430 | return true; |
1431 | |
1432 | if (strcmp(tegra->soc->phy_types[phy_type].name, "usb2" ) == 0) { |
1433 | if (is_usb2_otg_phy(tegra, index)) |
1434 | return ((index == tegra->otg_usb2_port) && tegra->host_mode); |
1435 | else |
1436 | return true; |
1437 | } |
1438 | |
1439 | if (strcmp(tegra->soc->phy_types[phy_type].name, "usb3" ) == 0) { |
1440 | if (is_usb3_otg_phy(tegra, index)) |
1441 | return ((index == tegra->otg_usb3_port) && tegra->host_mode); |
1442 | else |
1443 | return true; |
1444 | } |
1445 | |
1446 | return false; |
1447 | } |
1448 | #endif |
1449 | |
1450 | static int tegra_xusb_get_usb2_port(struct tegra_xusb *tegra, |
1451 | struct usb_phy *usbphy) |
1452 | { |
1453 | unsigned int i; |
1454 | |
1455 | for (i = 0; i < tegra->num_usb_phys; i++) { |
1456 | if (tegra->usbphy[i] && usbphy == tegra->usbphy[i]) |
1457 | return i; |
1458 | } |
1459 | |
1460 | return -1; |
1461 | } |
1462 | |
1463 | static int tegra_xhci_id_notify(struct notifier_block *nb, |
1464 | unsigned long action, void *data) |
1465 | { |
1466 | struct tegra_xusb *tegra = container_of(nb, struct tegra_xusb, |
1467 | id_nb); |
1468 | struct usb_phy *usbphy = (struct usb_phy *)data; |
1469 | |
1470 | dev_dbg(tegra->dev, "%s(): action is %d" , __func__, usbphy->last_event); |
1471 | |
1472 | if ((tegra->host_mode && usbphy->last_event == USB_EVENT_ID) || |
1473 | (!tegra->host_mode && usbphy->last_event != USB_EVENT_ID)) { |
1474 | dev_dbg(tegra->dev, "Same role(%d) received. Ignore" , |
1475 | tegra->host_mode); |
1476 | return NOTIFY_OK; |
1477 | } |
1478 | |
1479 | tegra->otg_usb2_port = tegra_xusb_get_usb2_port(tegra, usbphy); |
1480 | |
1481 | tegra->host_mode = (usbphy->last_event == USB_EVENT_ID) ? true : false; |
1482 | |
1483 | schedule_work(work: &tegra->id_work); |
1484 | |
1485 | return NOTIFY_OK; |
1486 | } |
1487 | |
1488 | static int tegra_xusb_init_usb_phy(struct tegra_xusb *tegra) |
1489 | { |
1490 | unsigned int i; |
1491 | |
1492 | tegra->usbphy = devm_kcalloc(dev: tegra->dev, n: tegra->num_usb_phys, |
1493 | size: sizeof(*tegra->usbphy), GFP_KERNEL); |
1494 | if (!tegra->usbphy) |
1495 | return -ENOMEM; |
1496 | |
1497 | INIT_WORK(&tegra->id_work, tegra_xhci_id_work); |
1498 | tegra->id_nb.notifier_call = tegra_xhci_id_notify; |
1499 | tegra->otg_usb2_port = -EINVAL; |
1500 | tegra->otg_usb3_port = -EINVAL; |
1501 | |
1502 | for (i = 0; i < tegra->num_usb_phys; i++) { |
1503 | struct phy *phy = tegra_xusb_get_phy(tegra, name: "usb2" , port: i); |
1504 | |
1505 | if (!phy) |
1506 | continue; |
1507 | |
1508 | tegra->usbphy[i] = devm_usb_get_phy_by_node(dev: tegra->dev, |
1509 | node: phy->dev.of_node, |
1510 | nb: &tegra->id_nb); |
1511 | if (!IS_ERR(ptr: tegra->usbphy[i])) { |
1512 | dev_dbg(tegra->dev, "usbphy-%d registered" , i); |
1513 | otg_set_host(otg: tegra->usbphy[i]->otg, host: &tegra->hcd->self); |
1514 | } else { |
1515 | /* |
1516 | * usb-phy is optional, continue if its not available. |
1517 | */ |
1518 | tegra->usbphy[i] = NULL; |
1519 | } |
1520 | } |
1521 | |
1522 | return 0; |
1523 | } |
1524 | |
1525 | static void tegra_xusb_deinit_usb_phy(struct tegra_xusb *tegra) |
1526 | { |
1527 | unsigned int i; |
1528 | |
1529 | cancel_work_sync(work: &tegra->id_work); |
1530 | |
1531 | for (i = 0; i < tegra->num_usb_phys; i++) |
1532 | if (tegra->usbphy[i]) |
1533 | otg_set_host(otg: tegra->usbphy[i]->otg, NULL); |
1534 | } |
1535 | |
1536 | static int tegra_xusb_probe(struct platform_device *pdev) |
1537 | { |
1538 | struct tegra_xusb *tegra; |
1539 | struct device_node *np; |
1540 | struct resource *regs; |
1541 | struct xhci_hcd *xhci; |
1542 | unsigned int i, j, k; |
1543 | struct phy *phy; |
1544 | int err; |
1545 | |
1546 | BUILD_BUG_ON(sizeof(struct tegra_xusb_fw_header) != 256); |
1547 | |
1548 | tegra = devm_kzalloc(dev: &pdev->dev, size: sizeof(*tegra), GFP_KERNEL); |
1549 | if (!tegra) |
1550 | return -ENOMEM; |
1551 | |
1552 | tegra->soc = of_device_get_match_data(dev: &pdev->dev); |
1553 | mutex_init(&tegra->lock); |
1554 | tegra->dev = &pdev->dev; |
1555 | |
1556 | err = tegra_xusb_init_context(tegra); |
1557 | if (err < 0) |
1558 | return err; |
1559 | |
1560 | tegra->regs = devm_platform_get_and_ioremap_resource(pdev, index: 0, res: ®s); |
1561 | if (IS_ERR(ptr: tegra->regs)) |
1562 | return PTR_ERR(ptr: tegra->regs); |
1563 | |
1564 | tegra->fpci_base = devm_platform_ioremap_resource(pdev, index: 1); |
1565 | if (IS_ERR(ptr: tegra->fpci_base)) |
1566 | return PTR_ERR(ptr: tegra->fpci_base); |
1567 | |
1568 | if (tegra->soc->has_ipfs) { |
1569 | tegra->ipfs_base = devm_platform_ioremap_resource(pdev, index: 2); |
1570 | if (IS_ERR(ptr: tegra->ipfs_base)) |
1571 | return PTR_ERR(ptr: tegra->ipfs_base); |
1572 | } else if (tegra->soc->has_bar2) { |
1573 | tegra->bar2_base = devm_platform_get_and_ioremap_resource(pdev, index: 2, res: &tegra->bar2); |
1574 | if (IS_ERR(ptr: tegra->bar2_base)) |
1575 | return PTR_ERR(ptr: tegra->bar2_base); |
1576 | } |
1577 | |
1578 | tegra->xhci_irq = platform_get_irq(pdev, 0); |
1579 | if (tegra->xhci_irq < 0) |
1580 | return tegra->xhci_irq; |
1581 | |
1582 | tegra->mbox_irq = platform_get_irq(pdev, 1); |
1583 | if (tegra->mbox_irq < 0) |
1584 | return tegra->mbox_irq; |
1585 | |
1586 | tegra->padctl = tegra_xusb_padctl_get(dev: &pdev->dev); |
1587 | if (IS_ERR(ptr: tegra->padctl)) |
1588 | return PTR_ERR(ptr: tegra->padctl); |
1589 | |
1590 | np = of_parse_phandle(np: pdev->dev.of_node, phandle_name: "nvidia,xusb-padctl" , index: 0); |
1591 | if (!np) { |
1592 | err = -ENODEV; |
1593 | goto put_padctl; |
1594 | } |
1595 | |
1596 | tegra->padctl_irq = of_irq_get(dev: np, index: 0); |
1597 | if (tegra->padctl_irq == -EPROBE_DEFER) { |
1598 | err = tegra->padctl_irq; |
1599 | goto put_padctl; |
1600 | } else if (tegra->padctl_irq <= 0) { |
1601 | /* Older device-trees don't have padctrl interrupt */ |
1602 | tegra->padctl_irq = 0; |
1603 | dev_dbg(&pdev->dev, |
1604 | "%pOF is missing an interrupt, disabling PM support\n" , np); |
1605 | } |
1606 | |
1607 | tegra->host_clk = devm_clk_get(dev: &pdev->dev, id: "xusb_host" ); |
1608 | if (IS_ERR(ptr: tegra->host_clk)) { |
1609 | err = PTR_ERR(ptr: tegra->host_clk); |
1610 | dev_err(&pdev->dev, "failed to get xusb_host: %d\n" , err); |
1611 | goto put_padctl; |
1612 | } |
1613 | |
1614 | tegra->falcon_clk = devm_clk_get(dev: &pdev->dev, id: "xusb_falcon_src" ); |
1615 | if (IS_ERR(ptr: tegra->falcon_clk)) { |
1616 | err = PTR_ERR(ptr: tegra->falcon_clk); |
1617 | dev_err(&pdev->dev, "failed to get xusb_falcon_src: %d\n" , err); |
1618 | goto put_padctl; |
1619 | } |
1620 | |
1621 | tegra->ss_clk = devm_clk_get(dev: &pdev->dev, id: "xusb_ss" ); |
1622 | if (IS_ERR(ptr: tegra->ss_clk)) { |
1623 | err = PTR_ERR(ptr: tegra->ss_clk); |
1624 | dev_err(&pdev->dev, "failed to get xusb_ss: %d\n" , err); |
1625 | goto put_padctl; |
1626 | } |
1627 | |
1628 | tegra->ss_src_clk = devm_clk_get(dev: &pdev->dev, id: "xusb_ss_src" ); |
1629 | if (IS_ERR(ptr: tegra->ss_src_clk)) { |
1630 | err = PTR_ERR(ptr: tegra->ss_src_clk); |
1631 | dev_err(&pdev->dev, "failed to get xusb_ss_src: %d\n" , err); |
1632 | goto put_padctl; |
1633 | } |
1634 | |
1635 | tegra->hs_src_clk = devm_clk_get(dev: &pdev->dev, id: "xusb_hs_src" ); |
1636 | if (IS_ERR(ptr: tegra->hs_src_clk)) { |
1637 | err = PTR_ERR(ptr: tegra->hs_src_clk); |
1638 | dev_err(&pdev->dev, "failed to get xusb_hs_src: %d\n" , err); |
1639 | goto put_padctl; |
1640 | } |
1641 | |
1642 | tegra->fs_src_clk = devm_clk_get(dev: &pdev->dev, id: "xusb_fs_src" ); |
1643 | if (IS_ERR(ptr: tegra->fs_src_clk)) { |
1644 | err = PTR_ERR(ptr: tegra->fs_src_clk); |
1645 | dev_err(&pdev->dev, "failed to get xusb_fs_src: %d\n" , err); |
1646 | goto put_padctl; |
1647 | } |
1648 | |
1649 | tegra->pll_u_480m = devm_clk_get(dev: &pdev->dev, id: "pll_u_480m" ); |
1650 | if (IS_ERR(ptr: tegra->pll_u_480m)) { |
1651 | err = PTR_ERR(ptr: tegra->pll_u_480m); |
1652 | dev_err(&pdev->dev, "failed to get pll_u_480m: %d\n" , err); |
1653 | goto put_padctl; |
1654 | } |
1655 | |
1656 | tegra->clk_m = devm_clk_get(dev: &pdev->dev, id: "clk_m" ); |
1657 | if (IS_ERR(ptr: tegra->clk_m)) { |
1658 | err = PTR_ERR(ptr: tegra->clk_m); |
1659 | dev_err(&pdev->dev, "failed to get clk_m: %d\n" , err); |
1660 | goto put_padctl; |
1661 | } |
1662 | |
1663 | tegra->pll_e = devm_clk_get(dev: &pdev->dev, id: "pll_e" ); |
1664 | if (IS_ERR(ptr: tegra->pll_e)) { |
1665 | err = PTR_ERR(ptr: tegra->pll_e); |
1666 | dev_err(&pdev->dev, "failed to get pll_e: %d\n" , err); |
1667 | goto put_padctl; |
1668 | } |
1669 | |
1670 | if (!of_property_read_bool(np: pdev->dev.of_node, propname: "power-domains" )) { |
1671 | tegra->host_rst = devm_reset_control_get(dev: &pdev->dev, |
1672 | id: "xusb_host" ); |
1673 | if (IS_ERR(ptr: tegra->host_rst)) { |
1674 | err = PTR_ERR(ptr: tegra->host_rst); |
1675 | dev_err(&pdev->dev, |
1676 | "failed to get xusb_host reset: %d\n" , err); |
1677 | goto put_padctl; |
1678 | } |
1679 | |
1680 | tegra->ss_rst = devm_reset_control_get(dev: &pdev->dev, id: "xusb_ss" ); |
1681 | if (IS_ERR(ptr: tegra->ss_rst)) { |
1682 | err = PTR_ERR(ptr: tegra->ss_rst); |
1683 | dev_err(&pdev->dev, "failed to get xusb_ss reset: %d\n" , |
1684 | err); |
1685 | goto put_padctl; |
1686 | } |
1687 | } else { |
1688 | err = tegra_xusb_powerdomain_init(dev: &pdev->dev, tegra); |
1689 | if (err) |
1690 | goto put_powerdomains; |
1691 | } |
1692 | |
1693 | tegra->supplies = devm_kcalloc(dev: &pdev->dev, n: tegra->soc->num_supplies, |
1694 | size: sizeof(*tegra->supplies), GFP_KERNEL); |
1695 | if (!tegra->supplies) { |
1696 | err = -ENOMEM; |
1697 | goto put_powerdomains; |
1698 | } |
1699 | |
1700 | regulator_bulk_set_supply_names(consumers: tegra->supplies, |
1701 | supply_names: tegra->soc->supply_names, |
1702 | num_supplies: tegra->soc->num_supplies); |
1703 | |
1704 | err = devm_regulator_bulk_get(dev: &pdev->dev, num_consumers: tegra->soc->num_supplies, |
1705 | consumers: tegra->supplies); |
1706 | if (err) { |
1707 | dev_err(&pdev->dev, "failed to get regulators: %d\n" , err); |
1708 | goto put_powerdomains; |
1709 | } |
1710 | |
1711 | for (i = 0; i < tegra->soc->num_types; i++) { |
1712 | if (!strncmp(tegra->soc->phy_types[i].name, "usb2" , 4)) |
1713 | tegra->num_usb_phys = tegra->soc->phy_types[i].num; |
1714 | tegra->num_phys += tegra->soc->phy_types[i].num; |
1715 | } |
1716 | |
1717 | tegra->phys = devm_kcalloc(dev: &pdev->dev, n: tegra->num_phys, |
1718 | size: sizeof(*tegra->phys), GFP_KERNEL); |
1719 | if (!tegra->phys) { |
1720 | err = -ENOMEM; |
1721 | goto put_powerdomains; |
1722 | } |
1723 | |
1724 | for (i = 0, k = 0; i < tegra->soc->num_types; i++) { |
1725 | char prop[8]; |
1726 | |
1727 | for (j = 0; j < tegra->soc->phy_types[i].num; j++) { |
1728 | snprintf(buf: prop, size: sizeof(prop), fmt: "%s-%d" , |
1729 | tegra->soc->phy_types[i].name, j); |
1730 | |
1731 | phy = devm_phy_optional_get(dev: &pdev->dev, string: prop); |
1732 | if (IS_ERR(ptr: phy)) { |
1733 | dev_err(&pdev->dev, |
1734 | "failed to get PHY %s: %ld\n" , prop, |
1735 | PTR_ERR(phy)); |
1736 | err = PTR_ERR(ptr: phy); |
1737 | goto put_powerdomains; |
1738 | } |
1739 | |
1740 | tegra->phys[k++] = phy; |
1741 | } |
1742 | } |
1743 | |
1744 | tegra->hcd = usb_create_hcd(driver: &tegra_xhci_hc_driver, dev: &pdev->dev, |
1745 | bus_name: dev_name(dev: &pdev->dev)); |
1746 | if (!tegra->hcd) { |
1747 | err = -ENOMEM; |
1748 | goto put_powerdomains; |
1749 | } |
1750 | |
1751 | tegra->hcd->skip_phy_initialization = 1; |
1752 | tegra->hcd->regs = tegra->regs; |
1753 | tegra->hcd->rsrc_start = regs->start; |
1754 | tegra->hcd->rsrc_len = resource_size(res: regs); |
1755 | |
1756 | /* |
1757 | * This must happen after usb_create_hcd(), because usb_create_hcd() |
1758 | * will overwrite the drvdata of the device with the hcd it creates. |
1759 | */ |
1760 | platform_set_drvdata(pdev, data: tegra); |
1761 | |
1762 | err = tegra_xusb_clk_enable(tegra); |
1763 | if (err) { |
1764 | dev_err(tegra->dev, "failed to enable clocks: %d\n" , err); |
1765 | goto put_hcd; |
1766 | } |
1767 | |
1768 | err = regulator_bulk_enable(num_consumers: tegra->soc->num_supplies, consumers: tegra->supplies); |
1769 | if (err) { |
1770 | dev_err(tegra->dev, "failed to enable regulators: %d\n" , err); |
1771 | goto disable_clk; |
1772 | } |
1773 | |
1774 | err = tegra_xusb_phy_enable(tegra); |
1775 | if (err < 0) { |
1776 | dev_err(&pdev->dev, "failed to enable PHYs: %d\n" , err); |
1777 | goto disable_regulator; |
1778 | } |
1779 | |
1780 | /* |
1781 | * The XUSB Falcon microcontroller can only address 40 bits, so set |
1782 | * the DMA mask accordingly. |
1783 | */ |
1784 | err = dma_set_mask_and_coherent(dev: tegra->dev, DMA_BIT_MASK(40)); |
1785 | if (err < 0) { |
1786 | dev_err(&pdev->dev, "failed to set DMA mask: %d\n" , err); |
1787 | goto disable_phy; |
1788 | } |
1789 | |
1790 | if (tegra->soc->firmware) { |
1791 | err = tegra_xusb_request_firmware(tegra); |
1792 | if (err < 0) { |
1793 | dev_err(&pdev->dev, |
1794 | "failed to request firmware: %d\n" , err); |
1795 | goto disable_phy; |
1796 | } |
1797 | } |
1798 | |
1799 | err = tegra_xusb_unpowergate_partitions(tegra); |
1800 | if (err) |
1801 | goto free_firmware; |
1802 | |
1803 | tegra_xusb_config(tegra); |
1804 | |
1805 | err = tegra_xusb_load_firmware(tegra); |
1806 | if (err < 0) { |
1807 | dev_err(&pdev->dev, "failed to load firmware: %d\n" , err); |
1808 | goto powergate; |
1809 | } |
1810 | |
1811 | err = usb_add_hcd(hcd: tegra->hcd, irqnum: tegra->xhci_irq, IRQF_SHARED); |
1812 | if (err < 0) { |
1813 | dev_err(&pdev->dev, "failed to add USB HCD: %d\n" , err); |
1814 | goto powergate; |
1815 | } |
1816 | |
1817 | device_wakeup_enable(dev: tegra->hcd->self.controller); |
1818 | |
1819 | xhci = hcd_to_xhci(hcd: tegra->hcd); |
1820 | |
1821 | xhci->shared_hcd = usb_create_shared_hcd(driver: &tegra_xhci_hc_driver, |
1822 | dev: &pdev->dev, |
1823 | bus_name: dev_name(dev: &pdev->dev), |
1824 | shared_hcd: tegra->hcd); |
1825 | if (!xhci->shared_hcd) { |
1826 | dev_err(&pdev->dev, "failed to create shared HCD\n" ); |
1827 | err = -ENOMEM; |
1828 | goto remove_usb2; |
1829 | } |
1830 | |
1831 | if (HCC_MAX_PSA(xhci->hcc_params) >= 4) |
1832 | xhci->shared_hcd->can_do_streams = 1; |
1833 | |
1834 | err = usb_add_hcd(hcd: xhci->shared_hcd, irqnum: tegra->xhci_irq, IRQF_SHARED); |
1835 | if (err < 0) { |
1836 | dev_err(&pdev->dev, "failed to add shared HCD: %d\n" , err); |
1837 | goto put_usb3; |
1838 | } |
1839 | |
1840 | err = devm_request_threaded_irq(dev: &pdev->dev, irq: tegra->mbox_irq, |
1841 | handler: tegra_xusb_mbox_irq, |
1842 | thread_fn: tegra_xusb_mbox_thread, irqflags: 0, |
1843 | devname: dev_name(dev: &pdev->dev), dev_id: tegra); |
1844 | if (err < 0) { |
1845 | dev_err(&pdev->dev, "failed to request IRQ: %d\n" , err); |
1846 | goto remove_usb3; |
1847 | } |
1848 | |
1849 | if (tegra->padctl_irq) { |
1850 | err = devm_request_threaded_irq(dev: &pdev->dev, irq: tegra->padctl_irq, |
1851 | NULL, thread_fn: tegra_xusb_padctl_irq, |
1852 | IRQF_ONESHOT, devname: dev_name(dev: &pdev->dev), |
1853 | dev_id: tegra); |
1854 | if (err < 0) { |
1855 | dev_err(&pdev->dev, "failed to request padctl IRQ: %d\n" , err); |
1856 | goto remove_usb3; |
1857 | } |
1858 | } |
1859 | |
1860 | err = tegra_xusb_enable_firmware_messages(tegra); |
1861 | if (err < 0) { |
1862 | dev_err(&pdev->dev, "failed to enable messages: %d\n" , err); |
1863 | goto remove_usb3; |
1864 | } |
1865 | |
1866 | err = tegra_xusb_init_usb_phy(tegra); |
1867 | if (err < 0) { |
1868 | dev_err(&pdev->dev, "failed to init USB PHY: %d\n" , err); |
1869 | goto remove_usb3; |
1870 | } |
1871 | |
1872 | /* Enable wake for both USB 2.0 and USB 3.0 roothubs */ |
1873 | device_init_wakeup(dev: &tegra->hcd->self.root_hub->dev, enable: true); |
1874 | device_init_wakeup(dev: &xhci->shared_hcd->self.root_hub->dev, enable: true); |
1875 | |
1876 | pm_runtime_use_autosuspend(dev: tegra->dev); |
1877 | pm_runtime_set_autosuspend_delay(dev: tegra->dev, delay: 2000); |
1878 | pm_runtime_mark_last_busy(dev: tegra->dev); |
1879 | pm_runtime_set_active(dev: tegra->dev); |
1880 | |
1881 | if (tegra->padctl_irq) { |
1882 | device_init_wakeup(dev: tegra->dev, enable: true); |
1883 | pm_runtime_enable(dev: tegra->dev); |
1884 | } |
1885 | |
1886 | return 0; |
1887 | |
1888 | remove_usb3: |
1889 | usb_remove_hcd(hcd: xhci->shared_hcd); |
1890 | put_usb3: |
1891 | usb_put_hcd(hcd: xhci->shared_hcd); |
1892 | remove_usb2: |
1893 | usb_remove_hcd(hcd: tegra->hcd); |
1894 | powergate: |
1895 | tegra_xusb_powergate_partitions(tegra); |
1896 | free_firmware: |
1897 | dma_free_coherent(dev: &pdev->dev, size: tegra->fw.size, cpu_addr: tegra->fw.virt, |
1898 | dma_handle: tegra->fw.phys); |
1899 | disable_phy: |
1900 | tegra_xusb_phy_disable(tegra); |
1901 | disable_regulator: |
1902 | regulator_bulk_disable(num_consumers: tegra->soc->num_supplies, consumers: tegra->supplies); |
1903 | disable_clk: |
1904 | tegra_xusb_clk_disable(tegra); |
1905 | put_hcd: |
1906 | usb_put_hcd(hcd: tegra->hcd); |
1907 | put_powerdomains: |
1908 | tegra_xusb_powerdomain_remove(dev: &pdev->dev, tegra); |
1909 | put_padctl: |
1910 | of_node_put(node: np); |
1911 | tegra_xusb_padctl_put(padctl: tegra->padctl); |
1912 | return err; |
1913 | } |
1914 | |
1915 | static void tegra_xusb_disable(struct tegra_xusb *tegra) |
1916 | { |
1917 | tegra_xusb_powergate_partitions(tegra); |
1918 | tegra_xusb_powerdomain_remove(dev: tegra->dev, tegra); |
1919 | tegra_xusb_phy_disable(tegra); |
1920 | tegra_xusb_clk_disable(tegra); |
1921 | regulator_bulk_disable(num_consumers: tegra->soc->num_supplies, consumers: tegra->supplies); |
1922 | } |
1923 | |
1924 | static void tegra_xusb_remove(struct platform_device *pdev) |
1925 | { |
1926 | struct tegra_xusb *tegra = platform_get_drvdata(pdev); |
1927 | struct xhci_hcd *xhci = hcd_to_xhci(hcd: tegra->hcd); |
1928 | |
1929 | tegra_xusb_deinit_usb_phy(tegra); |
1930 | |
1931 | pm_runtime_get_sync(dev: &pdev->dev); |
1932 | usb_remove_hcd(hcd: xhci->shared_hcd); |
1933 | usb_put_hcd(hcd: xhci->shared_hcd); |
1934 | xhci->shared_hcd = NULL; |
1935 | usb_remove_hcd(hcd: tegra->hcd); |
1936 | usb_put_hcd(hcd: tegra->hcd); |
1937 | |
1938 | dma_free_coherent(dev: &pdev->dev, size: tegra->fw.size, cpu_addr: tegra->fw.virt, |
1939 | dma_handle: tegra->fw.phys); |
1940 | |
1941 | if (tegra->padctl_irq) |
1942 | pm_runtime_disable(dev: &pdev->dev); |
1943 | |
1944 | pm_runtime_put(dev: &pdev->dev); |
1945 | |
1946 | tegra_xusb_disable(tegra); |
1947 | tegra_xusb_padctl_put(padctl: tegra->padctl); |
1948 | } |
1949 | |
1950 | static void tegra_xusb_shutdown(struct platform_device *pdev) |
1951 | { |
1952 | struct tegra_xusb *tegra = platform_get_drvdata(pdev); |
1953 | |
1954 | pm_runtime_get_sync(dev: &pdev->dev); |
1955 | disable_irq(irq: tegra->xhci_irq); |
1956 | xhci_shutdown(hcd: tegra->hcd); |
1957 | tegra_xusb_disable(tegra); |
1958 | } |
1959 | |
1960 | static bool xhci_hub_ports_suspended(struct xhci_hub *hub) |
1961 | { |
1962 | struct device *dev = hub->hcd->self.controller; |
1963 | bool status = true; |
1964 | unsigned int i; |
1965 | u32 value; |
1966 | |
1967 | for (i = 0; i < hub->num_ports; i++) { |
1968 | value = readl(addr: hub->ports[i]->addr); |
1969 | if ((value & PORT_PE) == 0) |
1970 | continue; |
1971 | |
1972 | if ((value & PORT_PLS_MASK) != XDEV_U3) { |
1973 | dev_info(dev, "%u-%u isn't suspended: %#010x\n" , |
1974 | hub->hcd->self.busnum, i + 1, value); |
1975 | status = false; |
1976 | } |
1977 | } |
1978 | |
1979 | return status; |
1980 | } |
1981 | |
1982 | static int tegra_xusb_check_ports(struct tegra_xusb *tegra) |
1983 | { |
1984 | struct xhci_hcd *xhci = hcd_to_xhci(hcd: tegra->hcd); |
1985 | struct xhci_bus_state *bus_state = &xhci->usb2_rhub.bus_state; |
1986 | unsigned long flags; |
1987 | int err = 0; |
1988 | |
1989 | if (bus_state->bus_suspended) { |
1990 | /* xusb_hub_suspend() has just directed one or more USB2 port(s) |
1991 | * to U3 state, it takes 3ms to enter U3. |
1992 | */ |
1993 | usleep_range(min: 3000, max: 4000); |
1994 | } |
1995 | |
1996 | spin_lock_irqsave(&xhci->lock, flags); |
1997 | |
1998 | if (!xhci_hub_ports_suspended(hub: &xhci->usb2_rhub) || |
1999 | !xhci_hub_ports_suspended(hub: &xhci->usb3_rhub)) |
2000 | err = -EBUSY; |
2001 | |
2002 | spin_unlock_irqrestore(lock: &xhci->lock, flags); |
2003 | |
2004 | return err; |
2005 | } |
2006 | |
2007 | static void tegra_xusb_save_context(struct tegra_xusb *tegra) |
2008 | { |
2009 | const struct tegra_xusb_context_soc *soc = tegra->soc->context; |
2010 | struct tegra_xusb_context *ctx = &tegra->context; |
2011 | unsigned int i; |
2012 | |
2013 | if (soc->ipfs.num_offsets > 0) { |
2014 | for (i = 0; i < soc->ipfs.num_offsets; i++) |
2015 | ctx->ipfs[i] = ipfs_readl(tegra, offset: soc->ipfs.offsets[i]); |
2016 | } |
2017 | |
2018 | if (soc->fpci.num_offsets > 0) { |
2019 | for (i = 0; i < soc->fpci.num_offsets; i++) |
2020 | ctx->fpci[i] = fpci_readl(tegra, offset: soc->fpci.offsets[i]); |
2021 | } |
2022 | } |
2023 | |
2024 | static void tegra_xusb_restore_context(struct tegra_xusb *tegra) |
2025 | { |
2026 | const struct tegra_xusb_context_soc *soc = tegra->soc->context; |
2027 | struct tegra_xusb_context *ctx = &tegra->context; |
2028 | unsigned int i; |
2029 | |
2030 | if (soc->fpci.num_offsets > 0) { |
2031 | for (i = 0; i < soc->fpci.num_offsets; i++) |
2032 | fpci_writel(tegra, value: ctx->fpci[i], offset: soc->fpci.offsets[i]); |
2033 | } |
2034 | |
2035 | if (soc->ipfs.num_offsets > 0) { |
2036 | for (i = 0; i < soc->ipfs.num_offsets; i++) |
2037 | ipfs_writel(tegra, value: ctx->ipfs[i], offset: soc->ipfs.offsets[i]); |
2038 | } |
2039 | } |
2040 | |
2041 | static enum usb_device_speed tegra_xhci_portsc_to_speed(struct tegra_xusb *tegra, u32 portsc) |
2042 | { |
2043 | if (DEV_LOWSPEED(portsc)) |
2044 | return USB_SPEED_LOW; |
2045 | |
2046 | if (DEV_HIGHSPEED(portsc)) |
2047 | return USB_SPEED_HIGH; |
2048 | |
2049 | if (DEV_FULLSPEED(portsc)) |
2050 | return USB_SPEED_FULL; |
2051 | |
2052 | if (DEV_SUPERSPEED_ANY(portsc)) |
2053 | return USB_SPEED_SUPER; |
2054 | |
2055 | return USB_SPEED_UNKNOWN; |
2056 | } |
2057 | |
2058 | static void tegra_xhci_enable_phy_sleepwalk_wake(struct tegra_xusb *tegra) |
2059 | { |
2060 | struct tegra_xusb_padctl *padctl = tegra->padctl; |
2061 | struct xhci_hcd *xhci = hcd_to_xhci(hcd: tegra->hcd); |
2062 | enum usb_device_speed speed; |
2063 | struct phy *phy; |
2064 | unsigned int index, offset; |
2065 | unsigned int i, j, k; |
2066 | struct xhci_hub *rhub; |
2067 | u32 portsc; |
2068 | |
2069 | for (i = 0, k = 0; i < tegra->soc->num_types; i++) { |
2070 | if (strcmp(tegra->soc->phy_types[i].name, "usb3" ) == 0) |
2071 | rhub = &xhci->usb3_rhub; |
2072 | else |
2073 | rhub = &xhci->usb2_rhub; |
2074 | |
2075 | if (strcmp(tegra->soc->phy_types[i].name, "hsic" ) == 0) |
2076 | offset = tegra->soc->ports.usb2.count; |
2077 | else |
2078 | offset = 0; |
2079 | |
2080 | for (j = 0; j < tegra->soc->phy_types[i].num; j++) { |
2081 | phy = tegra->phys[k++]; |
2082 | |
2083 | if (!phy) |
2084 | continue; |
2085 | |
2086 | index = j + offset; |
2087 | |
2088 | if (index >= rhub->num_ports) |
2089 | continue; |
2090 | |
2091 | if (!is_host_mode_phy(tegra, phy_type: i, index: j)) |
2092 | continue; |
2093 | |
2094 | portsc = readl(addr: rhub->ports[index]->addr); |
2095 | speed = tegra_xhci_portsc_to_speed(tegra, portsc); |
2096 | tegra_xusb_padctl_enable_phy_sleepwalk(padctl, phy, speed); |
2097 | tegra_xusb_padctl_enable_phy_wake(padctl, phy); |
2098 | } |
2099 | } |
2100 | } |
2101 | |
2102 | static void tegra_xhci_disable_phy_wake(struct tegra_xusb *tegra) |
2103 | { |
2104 | struct tegra_xusb_padctl *padctl = tegra->padctl; |
2105 | unsigned int i; |
2106 | |
2107 | for (i = 0; i < tegra->num_usb_phys; i++) { |
2108 | struct phy *phy = tegra_xusb_get_phy(tegra, name: "usb2" , port: i); |
2109 | |
2110 | if (!phy) |
2111 | continue; |
2112 | |
2113 | if (tegra_xusb_padctl_remote_wake_detected(padctl, phy)) |
2114 | tegra_phy_xusb_utmi_pad_power_on(phy); |
2115 | } |
2116 | |
2117 | for (i = 0; i < tegra->num_phys; i++) { |
2118 | if (!tegra->phys[i]) |
2119 | continue; |
2120 | |
2121 | if (tegra_xusb_padctl_remote_wake_detected(padctl, phy: tegra->phys[i])) |
2122 | dev_dbg(tegra->dev, "%pOF remote wake detected\n" , |
2123 | tegra->phys[i]->dev.of_node); |
2124 | |
2125 | tegra_xusb_padctl_disable_phy_wake(padctl, phy: tegra->phys[i]); |
2126 | } |
2127 | } |
2128 | |
2129 | static void tegra_xhci_disable_phy_sleepwalk(struct tegra_xusb *tegra) |
2130 | { |
2131 | struct tegra_xusb_padctl *padctl = tegra->padctl; |
2132 | unsigned int i; |
2133 | |
2134 | for (i = 0; i < tegra->num_phys; i++) { |
2135 | if (!tegra->phys[i]) |
2136 | continue; |
2137 | |
2138 | tegra_xusb_padctl_disable_phy_sleepwalk(padctl, phy: tegra->phys[i]); |
2139 | } |
2140 | } |
2141 | |
2142 | static void tegra_xhci_program_utmi_power_lp0_exit(struct tegra_xusb *tegra) |
2143 | { |
2144 | unsigned int i, index_to_usb2; |
2145 | struct phy *phy; |
2146 | |
2147 | for (i = 0; i < tegra->soc->num_types; i++) { |
2148 | if (strcmp(tegra->soc->phy_types[i].name, "usb2" ) == 0) |
2149 | index_to_usb2 = i; |
2150 | } |
2151 | |
2152 | for (i = 0; i < tegra->num_usb_phys; i++) { |
2153 | if (!is_host_mode_phy(tegra, phy_type: index_to_usb2, index: i)) |
2154 | continue; |
2155 | |
2156 | phy = tegra_xusb_get_phy(tegra, name: "usb2" , port: i); |
2157 | if (tegra->lp0_utmi_pad_mask & BIT(i)) |
2158 | tegra_phy_xusb_utmi_pad_power_on(phy); |
2159 | else |
2160 | tegra_phy_xusb_utmi_pad_power_down(phy); |
2161 | } |
2162 | } |
2163 | |
2164 | static int tegra_xusb_enter_elpg(struct tegra_xusb *tegra, bool runtime) |
2165 | { |
2166 | struct xhci_hcd *xhci = hcd_to_xhci(hcd: tegra->hcd); |
2167 | struct device *dev = tegra->dev; |
2168 | bool wakeup = runtime ? true : device_may_wakeup(dev); |
2169 | unsigned int i; |
2170 | int err; |
2171 | u32 usbcmd; |
2172 | u32 portsc; |
2173 | |
2174 | dev_dbg(dev, "entering ELPG\n" ); |
2175 | |
2176 | usbcmd = readl(addr: &xhci->op_regs->command); |
2177 | usbcmd &= ~CMD_EIE; |
2178 | writel(val: usbcmd, addr: &xhci->op_regs->command); |
2179 | |
2180 | err = tegra_xusb_check_ports(tegra); |
2181 | if (err < 0) { |
2182 | dev_err(tegra->dev, "not all ports suspended: %d\n" , err); |
2183 | goto out; |
2184 | } |
2185 | |
2186 | for (i = 0; i < tegra->num_usb_phys; i++) { |
2187 | if (!xhci->usb2_rhub.ports[i]) |
2188 | continue; |
2189 | portsc = readl(addr: xhci->usb2_rhub.ports[i]->addr); |
2190 | tegra->lp0_utmi_pad_mask &= ~BIT(i); |
2191 | if (((portsc & PORT_PLS_MASK) == XDEV_U3) || ((portsc & DEV_SPEED_MASK) == XDEV_FS)) |
2192 | tegra->lp0_utmi_pad_mask |= BIT(i); |
2193 | } |
2194 | |
2195 | err = xhci_suspend(xhci, do_wakeup: wakeup); |
2196 | if (err < 0) { |
2197 | dev_err(tegra->dev, "failed to suspend XHCI: %d\n" , err); |
2198 | goto out; |
2199 | } |
2200 | |
2201 | tegra_xusb_save_context(tegra); |
2202 | |
2203 | if (wakeup) |
2204 | tegra_xhci_enable_phy_sleepwalk_wake(tegra); |
2205 | |
2206 | tegra_xusb_powergate_partitions(tegra); |
2207 | |
2208 | for (i = 0; i < tegra->num_phys; i++) { |
2209 | if (!tegra->phys[i]) |
2210 | continue; |
2211 | |
2212 | phy_power_off(phy: tegra->phys[i]); |
2213 | if (!wakeup) |
2214 | phy_exit(phy: tegra->phys[i]); |
2215 | } |
2216 | |
2217 | tegra_xusb_clk_disable(tegra); |
2218 | |
2219 | out: |
2220 | if (!err) |
2221 | dev_dbg(tegra->dev, "entering ELPG done\n" ); |
2222 | else { |
2223 | usbcmd = readl(addr: &xhci->op_regs->command); |
2224 | usbcmd |= CMD_EIE; |
2225 | writel(val: usbcmd, addr: &xhci->op_regs->command); |
2226 | |
2227 | dev_dbg(tegra->dev, "entering ELPG failed\n" ); |
2228 | pm_runtime_mark_last_busy(dev: tegra->dev); |
2229 | } |
2230 | |
2231 | return err; |
2232 | } |
2233 | |
2234 | static int tegra_xusb_exit_elpg(struct tegra_xusb *tegra, bool runtime) |
2235 | { |
2236 | struct xhci_hcd *xhci = hcd_to_xhci(hcd: tegra->hcd); |
2237 | struct device *dev = tegra->dev; |
2238 | bool wakeup = runtime ? true : device_may_wakeup(dev); |
2239 | unsigned int i; |
2240 | u32 usbcmd; |
2241 | int err; |
2242 | |
2243 | dev_dbg(dev, "exiting ELPG\n" ); |
2244 | pm_runtime_mark_last_busy(dev: tegra->dev); |
2245 | |
2246 | err = tegra_xusb_clk_enable(tegra); |
2247 | if (err < 0) { |
2248 | dev_err(tegra->dev, "failed to enable clocks: %d\n" , err); |
2249 | goto out; |
2250 | } |
2251 | |
2252 | err = tegra_xusb_unpowergate_partitions(tegra); |
2253 | if (err) |
2254 | goto disable_clks; |
2255 | |
2256 | if (wakeup) |
2257 | tegra_xhci_disable_phy_wake(tegra); |
2258 | |
2259 | for (i = 0; i < tegra->num_phys; i++) { |
2260 | if (!tegra->phys[i]) |
2261 | continue; |
2262 | |
2263 | if (!wakeup) |
2264 | phy_init(phy: tegra->phys[i]); |
2265 | |
2266 | phy_power_on(phy: tegra->phys[i]); |
2267 | } |
2268 | if (tegra->suspended) |
2269 | tegra_xhci_program_utmi_power_lp0_exit(tegra); |
2270 | |
2271 | tegra_xusb_config(tegra); |
2272 | tegra_xusb_restore_context(tegra); |
2273 | |
2274 | err = tegra_xusb_load_firmware(tegra); |
2275 | if (err < 0) { |
2276 | dev_err(tegra->dev, "failed to load firmware: %d\n" , err); |
2277 | goto disable_phy; |
2278 | } |
2279 | |
2280 | err = __tegra_xusb_enable_firmware_messages(tegra); |
2281 | if (err < 0) { |
2282 | dev_err(tegra->dev, "failed to enable messages: %d\n" , err); |
2283 | goto disable_phy; |
2284 | } |
2285 | |
2286 | if (wakeup) |
2287 | tegra_xhci_disable_phy_sleepwalk(tegra); |
2288 | |
2289 | err = xhci_resume(xhci, msg: runtime ? PMSG_AUTO_RESUME : PMSG_RESUME); |
2290 | if (err < 0) { |
2291 | dev_err(tegra->dev, "failed to resume XHCI: %d\n" , err); |
2292 | goto disable_phy; |
2293 | } |
2294 | |
2295 | usbcmd = readl(addr: &xhci->op_regs->command); |
2296 | usbcmd |= CMD_EIE; |
2297 | writel(val: usbcmd, addr: &xhci->op_regs->command); |
2298 | |
2299 | goto out; |
2300 | |
2301 | disable_phy: |
2302 | for (i = 0; i < tegra->num_phys; i++) { |
2303 | if (!tegra->phys[i]) |
2304 | continue; |
2305 | |
2306 | phy_power_off(phy: tegra->phys[i]); |
2307 | if (!wakeup) |
2308 | phy_exit(phy: tegra->phys[i]); |
2309 | } |
2310 | tegra_xusb_powergate_partitions(tegra); |
2311 | disable_clks: |
2312 | tegra_xusb_clk_disable(tegra); |
2313 | out: |
2314 | if (!err) |
2315 | dev_dbg(dev, "exiting ELPG done\n" ); |
2316 | else |
2317 | dev_dbg(dev, "exiting ELPG failed\n" ); |
2318 | |
2319 | return err; |
2320 | } |
2321 | |
2322 | static __maybe_unused int tegra_xusb_suspend(struct device *dev) |
2323 | { |
2324 | struct tegra_xusb *tegra = dev_get_drvdata(dev); |
2325 | int err; |
2326 | |
2327 | synchronize_irq(irq: tegra->mbox_irq); |
2328 | |
2329 | mutex_lock(&tegra->lock); |
2330 | |
2331 | if (pm_runtime_suspended(dev)) { |
2332 | err = tegra_xusb_exit_elpg(tegra, runtime: true); |
2333 | if (err < 0) |
2334 | goto out; |
2335 | } |
2336 | |
2337 | err = tegra_xusb_enter_elpg(tegra, runtime: false); |
2338 | if (err < 0) { |
2339 | if (pm_runtime_suspended(dev)) { |
2340 | pm_runtime_disable(dev); |
2341 | pm_runtime_set_active(dev); |
2342 | pm_runtime_enable(dev); |
2343 | } |
2344 | |
2345 | goto out; |
2346 | } |
2347 | |
2348 | out: |
2349 | if (!err) { |
2350 | tegra->suspended = true; |
2351 | pm_runtime_disable(dev); |
2352 | |
2353 | if (device_may_wakeup(dev)) { |
2354 | if (enable_irq_wake(irq: tegra->padctl_irq)) |
2355 | dev_err(dev, "failed to enable padctl wakes\n" ); |
2356 | } |
2357 | } |
2358 | |
2359 | mutex_unlock(lock: &tegra->lock); |
2360 | |
2361 | return err; |
2362 | } |
2363 | |
2364 | static __maybe_unused int tegra_xusb_resume(struct device *dev) |
2365 | { |
2366 | struct tegra_xusb *tegra = dev_get_drvdata(dev); |
2367 | int err; |
2368 | |
2369 | mutex_lock(&tegra->lock); |
2370 | |
2371 | if (!tegra->suspended) { |
2372 | mutex_unlock(lock: &tegra->lock); |
2373 | return 0; |
2374 | } |
2375 | |
2376 | err = tegra_xusb_exit_elpg(tegra, runtime: false); |
2377 | if (err < 0) { |
2378 | mutex_unlock(lock: &tegra->lock); |
2379 | return err; |
2380 | } |
2381 | |
2382 | if (device_may_wakeup(dev)) { |
2383 | if (disable_irq_wake(irq: tegra->padctl_irq)) |
2384 | dev_err(dev, "failed to disable padctl wakes\n" ); |
2385 | } |
2386 | tegra->suspended = false; |
2387 | mutex_unlock(lock: &tegra->lock); |
2388 | |
2389 | pm_runtime_set_active(dev); |
2390 | pm_runtime_enable(dev); |
2391 | |
2392 | return 0; |
2393 | } |
2394 | |
2395 | static __maybe_unused int tegra_xusb_runtime_suspend(struct device *dev) |
2396 | { |
2397 | struct tegra_xusb *tegra = dev_get_drvdata(dev); |
2398 | int ret; |
2399 | |
2400 | synchronize_irq(irq: tegra->mbox_irq); |
2401 | mutex_lock(&tegra->lock); |
2402 | ret = tegra_xusb_enter_elpg(tegra, runtime: true); |
2403 | mutex_unlock(lock: &tegra->lock); |
2404 | |
2405 | return ret; |
2406 | } |
2407 | |
2408 | static __maybe_unused int tegra_xusb_runtime_resume(struct device *dev) |
2409 | { |
2410 | struct tegra_xusb *tegra = dev_get_drvdata(dev); |
2411 | int err; |
2412 | |
2413 | mutex_lock(&tegra->lock); |
2414 | err = tegra_xusb_exit_elpg(tegra, runtime: true); |
2415 | mutex_unlock(lock: &tegra->lock); |
2416 | |
2417 | return err; |
2418 | } |
2419 | |
2420 | static const struct dev_pm_ops tegra_xusb_pm_ops = { |
2421 | SET_RUNTIME_PM_OPS(tegra_xusb_runtime_suspend, |
2422 | tegra_xusb_runtime_resume, NULL) |
2423 | SET_SYSTEM_SLEEP_PM_OPS(tegra_xusb_suspend, tegra_xusb_resume) |
2424 | }; |
2425 | |
2426 | static const char * const tegra124_supply_names[] = { |
2427 | "avddio-pex" , |
2428 | "dvddio-pex" , |
2429 | "avdd-usb" , |
2430 | "hvdd-usb-ss" , |
2431 | }; |
2432 | |
2433 | static const struct tegra_xusb_phy_type tegra124_phy_types[] = { |
2434 | { .name = "usb3" , .num = 2, }, |
2435 | { .name = "usb2" , .num = 3, }, |
2436 | { .name = "hsic" , .num = 2, }, |
2437 | }; |
2438 | |
2439 | static const unsigned int tegra124_xusb_context_ipfs[] = { |
2440 | IPFS_XUSB_HOST_MSI_BAR_SZ_0, |
2441 | IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0, |
2442 | IPFS_XUSB_HOST_MSI_FPCI_BAR_ST_0, |
2443 | IPFS_XUSB_HOST_MSI_VEC0_0, |
2444 | IPFS_XUSB_HOST_MSI_EN_VEC0_0, |
2445 | IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0, |
2446 | IPFS_XUSB_HOST_INTR_MASK_0, |
2447 | IPFS_XUSB_HOST_INTR_ENABLE_0, |
2448 | IPFS_XUSB_HOST_UFPCI_CONFIG_0, |
2449 | IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0, |
2450 | IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0, |
2451 | }; |
2452 | |
2453 | static const unsigned int tegra124_xusb_context_fpci[] = { |
2454 | XUSB_CFG_ARU_CONTEXT_HS_PLS, |
2455 | XUSB_CFG_ARU_CONTEXT_FS_PLS, |
2456 | XUSB_CFG_ARU_CONTEXT_HSFS_SPEED, |
2457 | XUSB_CFG_ARU_CONTEXT_HSFS_PP, |
2458 | XUSB_CFG_ARU_CONTEXT, |
2459 | XUSB_CFG_AXI_CFG, |
2460 | XUSB_CFG_24, |
2461 | XUSB_CFG_16, |
2462 | }; |
2463 | |
2464 | static const struct tegra_xusb_context_soc tegra124_xusb_context = { |
2465 | .ipfs = { |
2466 | .num_offsets = ARRAY_SIZE(tegra124_xusb_context_ipfs), |
2467 | .offsets = tegra124_xusb_context_ipfs, |
2468 | }, |
2469 | .fpci = { |
2470 | .num_offsets = ARRAY_SIZE(tegra124_xusb_context_fpci), |
2471 | .offsets = tegra124_xusb_context_fpci, |
2472 | }, |
2473 | }; |
2474 | |
2475 | static const struct tegra_xusb_soc_ops tegra124_ops = { |
2476 | .mbox_reg_readl = &fpci_readl, |
2477 | .mbox_reg_writel = &fpci_writel, |
2478 | .csb_reg_readl = &fpci_csb_readl, |
2479 | .csb_reg_writel = &fpci_csb_writel, |
2480 | }; |
2481 | |
2482 | static const struct tegra_xusb_soc tegra124_soc = { |
2483 | .firmware = "nvidia/tegra124/xusb.bin" , |
2484 | .supply_names = tegra124_supply_names, |
2485 | .num_supplies = ARRAY_SIZE(tegra124_supply_names), |
2486 | .phy_types = tegra124_phy_types, |
2487 | .num_types = ARRAY_SIZE(tegra124_phy_types), |
2488 | .context = &tegra124_xusb_context, |
2489 | .ports = { |
2490 | .usb2 = { .offset = 4, .count = 4, }, |
2491 | .hsic = { .offset = 6, .count = 2, }, |
2492 | .usb3 = { .offset = 0, .count = 2, }, |
2493 | }, |
2494 | .scale_ss_clock = true, |
2495 | .has_ipfs = true, |
2496 | .otg_reset_sspi = false, |
2497 | .ops = &tegra124_ops, |
2498 | .mbox = { |
2499 | .cmd = 0xe4, |
2500 | .data_in = 0xe8, |
2501 | .data_out = 0xec, |
2502 | .owner = 0xf0, |
2503 | .smi_intr = XUSB_CFG_ARU_SMI_INTR, |
2504 | }, |
2505 | }; |
2506 | MODULE_FIRMWARE("nvidia/tegra124/xusb.bin" ); |
2507 | |
2508 | static const char * const tegra210_supply_names[] = { |
2509 | "dvddio-pex" , |
2510 | "hvddio-pex" , |
2511 | "avdd-usb" , |
2512 | }; |
2513 | |
2514 | static const struct tegra_xusb_phy_type tegra210_phy_types[] = { |
2515 | { .name = "usb3" , .num = 4, }, |
2516 | { .name = "usb2" , .num = 4, }, |
2517 | { .name = "hsic" , .num = 1, }, |
2518 | }; |
2519 | |
2520 | static const struct tegra_xusb_soc tegra210_soc = { |
2521 | .firmware = "nvidia/tegra210/xusb.bin" , |
2522 | .supply_names = tegra210_supply_names, |
2523 | .num_supplies = ARRAY_SIZE(tegra210_supply_names), |
2524 | .phy_types = tegra210_phy_types, |
2525 | .num_types = ARRAY_SIZE(tegra210_phy_types), |
2526 | .context = &tegra124_xusb_context, |
2527 | .ports = { |
2528 | .usb2 = { .offset = 4, .count = 4, }, |
2529 | .hsic = { .offset = 8, .count = 1, }, |
2530 | .usb3 = { .offset = 0, .count = 4, }, |
2531 | }, |
2532 | .scale_ss_clock = false, |
2533 | .has_ipfs = true, |
2534 | .otg_reset_sspi = true, |
2535 | .ops = &tegra124_ops, |
2536 | .mbox = { |
2537 | .cmd = 0xe4, |
2538 | .data_in = 0xe8, |
2539 | .data_out = 0xec, |
2540 | .owner = 0xf0, |
2541 | .smi_intr = XUSB_CFG_ARU_SMI_INTR, |
2542 | }, |
2543 | }; |
2544 | MODULE_FIRMWARE("nvidia/tegra210/xusb.bin" ); |
2545 | |
2546 | static const char * const tegra186_supply_names[] = { |
2547 | }; |
2548 | MODULE_FIRMWARE("nvidia/tegra186/xusb.bin" ); |
2549 | |
2550 | static const struct tegra_xusb_phy_type tegra186_phy_types[] = { |
2551 | { .name = "usb3" , .num = 3, }, |
2552 | { .name = "usb2" , .num = 3, }, |
2553 | { .name = "hsic" , .num = 1, }, |
2554 | }; |
2555 | |
2556 | static const struct tegra_xusb_context_soc tegra186_xusb_context = { |
2557 | .fpci = { |
2558 | .num_offsets = ARRAY_SIZE(tegra124_xusb_context_fpci), |
2559 | .offsets = tegra124_xusb_context_fpci, |
2560 | }, |
2561 | }; |
2562 | |
2563 | static const struct tegra_xusb_soc tegra186_soc = { |
2564 | .firmware = "nvidia/tegra186/xusb.bin" , |
2565 | .supply_names = tegra186_supply_names, |
2566 | .num_supplies = ARRAY_SIZE(tegra186_supply_names), |
2567 | .phy_types = tegra186_phy_types, |
2568 | .num_types = ARRAY_SIZE(tegra186_phy_types), |
2569 | .context = &tegra186_xusb_context, |
2570 | .ports = { |
2571 | .usb3 = { .offset = 0, .count = 3, }, |
2572 | .usb2 = { .offset = 3, .count = 3, }, |
2573 | .hsic = { .offset = 6, .count = 1, }, |
2574 | }, |
2575 | .scale_ss_clock = false, |
2576 | .has_ipfs = false, |
2577 | .otg_reset_sspi = false, |
2578 | .ops = &tegra124_ops, |
2579 | .mbox = { |
2580 | .cmd = 0xe4, |
2581 | .data_in = 0xe8, |
2582 | .data_out = 0xec, |
2583 | .owner = 0xf0, |
2584 | .smi_intr = XUSB_CFG_ARU_SMI_INTR, |
2585 | }, |
2586 | .lpm_support = true, |
2587 | }; |
2588 | |
2589 | static const char * const tegra194_supply_names[] = { |
2590 | }; |
2591 | |
2592 | static const struct tegra_xusb_phy_type tegra194_phy_types[] = { |
2593 | { .name = "usb3" , .num = 4, }, |
2594 | { .name = "usb2" , .num = 4, }, |
2595 | }; |
2596 | |
2597 | static const struct tegra_xusb_soc tegra194_soc = { |
2598 | .firmware = "nvidia/tegra194/xusb.bin" , |
2599 | .supply_names = tegra194_supply_names, |
2600 | .num_supplies = ARRAY_SIZE(tegra194_supply_names), |
2601 | .phy_types = tegra194_phy_types, |
2602 | .num_types = ARRAY_SIZE(tegra194_phy_types), |
2603 | .context = &tegra186_xusb_context, |
2604 | .ports = { |
2605 | .usb3 = { .offset = 0, .count = 4, }, |
2606 | .usb2 = { .offset = 4, .count = 4, }, |
2607 | }, |
2608 | .scale_ss_clock = false, |
2609 | .has_ipfs = false, |
2610 | .otg_reset_sspi = false, |
2611 | .ops = &tegra124_ops, |
2612 | .mbox = { |
2613 | .cmd = 0x68, |
2614 | .data_in = 0x6c, |
2615 | .data_out = 0x70, |
2616 | .owner = 0x74, |
2617 | .smi_intr = XUSB_CFG_ARU_SMI_INTR, |
2618 | }, |
2619 | .lpm_support = true, |
2620 | }; |
2621 | MODULE_FIRMWARE("nvidia/tegra194/xusb.bin" ); |
2622 | |
2623 | static const struct tegra_xusb_soc_ops tegra234_ops = { |
2624 | .mbox_reg_readl = &bar2_readl, |
2625 | .mbox_reg_writel = &bar2_writel, |
2626 | .csb_reg_readl = &bar2_csb_readl, |
2627 | .csb_reg_writel = &bar2_csb_writel, |
2628 | }; |
2629 | |
2630 | static const struct tegra_xusb_soc tegra234_soc = { |
2631 | .supply_names = tegra194_supply_names, |
2632 | .num_supplies = ARRAY_SIZE(tegra194_supply_names), |
2633 | .phy_types = tegra194_phy_types, |
2634 | .num_types = ARRAY_SIZE(tegra194_phy_types), |
2635 | .context = &tegra186_xusb_context, |
2636 | .ports = { |
2637 | .usb3 = { .offset = 0, .count = 4, }, |
2638 | .usb2 = { .offset = 4, .count = 4, }, |
2639 | }, |
2640 | .scale_ss_clock = false, |
2641 | .has_ipfs = false, |
2642 | .otg_reset_sspi = false, |
2643 | .ops = &tegra234_ops, |
2644 | .mbox = { |
2645 | .cmd = XUSB_BAR2_ARU_MBOX_CMD, |
2646 | .data_in = XUSB_BAR2_ARU_MBOX_DATA_IN, |
2647 | .data_out = XUSB_BAR2_ARU_MBOX_DATA_OUT, |
2648 | .owner = XUSB_BAR2_ARU_MBOX_OWNER, |
2649 | .smi_intr = XUSB_BAR2_ARU_SMI_INTR, |
2650 | }, |
2651 | .lpm_support = true, |
2652 | .has_bar2 = true, |
2653 | }; |
2654 | |
2655 | static const struct of_device_id tegra_xusb_of_match[] = { |
2656 | { .compatible = "nvidia,tegra124-xusb" , .data = &tegra124_soc }, |
2657 | { .compatible = "nvidia,tegra210-xusb" , .data = &tegra210_soc }, |
2658 | { .compatible = "nvidia,tegra186-xusb" , .data = &tegra186_soc }, |
2659 | { .compatible = "nvidia,tegra194-xusb" , .data = &tegra194_soc }, |
2660 | { .compatible = "nvidia,tegra234-xusb" , .data = &tegra234_soc }, |
2661 | { }, |
2662 | }; |
2663 | MODULE_DEVICE_TABLE(of, tegra_xusb_of_match); |
2664 | |
2665 | static struct platform_driver tegra_xusb_driver = { |
2666 | .probe = tegra_xusb_probe, |
2667 | .remove_new = tegra_xusb_remove, |
2668 | .shutdown = tegra_xusb_shutdown, |
2669 | .driver = { |
2670 | .name = "tegra-xusb" , |
2671 | .pm = &tegra_xusb_pm_ops, |
2672 | .of_match_table = tegra_xusb_of_match, |
2673 | }, |
2674 | }; |
2675 | |
2676 | static void tegra_xhci_quirks(struct device *dev, struct xhci_hcd *xhci) |
2677 | { |
2678 | struct tegra_xusb *tegra = dev_get_drvdata(dev); |
2679 | |
2680 | if (tegra && tegra->soc->lpm_support) |
2681 | xhci->quirks |= XHCI_LPM_SUPPORT; |
2682 | } |
2683 | |
2684 | static int tegra_xhci_setup(struct usb_hcd *hcd) |
2685 | { |
2686 | return xhci_gen_setup(hcd, get_quirks: tegra_xhci_quirks); |
2687 | } |
2688 | |
2689 | static int tegra_xhci_hub_control(struct usb_hcd *hcd, u16 type_req, u16 value, u16 index, |
2690 | char *buf, u16 length) |
2691 | { |
2692 | struct tegra_xusb *tegra = dev_get_drvdata(dev: hcd->self.controller); |
2693 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
2694 | struct xhci_hub *rhub; |
2695 | struct xhci_bus_state *bus_state; |
2696 | int port = (index & 0xff) - 1; |
2697 | unsigned int i; |
2698 | struct xhci_port **ports; |
2699 | u32 portsc; |
2700 | int ret; |
2701 | struct phy *phy; |
2702 | |
2703 | rhub = &xhci->usb2_rhub; |
2704 | bus_state = &rhub->bus_state; |
2705 | if (bus_state->resuming_ports && hcd->speed == HCD_USB2) { |
2706 | ports = rhub->ports; |
2707 | i = rhub->num_ports; |
2708 | while (i--) { |
2709 | if (!test_bit(i, &bus_state->resuming_ports)) |
2710 | continue; |
2711 | portsc = readl(addr: ports[i]->addr); |
2712 | if ((portsc & PORT_PLS_MASK) == XDEV_RESUME) |
2713 | tegra_phy_xusb_utmi_pad_power_on( |
2714 | phy: tegra_xusb_get_phy(tegra, name: "usb2" , port: (int) i)); |
2715 | } |
2716 | } |
2717 | |
2718 | if (hcd->speed == HCD_USB2) { |
2719 | phy = tegra_xusb_get_phy(tegra, name: "usb2" , port); |
2720 | if ((type_req == ClearPortFeature) && (value == USB_PORT_FEAT_SUSPEND)) { |
2721 | if (!index || index > rhub->num_ports) |
2722 | return -EPIPE; |
2723 | tegra_phy_xusb_utmi_pad_power_on(phy); |
2724 | } |
2725 | if ((type_req == SetPortFeature) && (value == USB_PORT_FEAT_RESET)) { |
2726 | if (!index || index > rhub->num_ports) |
2727 | return -EPIPE; |
2728 | ports = rhub->ports; |
2729 | portsc = readl(addr: ports[port]->addr); |
2730 | if (portsc & PORT_CONNECT) |
2731 | tegra_phy_xusb_utmi_pad_power_on(phy); |
2732 | } |
2733 | } |
2734 | |
2735 | ret = xhci_hub_control(hcd, typeReq: type_req, wValue: value, wIndex: index, buf, wLength: length); |
2736 | if (ret < 0) |
2737 | return ret; |
2738 | |
2739 | if (hcd->speed == HCD_USB2) { |
2740 | /* Use phy where we set previously */ |
2741 | if ((type_req == SetPortFeature) && (value == USB_PORT_FEAT_SUSPEND)) |
2742 | /* We don't suspend the PAD while HNP role swap happens on the OTG port */ |
2743 | if (!((hcd->self.otg_port == (port + 1)) && hcd->self.b_hnp_enable)) |
2744 | tegra_phy_xusb_utmi_pad_power_down(phy); |
2745 | |
2746 | if ((type_req == ClearPortFeature) && (value == USB_PORT_FEAT_C_CONNECTION)) { |
2747 | ports = rhub->ports; |
2748 | portsc = readl(addr: ports[port]->addr); |
2749 | if (!(portsc & PORT_CONNECT)) { |
2750 | /* We don't suspend the PAD while HNP role swap happens on the OTG |
2751 | * port |
2752 | */ |
2753 | if (!((hcd->self.otg_port == (port + 1)) && hcd->self.b_hnp_enable)) |
2754 | tegra_phy_xusb_utmi_pad_power_down(phy); |
2755 | } |
2756 | } |
2757 | if ((type_req == SetPortFeature) && (value == USB_PORT_FEAT_TEST)) |
2758 | tegra_phy_xusb_utmi_pad_power_on(phy); |
2759 | } |
2760 | |
2761 | return ret; |
2762 | } |
2763 | |
2764 | static const struct xhci_driver_overrides tegra_xhci_overrides __initconst = { |
2765 | .reset = tegra_xhci_setup, |
2766 | .hub_control = tegra_xhci_hub_control, |
2767 | }; |
2768 | |
2769 | static int __init tegra_xusb_init(void) |
2770 | { |
2771 | xhci_init_driver(drv: &tegra_xhci_hc_driver, over: &tegra_xhci_overrides); |
2772 | |
2773 | return platform_driver_register(&tegra_xusb_driver); |
2774 | } |
2775 | module_init(tegra_xusb_init); |
2776 | |
2777 | static void __exit tegra_xusb_exit(void) |
2778 | { |
2779 | platform_driver_unregister(&tegra_xusb_driver); |
2780 | } |
2781 | module_exit(tegra_xusb_exit); |
2782 | |
2783 | MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>" ); |
2784 | MODULE_DESCRIPTION("NVIDIA Tegra XUSB xHCI host-controller driver" ); |
2785 | MODULE_LICENSE("GPL v2" ); |
2786 | |