1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * MUSB OTG driver DMA controller abstraction |
4 | * |
5 | * Copyright 2005 Mentor Graphics Corporation |
6 | * Copyright (C) 2005-2006 by Texas Instruments |
7 | * Copyright (C) 2006-2007 Nokia Corporation |
8 | */ |
9 | |
10 | #ifndef __MUSB_DMA_H__ |
11 | #define __MUSB_DMA_H__ |
12 | |
13 | struct musb_hw_ep; |
14 | |
15 | /* |
16 | * DMA Controller Abstraction |
17 | * |
18 | * DMA Controllers are abstracted to allow use of a variety of different |
19 | * implementations of DMA, as allowed by the Inventra USB cores. On the |
20 | * host side, usbcore sets up the DMA mappings and flushes caches; on the |
21 | * peripheral side, the gadget controller driver does. Responsibilities |
22 | * of a DMA controller driver include: |
23 | * |
24 | * - Handling the details of moving multiple USB packets |
25 | * in cooperation with the Inventra USB core, including especially |
26 | * the correct RX side treatment of short packets and buffer-full |
27 | * states (both of which terminate transfers). |
28 | * |
29 | * - Knowing the correlation between dma channels and the |
30 | * Inventra core's local endpoint resources and data direction. |
31 | * |
32 | * - Maintaining a list of allocated/available channels. |
33 | * |
34 | * - Updating channel status on interrupts, |
35 | * whether shared with the Inventra core or separate. |
36 | */ |
37 | |
38 | #define MUSB_HSDMA_BASE 0x200 |
39 | #define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0) |
40 | #define MUSB_HSDMA_CONTROL 0x4 |
41 | #define MUSB_HSDMA_ADDRESS 0x8 |
42 | #define MUSB_HSDMA_COUNT 0xc |
43 | |
44 | #define DMA_ADDR_INVALID (~(dma_addr_t)0) |
45 | |
46 | #ifdef CONFIG_MUSB_PIO_ONLY |
47 | #define is_dma_capable() (0) |
48 | #else |
49 | #define is_dma_capable() (1) |
50 | #endif |
51 | |
52 | #ifdef CONFIG_USB_UX500_DMA |
53 | #define musb_dma_ux500(musb) (musb->ops->quirks & MUSB_DMA_UX500) |
54 | #else |
55 | #define musb_dma_ux500(musb) 0 |
56 | #endif |
57 | |
58 | #ifdef CONFIG_USB_TI_CPPI41_DMA |
59 | #define musb_dma_cppi41(musb) (musb->ops->quirks & MUSB_DMA_CPPI41) |
60 | #else |
61 | #define musb_dma_cppi41(musb) 0 |
62 | #endif |
63 | |
64 | #ifdef CONFIG_USB_TUSB_OMAP_DMA |
65 | #define tusb_dma_omap(musb) (musb->ops->quirks & MUSB_DMA_TUSB_OMAP) |
66 | #else |
67 | #define tusb_dma_omap(musb) 0 |
68 | #endif |
69 | |
70 | #ifdef CONFIG_USB_INVENTRA_DMA |
71 | #define musb_dma_inventra(musb) (musb->ops->quirks & MUSB_DMA_INVENTRA) |
72 | #else |
73 | #define musb_dma_inventra(musb) 0 |
74 | #endif |
75 | |
76 | #if defined(CONFIG_USB_TI_CPPI41_DMA) |
77 | #define is_cppi_enabled(musb) musb_dma_cppi41(musb) |
78 | #else |
79 | #define is_cppi_enabled(musb) 0 |
80 | #endif |
81 | |
82 | /* |
83 | * DMA channel status ... updated by the dma controller driver whenever that |
84 | * status changes, and protected by the overall controller spinlock. |
85 | */ |
86 | enum dma_channel_status { |
87 | /* unallocated */ |
88 | MUSB_DMA_STATUS_UNKNOWN, |
89 | /* allocated ... but not busy, no errors */ |
90 | MUSB_DMA_STATUS_FREE, |
91 | /* busy ... transactions are active */ |
92 | MUSB_DMA_STATUS_BUSY, |
93 | /* transaction(s) aborted due to ... dma or memory bus error */ |
94 | MUSB_DMA_STATUS_BUS_ABORT, |
95 | /* transaction(s) aborted due to ... core error or USB fault */ |
96 | MUSB_DMA_STATUS_CORE_ABORT |
97 | }; |
98 | |
99 | struct dma_controller; |
100 | |
101 | /** |
102 | * struct dma_channel - A DMA channel. |
103 | * @private_data: channel-private data |
104 | * @max_len: the maximum number of bytes the channel can move in one |
105 | * transaction (typically representing many USB maximum-sized packets) |
106 | * @actual_len: how many bytes have been transferred |
107 | * @status: current channel status (updated e.g. on interrupt) |
108 | * @desired_mode: true if mode 1 is desired; false if mode 0 is desired |
109 | * |
110 | * channels are associated with an endpoint for the duration of at least |
111 | * one usb transfer. |
112 | */ |
113 | struct dma_channel { |
114 | void *private_data; |
115 | /* FIXME not void* private_data, but a dma_controller * */ |
116 | size_t max_len; |
117 | size_t actual_len; |
118 | enum dma_channel_status status; |
119 | bool desired_mode; |
120 | bool rx_packet_done; |
121 | }; |
122 | |
123 | /* |
124 | * dma_channel_status - return status of dma channel |
125 | * @c: the channel |
126 | * |
127 | * Returns the software's view of the channel status. If that status is BUSY |
128 | * then it's possible that the hardware has completed (or aborted) a transfer, |
129 | * so the driver needs to update that status. |
130 | */ |
131 | static inline enum dma_channel_status |
132 | dma_channel_status(struct dma_channel *c) |
133 | { |
134 | return (is_dma_capable() && c) ? c->status : MUSB_DMA_STATUS_UNKNOWN; |
135 | } |
136 | |
137 | /** |
138 | * struct dma_controller - A DMA Controller. |
139 | * @musb: the usb controller |
140 | * @start: call this to start a DMA controller; |
141 | * return 0 on success, else negative errno |
142 | * @stop: call this to stop a DMA controller |
143 | * return 0 on success, else negative errno |
144 | * @channel_alloc: call this to allocate a DMA channel |
145 | * @channel_release: call this to release a DMA channel |
146 | * @channel_abort: call this to abort a pending DMA transaction, |
147 | * returning it to FREE (but allocated) state |
148 | * @dma_callback: invoked on DMA completion, useful to run platform |
149 | * code such IRQ acknowledgment. |
150 | * |
151 | * Controllers manage dma channels. |
152 | */ |
153 | struct dma_controller { |
154 | struct musb *musb; |
155 | struct dma_channel *(*channel_alloc)(struct dma_controller *, |
156 | struct musb_hw_ep *, u8 is_tx); |
157 | void (*channel_release)(struct dma_channel *); |
158 | int (*channel_program)(struct dma_channel *channel, |
159 | u16 maxpacket, u8 mode, |
160 | dma_addr_t dma_addr, |
161 | u32 length); |
162 | int (*channel_abort)(struct dma_channel *); |
163 | int (*is_compatible)(struct dma_channel *channel, |
164 | u16 maxpacket, |
165 | void *buf, u32 length); |
166 | void (*dma_callback)(struct dma_controller *); |
167 | }; |
168 | |
169 | /* called after channel_program(), may indicate a fault */ |
170 | extern void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit); |
171 | |
172 | #ifdef CONFIG_MUSB_PIO_ONLY |
173 | static inline struct dma_controller * |
174 | musb_dma_controller_create(struct musb *m, void __iomem *io) |
175 | { |
176 | return NULL; |
177 | } |
178 | |
179 | static inline void musb_dma_controller_destroy(struct dma_controller *d) { } |
180 | |
181 | #else |
182 | |
183 | extern struct dma_controller * |
184 | (*musb_dma_controller_create)(struct musb *, void __iomem *); |
185 | |
186 | extern void (*musb_dma_controller_destroy)(struct dma_controller *); |
187 | #endif |
188 | |
189 | /* Platform specific DMA functions */ |
190 | extern struct dma_controller * |
191 | musbhs_dma_controller_create(struct musb *musb, void __iomem *base); |
192 | extern void musbhs_dma_controller_destroy(struct dma_controller *c); |
193 | extern struct dma_controller * |
194 | musbhs_dma_controller_create_noirq(struct musb *musb, void __iomem *base); |
195 | extern irqreturn_t dma_controller_irq(int irq, void *private_data); |
196 | |
197 | extern struct dma_controller * |
198 | tusb_dma_controller_create(struct musb *musb, void __iomem *base); |
199 | extern void tusb_dma_controller_destroy(struct dma_controller *c); |
200 | |
201 | extern struct dma_controller * |
202 | cppi41_dma_controller_create(struct musb *musb, void __iomem *base); |
203 | extern void cppi41_dma_controller_destroy(struct dma_controller *c); |
204 | |
205 | extern struct dma_controller * |
206 | ux500_dma_controller_create(struct musb *musb, void __iomem *base); |
207 | extern void ux500_dma_controller_destroy(struct dma_controller *c); |
208 | |
209 | #endif /* __MUSB_DMA_H__ */ |
210 | |