1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * MUSB OTG driver register defines |
4 | * |
5 | * Copyright 2005 Mentor Graphics Corporation |
6 | * Copyright (C) 2005-2006 by Texas Instruments |
7 | * Copyright (C) 2006-2007 Nokia Corporation |
8 | */ |
9 | |
10 | #ifndef __MUSB_REGS_H__ |
11 | #define __MUSB_REGS_H__ |
12 | |
13 | #define MUSB_EP0_FIFOSIZE 64 /* This is non-configurable */ |
14 | |
15 | /* |
16 | * MUSB Register bits |
17 | */ |
18 | |
19 | /* POWER */ |
20 | #define MUSB_POWER_ISOUPDATE 0x80 |
21 | #define MUSB_POWER_SOFTCONN 0x40 |
22 | #define MUSB_POWER_HSENAB 0x20 |
23 | #define MUSB_POWER_HSMODE 0x10 |
24 | #define MUSB_POWER_RESET 0x08 |
25 | #define MUSB_POWER_RESUME 0x04 |
26 | #define MUSB_POWER_SUSPENDM 0x02 |
27 | #define MUSB_POWER_ENSUSPEND 0x01 |
28 | |
29 | /* INTRUSB */ |
30 | #define MUSB_INTR_SUSPEND 0x01 |
31 | #define MUSB_INTR_RESUME 0x02 |
32 | #define MUSB_INTR_RESET 0x04 |
33 | #define MUSB_INTR_BABBLE 0x04 |
34 | #define MUSB_INTR_SOF 0x08 |
35 | #define MUSB_INTR_CONNECT 0x10 |
36 | #define MUSB_INTR_DISCONNECT 0x20 |
37 | #define MUSB_INTR_SESSREQ 0x40 |
38 | #define MUSB_INTR_VBUSERROR 0x80 /* For SESSION end */ |
39 | |
40 | /* DEVCTL */ |
41 | #define MUSB_DEVCTL_BDEVICE 0x80 |
42 | #define MUSB_DEVCTL_FSDEV 0x40 |
43 | #define MUSB_DEVCTL_LSDEV 0x20 |
44 | #define MUSB_DEVCTL_VBUS 0x18 |
45 | #define MUSB_DEVCTL_VBUS_SHIFT 3 |
46 | #define MUSB_DEVCTL_HM 0x04 |
47 | #define MUSB_DEVCTL_HR 0x02 |
48 | #define MUSB_DEVCTL_SESSION 0x01 |
49 | |
50 | /* BABBLE_CTL */ |
51 | #define MUSB_BABBLE_FORCE_TXIDLE 0x80 |
52 | #define MUSB_BABBLE_SW_SESSION_CTRL 0x40 |
53 | #define MUSB_BABBLE_STUCK_J 0x20 |
54 | #define MUSB_BABBLE_RCV_DISABLE 0x04 |
55 | |
56 | /* MUSB ULPI VBUSCONTROL */ |
57 | #define MUSB_ULPI_USE_EXTVBUS 0x01 |
58 | #define MUSB_ULPI_USE_EXTVBUSIND 0x02 |
59 | /* ULPI_REG_CONTROL */ |
60 | #define MUSB_ULPI_REG_REQ (1 << 0) |
61 | #define MUSB_ULPI_REG_CMPLT (1 << 1) |
62 | #define MUSB_ULPI_RDN_WR (1 << 2) |
63 | |
64 | /* TESTMODE */ |
65 | #define MUSB_TEST_FORCE_HOST 0x80 |
66 | #define MUSB_TEST_FIFO_ACCESS 0x40 |
67 | #define MUSB_TEST_FORCE_FS 0x20 |
68 | #define MUSB_TEST_FORCE_HS 0x10 |
69 | #define MUSB_TEST_PACKET 0x08 |
70 | #define MUSB_TEST_K 0x04 |
71 | #define MUSB_TEST_J 0x02 |
72 | #define MUSB_TEST_SE0_NAK 0x01 |
73 | |
74 | /* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */ |
75 | #define MUSB_FIFOSZ_DPB 0x10 |
76 | /* Allocation size (8, 16, 32, ... 4096) */ |
77 | #define MUSB_FIFOSZ_SIZE 0x0f |
78 | |
79 | /* CSR0 */ |
80 | #define MUSB_CSR0_FLUSHFIFO 0x0100 |
81 | #define MUSB_CSR0_TXPKTRDY 0x0002 |
82 | #define MUSB_CSR0_RXPKTRDY 0x0001 |
83 | |
84 | /* CSR0 in Peripheral mode */ |
85 | #define MUSB_CSR0_P_SVDSETUPEND 0x0080 |
86 | #define MUSB_CSR0_P_SVDRXPKTRDY 0x0040 |
87 | #define MUSB_CSR0_P_SENDSTALL 0x0020 |
88 | #define MUSB_CSR0_P_SETUPEND 0x0010 |
89 | #define MUSB_CSR0_P_DATAEND 0x0008 |
90 | #define MUSB_CSR0_P_SENTSTALL 0x0004 |
91 | |
92 | /* CSR0 in Host mode */ |
93 | #define MUSB_CSR0_H_DIS_PING 0x0800 |
94 | #define MUSB_CSR0_H_WR_DATATOGGLE 0x0400 /* Set to allow setting: */ |
95 | #define MUSB_CSR0_H_DATATOGGLE 0x0200 /* Data toggle control */ |
96 | #define MUSB_CSR0_H_NAKTIMEOUT 0x0080 |
97 | #define MUSB_CSR0_H_STATUSPKT 0x0040 |
98 | #define MUSB_CSR0_H_REQPKT 0x0020 |
99 | #define MUSB_CSR0_H_ERROR 0x0010 |
100 | #define MUSB_CSR0_H_SETUPPKT 0x0008 |
101 | #define MUSB_CSR0_H_RXSTALL 0x0004 |
102 | |
103 | /* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */ |
104 | #define MUSB_CSR0_P_WZC_BITS \ |
105 | (MUSB_CSR0_P_SENTSTALL) |
106 | #define MUSB_CSR0_H_WZC_BITS \ |
107 | (MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \ |
108 | | MUSB_CSR0_RXPKTRDY) |
109 | |
110 | /* TxType/RxType */ |
111 | #define MUSB_TYPE_SPEED 0xc0 |
112 | #define MUSB_TYPE_SPEED_SHIFT 6 |
113 | #define MUSB_TYPE_PROTO 0x30 /* Implicitly zero for ep0 */ |
114 | #define MUSB_TYPE_PROTO_SHIFT 4 |
115 | #define MUSB_TYPE_REMOTE_END 0xf /* Implicitly zero for ep0 */ |
116 | |
117 | /* CONFIGDATA */ |
118 | #define MUSB_CONFIGDATA_MPRXE 0x80 /* Auto bulk pkt combining */ |
119 | #define MUSB_CONFIGDATA_MPTXE 0x40 /* Auto bulk pkt splitting */ |
120 | #define MUSB_CONFIGDATA_BIGENDIAN 0x20 |
121 | #define MUSB_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */ |
122 | #define MUSB_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */ |
123 | #define MUSB_CONFIGDATA_DYNFIFO 0x04 /* Dynamic FIFO sizing */ |
124 | #define MUSB_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */ |
125 | #define MUSB_CONFIGDATA_UTMIDW 0x01 /* Data width 0/1 => 8/16bits */ |
126 | |
127 | /* TXCSR in Peripheral and Host mode */ |
128 | #define MUSB_TXCSR_AUTOSET 0x8000 |
129 | #define MUSB_TXCSR_DMAENAB 0x1000 |
130 | #define MUSB_TXCSR_FRCDATATOG 0x0800 |
131 | #define MUSB_TXCSR_DMAMODE 0x0400 |
132 | #define MUSB_TXCSR_CLRDATATOG 0x0040 |
133 | #define MUSB_TXCSR_FLUSHFIFO 0x0008 |
134 | #define MUSB_TXCSR_FIFONOTEMPTY 0x0002 |
135 | #define MUSB_TXCSR_TXPKTRDY 0x0001 |
136 | |
137 | /* TXCSR in Peripheral mode */ |
138 | #define MUSB_TXCSR_P_ISO 0x4000 |
139 | #define MUSB_TXCSR_P_INCOMPTX 0x0080 |
140 | #define MUSB_TXCSR_P_SENTSTALL 0x0020 |
141 | #define MUSB_TXCSR_P_SENDSTALL 0x0010 |
142 | #define MUSB_TXCSR_P_UNDERRUN 0x0004 |
143 | |
144 | /* TXCSR in Host mode */ |
145 | #define MUSB_TXCSR_H_WR_DATATOGGLE 0x0200 |
146 | #define MUSB_TXCSR_H_DATATOGGLE 0x0100 |
147 | #define MUSB_TXCSR_H_NAKTIMEOUT 0x0080 |
148 | #define MUSB_TXCSR_H_RXSTALL 0x0020 |
149 | #define MUSB_TXCSR_H_ERROR 0x0004 |
150 | |
151 | /* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */ |
152 | #define MUSB_TXCSR_P_WZC_BITS \ |
153 | (MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \ |
154 | | MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY) |
155 | #define MUSB_TXCSR_H_WZC_BITS \ |
156 | (MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \ |
157 | | MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY) |
158 | |
159 | /* RXCSR in Peripheral and Host mode */ |
160 | #define MUSB_RXCSR_AUTOCLEAR 0x8000 |
161 | #define MUSB_RXCSR_DMAENAB 0x2000 |
162 | #define MUSB_RXCSR_DISNYET 0x1000 |
163 | #define MUSB_RXCSR_PID_ERR 0x1000 |
164 | #define MUSB_RXCSR_DMAMODE 0x0800 |
165 | #define MUSB_RXCSR_INCOMPRX 0x0100 |
166 | #define MUSB_RXCSR_CLRDATATOG 0x0080 |
167 | #define MUSB_RXCSR_FLUSHFIFO 0x0010 |
168 | #define MUSB_RXCSR_DATAERROR 0x0008 |
169 | #define MUSB_RXCSR_FIFOFULL 0x0002 |
170 | #define MUSB_RXCSR_RXPKTRDY 0x0001 |
171 | |
172 | /* RXCSR in Peripheral mode */ |
173 | #define MUSB_RXCSR_P_ISO 0x4000 |
174 | #define MUSB_RXCSR_P_SENTSTALL 0x0040 |
175 | #define MUSB_RXCSR_P_SENDSTALL 0x0020 |
176 | #define MUSB_RXCSR_P_OVERRUN 0x0004 |
177 | |
178 | /* RXCSR in Host mode */ |
179 | #define MUSB_RXCSR_H_AUTOREQ 0x4000 |
180 | #define MUSB_RXCSR_H_WR_DATATOGGLE 0x0400 |
181 | #define MUSB_RXCSR_H_DATATOGGLE 0x0200 |
182 | #define MUSB_RXCSR_H_RXSTALL 0x0040 |
183 | #define MUSB_RXCSR_H_REQPKT 0x0020 |
184 | #define MUSB_RXCSR_H_ERROR 0x0004 |
185 | |
186 | /* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */ |
187 | #define MUSB_RXCSR_P_WZC_BITS \ |
188 | (MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \ |
189 | | MUSB_RXCSR_RXPKTRDY) |
190 | #define MUSB_RXCSR_H_WZC_BITS \ |
191 | (MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \ |
192 | | MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY) |
193 | |
194 | /* HUBADDR */ |
195 | #define MUSB_HUBADDR_MULTI_TT 0x80 |
196 | |
197 | |
198 | /* |
199 | * Common USB registers |
200 | */ |
201 | |
202 | #define MUSB_FADDR 0x00 /* 8-bit */ |
203 | #define MUSB_POWER 0x01 /* 8-bit */ |
204 | |
205 | #define MUSB_INTRTX 0x02 /* 16-bit */ |
206 | #define MUSB_INTRRX 0x04 |
207 | #define MUSB_INTRTXE 0x06 |
208 | #define MUSB_INTRRXE 0x08 |
209 | #define MUSB_INTRUSB 0x0A /* 8 bit */ |
210 | #define MUSB_INTRUSBE 0x0B /* 8 bit */ |
211 | #define MUSB_FRAME 0x0C |
212 | #define MUSB_INDEX 0x0E /* 8 bit */ |
213 | #define MUSB_TESTMODE 0x0F /* 8 bit */ |
214 | |
215 | /* |
216 | * Additional Control Registers |
217 | */ |
218 | |
219 | #define MUSB_DEVCTL 0x60 /* 8 bit */ |
220 | #define MUSB_BABBLE_CTL 0x61 /* 8 bit */ |
221 | |
222 | /* These are always controlled through the INDEX register */ |
223 | #define MUSB_TXFIFOSZ 0x62 /* 8-bit (see masks) */ |
224 | #define MUSB_RXFIFOSZ 0x63 /* 8-bit (see masks) */ |
225 | #define MUSB_TXFIFOADD 0x64 /* 16-bit offset shifted right 3 */ |
226 | #define MUSB_RXFIFOADD 0x66 /* 16-bit offset shifted right 3 */ |
227 | |
228 | /* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */ |
229 | #define MUSB_HWVERS 0x6C /* 8 bit */ |
230 | #define MUSB_ULPI_BUSCONTROL 0x70 /* 8 bit */ |
231 | #define MUSB_ULPI_INT_MASK 0x72 /* 8 bit */ |
232 | #define MUSB_ULPI_INT_SRC 0x73 /* 8 bit */ |
233 | #define MUSB_ULPI_REG_DATA 0x74 /* 8 bit */ |
234 | #define MUSB_ULPI_REG_ADDR 0x75 /* 8 bit */ |
235 | #define MUSB_ULPI_REG_CONTROL 0x76 /* 8 bit */ |
236 | #define MUSB_ULPI_RAW_DATA 0x77 /* 8 bit */ |
237 | |
238 | #define MUSB_EPINFO 0x78 /* 8 bit */ |
239 | #define MUSB_RAMINFO 0x79 /* 8 bit */ |
240 | #define MUSB_LINKINFO 0x7a /* 8 bit */ |
241 | #define MUSB_VPLEN 0x7b /* 8 bit */ |
242 | #define MUSB_HS_EOF1 0x7c /* 8 bit */ |
243 | #define MUSB_FS_EOF1 0x7d /* 8 bit */ |
244 | #define MUSB_LS_EOF1 0x7e /* 8 bit */ |
245 | |
246 | /* Offsets to endpoint registers */ |
247 | #define MUSB_TXMAXP 0x00 |
248 | #define MUSB_TXCSR 0x02 |
249 | #define MUSB_CSR0 MUSB_TXCSR /* Re-used for EP0 */ |
250 | #define MUSB_RXMAXP 0x04 |
251 | #define MUSB_RXCSR 0x06 |
252 | #define MUSB_RXCOUNT 0x08 |
253 | #define MUSB_COUNT0 MUSB_RXCOUNT /* Re-used for EP0 */ |
254 | #define MUSB_TXTYPE 0x0A |
255 | #define MUSB_TYPE0 MUSB_TXTYPE /* Re-used for EP0 */ |
256 | #define MUSB_TXINTERVAL 0x0B |
257 | #define MUSB_NAKLIMIT0 MUSB_TXINTERVAL /* Re-used for EP0 */ |
258 | #define MUSB_RXTYPE 0x0C |
259 | #define MUSB_RXINTERVAL 0x0D |
260 | #define MUSB_FIFOSIZE 0x0F |
261 | #define MUSB_CONFIGDATA MUSB_FIFOSIZE /* Re-used for EP0 */ |
262 | |
263 | #include "tusb6010.h" /* Needed "only" for TUSB_EP0_CONF */ |
264 | |
265 | #define MUSB_TXCSR_MODE 0x2000 |
266 | |
267 | /* "bus control"/target registers, for host side multipoint (external hubs) */ |
268 | #define MUSB_TXFUNCADDR 0x00 |
269 | #define MUSB_TXHUBADDR 0x02 |
270 | #define MUSB_TXHUBPORT 0x03 |
271 | |
272 | #define MUSB_RXFUNCADDR 0x04 |
273 | #define MUSB_RXHUBADDR 0x06 |
274 | #define MUSB_RXHUBPORT 0x07 |
275 | |
276 | static inline u8 musb_read_configdata(void __iomem *mbase) |
277 | { |
278 | musb_writeb(mbase, MUSB_INDEX, 0); |
279 | return musb_readb(mbase, 0x10 + MUSB_CONFIGDATA); |
280 | } |
281 | |
282 | static inline void musb_write_rxfunaddr(struct musb *musb, u8 epnum, |
283 | u8 qh_addr_reg) |
284 | { |
285 | musb_writeb(musb->mregs, |
286 | musb->io.busctl_offset(epnum, MUSB_RXFUNCADDR), |
287 | qh_addr_reg); |
288 | } |
289 | |
290 | static inline void musb_write_rxhubaddr(struct musb *musb, u8 epnum, |
291 | u8 qh_h_addr_reg) |
292 | { |
293 | musb_writeb(musb->mregs, musb->io.busctl_offset(epnum, MUSB_RXHUBADDR), |
294 | qh_h_addr_reg); |
295 | } |
296 | |
297 | static inline void musb_write_rxhubport(struct musb *musb, u8 epnum, |
298 | u8 qh_h_port_reg) |
299 | { |
300 | musb_writeb(musb->mregs, musb->io.busctl_offset(epnum, MUSB_RXHUBPORT), |
301 | qh_h_port_reg); |
302 | } |
303 | |
304 | static inline void musb_write_txfunaddr(struct musb *musb, u8 epnum, |
305 | u8 qh_addr_reg) |
306 | { |
307 | musb_writeb(musb->mregs, |
308 | musb->io.busctl_offset(epnum, MUSB_TXFUNCADDR), |
309 | qh_addr_reg); |
310 | } |
311 | |
312 | static inline void musb_write_txhubaddr(struct musb *musb, u8 epnum, |
313 | u8 qh_addr_reg) |
314 | { |
315 | musb_writeb(musb->mregs, musb->io.busctl_offset(epnum, MUSB_TXHUBADDR), |
316 | qh_addr_reg); |
317 | } |
318 | |
319 | static inline void musb_write_txhubport(struct musb *musb, u8 epnum, |
320 | u8 qh_h_port_reg) |
321 | { |
322 | musb_writeb(musb->mregs, musb->io.busctl_offset(epnum, MUSB_TXHUBPORT), |
323 | qh_h_port_reg); |
324 | } |
325 | |
326 | static inline u8 musb_read_rxfunaddr(struct musb *musb, u8 epnum) |
327 | { |
328 | return musb_readb(musb->mregs, |
329 | musb->io.busctl_offset(epnum, MUSB_RXFUNCADDR)); |
330 | } |
331 | |
332 | static inline u8 musb_read_rxhubaddr(struct musb *musb, u8 epnum) |
333 | { |
334 | return musb_readb(musb->mregs, |
335 | musb->io.busctl_offset(epnum, MUSB_RXHUBADDR)); |
336 | } |
337 | |
338 | static inline u8 musb_read_rxhubport(struct musb *musb, u8 epnum) |
339 | { |
340 | return musb_readb(musb->mregs, |
341 | musb->io.busctl_offset(epnum, MUSB_RXHUBPORT)); |
342 | } |
343 | |
344 | static inline u8 musb_read_txfunaddr(struct musb *musb, u8 epnum) |
345 | { |
346 | return musb_readb(musb->mregs, |
347 | musb->io.busctl_offset(epnum, MUSB_TXFUNCADDR)); |
348 | } |
349 | |
350 | static inline u8 musb_read_txhubaddr(struct musb *musb, u8 epnum) |
351 | { |
352 | return musb_readb(musb->mregs, |
353 | musb->io.busctl_offset(epnum, MUSB_TXHUBADDR)); |
354 | } |
355 | |
356 | static inline u8 musb_read_txhubport(struct musb *musb, u8 epnum) |
357 | { |
358 | return musb_readb(musb->mregs, |
359 | musb->io.busctl_offset(epnum, MUSB_TXHUBPORT)); |
360 | } |
361 | |
362 | #endif /* __MUSB_REGS_H__ */ |
363 | |