1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * TUSB6010 USB 2.0 OTG Dual Role controller |
4 | * |
5 | * Copyright (C) 2006 Nokia Corporation |
6 | * Tony Lindgren <tony@atomide.com> |
7 | * |
8 | * Notes: |
9 | * - Driver assumes that interface to external host (main CPU) is |
10 | * configured for NOR FLASH interface instead of VLYNQ serial |
11 | * interface. |
12 | */ |
13 | |
14 | #include <linux/gpio/consumer.h> |
15 | #include <linux/delay.h> |
16 | #include <linux/module.h> |
17 | #include <linux/kernel.h> |
18 | #include <linux/errno.h> |
19 | #include <linux/err.h> |
20 | #include <linux/prefetch.h> |
21 | #include <linux/usb.h> |
22 | #include <linux/irq.h> |
23 | #include <linux/io.h> |
24 | #include <linux/iopoll.h> |
25 | #include <linux/device.h> |
26 | #include <linux/platform_device.h> |
27 | #include <linux/dma-mapping.h> |
28 | #include <linux/usb/usb_phy_generic.h> |
29 | |
30 | #include "musb_core.h" |
31 | |
32 | struct tusb6010_glue { |
33 | struct device *dev; |
34 | struct platform_device *musb; |
35 | struct platform_device *phy; |
36 | struct gpio_desc *enable; |
37 | struct gpio_desc *intpin; |
38 | }; |
39 | |
40 | static void tusb_musb_set_vbus(struct musb *musb, int is_on); |
41 | |
42 | #define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf) |
43 | #define TUSB_REV_MINOR(reg_val) (reg_val & 0xf) |
44 | |
45 | /* |
46 | * Checks the revision. We need to use the DMA register as 3.0 does not |
47 | * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV. |
48 | */ |
49 | static u8 tusb_get_revision(struct musb *musb) |
50 | { |
51 | void __iomem *tbase = musb->ctrl_base; |
52 | u32 die_id; |
53 | u8 rev; |
54 | |
55 | rev = musb_readl(addr: tbase, TUSB_DMA_CTRL_REV) & 0xff; |
56 | if (TUSB_REV_MAJOR(rev) == 3) { |
57 | die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, |
58 | TUSB_DIDR1_HI)); |
59 | if (die_id >= TUSB_DIDR1_HI_REV_31) |
60 | rev |= 1; |
61 | } |
62 | |
63 | return rev; |
64 | } |
65 | |
66 | static void tusb_print_revision(struct musb *musb) |
67 | { |
68 | void __iomem *tbase = musb->ctrl_base; |
69 | u8 rev; |
70 | |
71 | rev = musb->tusb_revision; |
72 | |
73 | pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n" , |
74 | "prcm" , |
75 | TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)), |
76 | TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)), |
77 | "int" , |
78 | TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)), |
79 | TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)), |
80 | "gpio" , |
81 | TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)), |
82 | TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)), |
83 | "dma" , |
84 | TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)), |
85 | TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)), |
86 | "dieid" , |
87 | TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)), |
88 | "rev" , |
89 | TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev)); |
90 | } |
91 | |
92 | #define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \ |
93 | | TUSB_PHY_OTG_CTRL_TESTM0) |
94 | |
95 | /* |
96 | * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0. |
97 | * Disables power detection in PHY for the duration of idle. |
98 | */ |
99 | static void tusb_wbus_quirk(struct musb *musb, int enabled) |
100 | { |
101 | void __iomem *tbase = musb->ctrl_base; |
102 | static u32 phy_otg_ctrl, phy_otg_ena; |
103 | u32 tmp; |
104 | |
105 | if (enabled) { |
106 | phy_otg_ctrl = musb_readl(addr: tbase, TUSB_PHY_OTG_CTRL); |
107 | phy_otg_ena = musb_readl(addr: tbase, TUSB_PHY_OTG_CTRL_ENABLE); |
108 | tmp = TUSB_PHY_OTG_CTRL_WRPROTECT |
109 | | phy_otg_ena | WBUS_QUIRK_MASK; |
110 | musb_writel(addr: tbase, TUSB_PHY_OTG_CTRL, data: tmp); |
111 | tmp = phy_otg_ena & ~WBUS_QUIRK_MASK; |
112 | tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2; |
113 | musb_writel(addr: tbase, TUSB_PHY_OTG_CTRL_ENABLE, data: tmp); |
114 | dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n" , |
115 | musb_readl(tbase, TUSB_PHY_OTG_CTRL), |
116 | musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)); |
117 | } else if (musb_readl(addr: tbase, TUSB_PHY_OTG_CTRL_ENABLE) |
118 | & TUSB_PHY_OTG_CTRL_TESTM2) { |
119 | tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl; |
120 | musb_writel(addr: tbase, TUSB_PHY_OTG_CTRL, data: tmp); |
121 | tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena; |
122 | musb_writel(addr: tbase, TUSB_PHY_OTG_CTRL_ENABLE, data: tmp); |
123 | dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n" , |
124 | musb_readl(tbase, TUSB_PHY_OTG_CTRL), |
125 | musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)); |
126 | phy_otg_ctrl = 0; |
127 | phy_otg_ena = 0; |
128 | } |
129 | } |
130 | |
131 | static u32 tusb_fifo_offset(u8 epnum) |
132 | { |
133 | return 0x200 + (epnum * 0x20); |
134 | } |
135 | |
136 | static u32 tusb_ep_offset(u8 epnum, u16 offset) |
137 | { |
138 | return 0x10 + offset; |
139 | } |
140 | |
141 | /* TUSB mapping: "flat" plus ep0 special cases */ |
142 | static void tusb_ep_select(void __iomem *mbase, u8 epnum) |
143 | { |
144 | musb_writeb(mbase, MUSB_INDEX, epnum); |
145 | } |
146 | |
147 | /* |
148 | * TUSB6010 doesn't allow 8-bit access; 16-bit access is the minimum. |
149 | */ |
150 | static u8 tusb_readb(void __iomem *addr, u32 offset) |
151 | { |
152 | u16 tmp; |
153 | u8 val; |
154 | |
155 | tmp = __raw_readw(addr: addr + (offset & ~1)); |
156 | if (offset & 1) |
157 | val = (tmp >> 8); |
158 | else |
159 | val = tmp & 0xff; |
160 | |
161 | return val; |
162 | } |
163 | |
164 | static void tusb_writeb(void __iomem *addr, u32 offset, u8 data) |
165 | { |
166 | u16 tmp; |
167 | |
168 | tmp = __raw_readw(addr: addr + (offset & ~1)); |
169 | if (offset & 1) |
170 | tmp = (data << 8) | (tmp & 0xff); |
171 | else |
172 | tmp = (tmp & 0xff00) | data; |
173 | |
174 | __raw_writew(val: tmp, addr: addr + (offset & ~1)); |
175 | } |
176 | |
177 | /* |
178 | * TUSB 6010 may use a parallel bus that doesn't support byte ops; |
179 | * so both loading and unloading FIFOs need explicit byte counts. |
180 | */ |
181 | |
182 | static inline void |
183 | tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len) |
184 | { |
185 | u32 val; |
186 | int i; |
187 | |
188 | if (len > 4) { |
189 | for (i = 0; i < (len >> 2); i++) { |
190 | memcpy(&val, buf, 4); |
191 | musb_writel(addr: fifo, offset: 0, data: val); |
192 | buf += 4; |
193 | } |
194 | len %= 4; |
195 | } |
196 | if (len > 0) { |
197 | /* Write the rest 1 - 3 bytes to FIFO */ |
198 | val = 0; |
199 | memcpy(&val, buf, len); |
200 | musb_writel(addr: fifo, offset: 0, data: val); |
201 | } |
202 | } |
203 | |
204 | static inline void tusb_fifo_read_unaligned(void __iomem *fifo, |
205 | void *buf, u16 len) |
206 | { |
207 | u32 val; |
208 | int i; |
209 | |
210 | if (len > 4) { |
211 | for (i = 0; i < (len >> 2); i++) { |
212 | val = musb_readl(addr: fifo, offset: 0); |
213 | memcpy(buf, &val, 4); |
214 | buf += 4; |
215 | } |
216 | len %= 4; |
217 | } |
218 | if (len > 0) { |
219 | /* Read the rest 1 - 3 bytes from FIFO */ |
220 | val = musb_readl(addr: fifo, offset: 0); |
221 | memcpy(buf, &val, len); |
222 | } |
223 | } |
224 | |
225 | static void tusb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf) |
226 | { |
227 | struct musb *musb = hw_ep->musb; |
228 | void __iomem *ep_conf = hw_ep->conf; |
229 | void __iomem *fifo = hw_ep->fifo; |
230 | u8 epnum = hw_ep->epnum; |
231 | |
232 | prefetch(buf); |
233 | |
234 | dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n" , |
235 | 'T', epnum, fifo, len, buf); |
236 | |
237 | if (epnum) |
238 | musb_writel(addr: ep_conf, TUSB_EP_TX_OFFSET, |
239 | TUSB_EP_CONFIG_XFR_SIZE(len)); |
240 | else |
241 | musb_writel(addr: ep_conf, offset: 0, TUSB_EP0_CONFIG_DIR_TX | |
242 | TUSB_EP0_CONFIG_XFR_SIZE(len)); |
243 | |
244 | if (likely((0x01 & (unsigned long) buf) == 0)) { |
245 | |
246 | /* Best case is 32bit-aligned destination address */ |
247 | if ((0x02 & (unsigned long) buf) == 0) { |
248 | if (len >= 4) { |
249 | iowrite32_rep(port: fifo, buf, count: len >> 2); |
250 | buf += (len & ~0x03); |
251 | len &= 0x03; |
252 | } |
253 | } else { |
254 | if (len >= 2) { |
255 | u32 val; |
256 | int i; |
257 | |
258 | /* Cannot use writesw, fifo is 32-bit */ |
259 | for (i = 0; i < (len >> 2); i++) { |
260 | val = (u32)(*(u16 *)buf); |
261 | buf += 2; |
262 | val |= (*(u16 *)buf) << 16; |
263 | buf += 2; |
264 | musb_writel(addr: fifo, offset: 0, data: val); |
265 | } |
266 | len &= 0x03; |
267 | } |
268 | } |
269 | } |
270 | |
271 | if (len > 0) |
272 | tusb_fifo_write_unaligned(fifo, buf, len); |
273 | } |
274 | |
275 | static void tusb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf) |
276 | { |
277 | struct musb *musb = hw_ep->musb; |
278 | void __iomem *ep_conf = hw_ep->conf; |
279 | void __iomem *fifo = hw_ep->fifo; |
280 | u8 epnum = hw_ep->epnum; |
281 | |
282 | dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n" , |
283 | 'R', epnum, fifo, len, buf); |
284 | |
285 | if (epnum) |
286 | musb_writel(addr: ep_conf, TUSB_EP_RX_OFFSET, |
287 | TUSB_EP_CONFIG_XFR_SIZE(len)); |
288 | else |
289 | musb_writel(addr: ep_conf, offset: 0, TUSB_EP0_CONFIG_XFR_SIZE(len)); |
290 | |
291 | if (likely((0x01 & (unsigned long) buf) == 0)) { |
292 | |
293 | /* Best case is 32bit-aligned destination address */ |
294 | if ((0x02 & (unsigned long) buf) == 0) { |
295 | if (len >= 4) { |
296 | ioread32_rep(port: fifo, buf, count: len >> 2); |
297 | buf += (len & ~0x03); |
298 | len &= 0x03; |
299 | } |
300 | } else { |
301 | if (len >= 2) { |
302 | u32 val; |
303 | int i; |
304 | |
305 | /* Cannot use readsw, fifo is 32-bit */ |
306 | for (i = 0; i < (len >> 2); i++) { |
307 | val = musb_readl(addr: fifo, offset: 0); |
308 | *(u16 *)buf = (u16)(val & 0xffff); |
309 | buf += 2; |
310 | *(u16 *)buf = (u16)(val >> 16); |
311 | buf += 2; |
312 | } |
313 | len &= 0x03; |
314 | } |
315 | } |
316 | } |
317 | |
318 | if (len > 0) |
319 | tusb_fifo_read_unaligned(fifo, buf, len); |
320 | } |
321 | |
322 | static struct musb *the_musb; |
323 | |
324 | /* This is used by gadget drivers, and OTG transceiver logic, allowing |
325 | * at most mA current to be drawn from VBUS during a Default-B session |
326 | * (that is, while VBUS exceeds 4.4V). In Default-A (including pure host |
327 | * mode), or low power Default-B sessions, something else supplies power. |
328 | * Caller must take care of locking. |
329 | */ |
330 | static int tusb_draw_power(struct usb_phy *x, unsigned mA) |
331 | { |
332 | struct musb *musb = the_musb; |
333 | void __iomem *tbase = musb->ctrl_base; |
334 | u32 reg; |
335 | |
336 | /* tps65030 seems to consume max 100mA, with maybe 60mA available |
337 | * (measured on one board) for things other than tps and tusb. |
338 | * |
339 | * Boards sharing the CPU clock with CLKIN will need to prevent |
340 | * certain idle sleep states while the USB link is active. |
341 | * |
342 | * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }. |
343 | * The actual current usage would be very board-specific. For now, |
344 | * it's simpler to just use an aggregate (also board-specific). |
345 | */ |
346 | if (x->otg->default_a || mA < (musb->min_power << 1)) |
347 | mA = 0; |
348 | |
349 | reg = musb_readl(addr: tbase, TUSB_PRCM_MNGMT); |
350 | if (mA) { |
351 | musb->is_bus_powered = 1; |
352 | reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN; |
353 | } else { |
354 | musb->is_bus_powered = 0; |
355 | reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN); |
356 | } |
357 | musb_writel(addr: tbase, TUSB_PRCM_MNGMT, data: reg); |
358 | |
359 | dev_dbg(musb->controller, "draw max %d mA VBUS\n" , mA); |
360 | return 0; |
361 | } |
362 | |
363 | /* workaround for issue 13: change clock during chip idle |
364 | * (to be fixed in rev3 silicon) ... symptoms include disconnect |
365 | * or looping suspend/resume cycles |
366 | */ |
367 | static void tusb_set_clock_source(struct musb *musb, unsigned mode) |
368 | { |
369 | void __iomem *tbase = musb->ctrl_base; |
370 | u32 reg; |
371 | |
372 | reg = musb_readl(addr: tbase, TUSB_PRCM_CONF); |
373 | reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3); |
374 | |
375 | /* 0 = refclk (clkin, XI) |
376 | * 1 = PHY 60 MHz (internal PLL) |
377 | * 2 = not supported |
378 | * 3 = what? |
379 | */ |
380 | if (mode > 0) |
381 | reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3); |
382 | |
383 | musb_writel(addr: tbase, TUSB_PRCM_CONF, data: reg); |
384 | |
385 | /* FIXME tusb6010_platform_retime(mode == 0); */ |
386 | } |
387 | |
388 | /* |
389 | * Idle TUSB6010 until next wake-up event; NOR access always wakes. |
390 | * Other code ensures that we idle unless we're connected _and_ the |
391 | * USB link is not suspended ... and tells us the relevant wakeup |
392 | * events. SW_EN for voltage is handled separately. |
393 | */ |
394 | static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables) |
395 | { |
396 | void __iomem *tbase = musb->ctrl_base; |
397 | u32 reg; |
398 | |
399 | if ((wakeup_enables & TUSB_PRCM_WBUS) |
400 | && (musb->tusb_revision == TUSB_REV_30)) |
401 | tusb_wbus_quirk(musb, enabled: 1); |
402 | |
403 | tusb_set_clock_source(musb, mode: 0); |
404 | |
405 | wakeup_enables |= TUSB_PRCM_WNORCS; |
406 | musb_writel(addr: tbase, TUSB_PRCM_WAKEUP_MASK, data: ~wakeup_enables); |
407 | |
408 | /* REVISIT writeup of WID implies that if WID set and ID is grounded, |
409 | * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared. |
410 | * Presumably that's mostly to save power, hence WID is immaterial ... |
411 | */ |
412 | |
413 | reg = musb_readl(addr: tbase, TUSB_PRCM_MNGMT); |
414 | /* issue 4: when driving vbus, use hipower (vbus_det) comparator */ |
415 | if (is_host_active(musb)) { |
416 | reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; |
417 | reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN; |
418 | } else { |
419 | reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN; |
420 | reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; |
421 | } |
422 | reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE; |
423 | musb_writel(addr: tbase, TUSB_PRCM_MNGMT, data: reg); |
424 | |
425 | dev_dbg(musb->controller, "idle, wake on %02x\n" , wakeup_enables); |
426 | } |
427 | |
428 | /* |
429 | * Updates cable VBUS status. Caller must take care of locking. |
430 | */ |
431 | static int tusb_musb_vbus_status(struct musb *musb) |
432 | { |
433 | void __iomem *tbase = musb->ctrl_base; |
434 | u32 otg_stat, prcm_mngmt; |
435 | int ret = 0; |
436 | |
437 | otg_stat = musb_readl(addr: tbase, TUSB_DEV_OTG_STAT); |
438 | prcm_mngmt = musb_readl(addr: tbase, TUSB_PRCM_MNGMT); |
439 | |
440 | /* Temporarily enable VBUS detection if it was disabled for |
441 | * suspend mode. Unless it's enabled otg_stat and devctl will |
442 | * not show correct VBUS state. |
443 | */ |
444 | if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) { |
445 | u32 tmp = prcm_mngmt; |
446 | tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; |
447 | musb_writel(addr: tbase, TUSB_PRCM_MNGMT, data: tmp); |
448 | otg_stat = musb_readl(addr: tbase, TUSB_DEV_OTG_STAT); |
449 | musb_writel(addr: tbase, TUSB_PRCM_MNGMT, data: prcm_mngmt); |
450 | } |
451 | |
452 | if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) |
453 | ret = 1; |
454 | |
455 | return ret; |
456 | } |
457 | |
458 | static void musb_do_idle(struct timer_list *t) |
459 | { |
460 | struct musb *musb = from_timer(musb, t, dev_timer); |
461 | unsigned long flags; |
462 | |
463 | spin_lock_irqsave(&musb->lock, flags); |
464 | |
465 | switch (musb->xceiv->otg->state) { |
466 | case OTG_STATE_A_WAIT_BCON: |
467 | if ((musb->a_wait_bcon != 0) |
468 | && (musb->idle_timeout == 0 |
469 | || time_after(jiffies, musb->idle_timeout))) { |
470 | dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n" , |
471 | usb_otg_state_string(musb->xceiv->otg->state)); |
472 | } |
473 | fallthrough; |
474 | case OTG_STATE_A_IDLE: |
475 | tusb_musb_set_vbus(musb, is_on: 0); |
476 | break; |
477 | default: |
478 | break; |
479 | } |
480 | |
481 | if (!musb->is_active) { |
482 | u32 wakeups; |
483 | |
484 | /* wait until hub_wq handles port change status */ |
485 | if (is_host_active(musb) && (musb->port1_status >> 16)) |
486 | goto done; |
487 | |
488 | if (!musb->gadget_driver) { |
489 | wakeups = 0; |
490 | } else { |
491 | wakeups = TUSB_PRCM_WHOSTDISCON |
492 | | TUSB_PRCM_WBUS |
493 | | TUSB_PRCM_WVBUS; |
494 | wakeups |= TUSB_PRCM_WID; |
495 | } |
496 | tusb_allow_idle(musb, wakeup_enables: wakeups); |
497 | } |
498 | done: |
499 | spin_unlock_irqrestore(lock: &musb->lock, flags); |
500 | } |
501 | |
502 | /* |
503 | * Maybe put TUSB6010 into idle mode depending on USB link status, |
504 | * like "disconnected" or "suspended". We'll be woken out of it by |
505 | * connect, resume, or disconnect. |
506 | * |
507 | * Needs to be called as the last function everywhere where there is |
508 | * register access to TUSB6010 because of NOR flash wake-up. |
509 | * Caller should own controller spinlock. |
510 | * |
511 | * Delay because peripheral enables D+ pullup 3msec after SE0, and |
512 | * we don't want to treat that full speed J as a wakeup event. |
513 | * ... peripherals must draw only suspend current after 10 msec. |
514 | */ |
515 | static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout) |
516 | { |
517 | unsigned long default_timeout = jiffies + msecs_to_jiffies(m: 3); |
518 | static unsigned long last_timer; |
519 | |
520 | if (timeout == 0) |
521 | timeout = default_timeout; |
522 | |
523 | /* Never idle if active, or when VBUS timeout is not set as host */ |
524 | if (musb->is_active || ((musb->a_wait_bcon == 0) |
525 | && (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON))) { |
526 | dev_dbg(musb->controller, "%s active, deleting timer\n" , |
527 | usb_otg_state_string(musb->xceiv->otg->state)); |
528 | del_timer(timer: &musb->dev_timer); |
529 | last_timer = jiffies; |
530 | return; |
531 | } |
532 | |
533 | if (time_after(last_timer, timeout)) { |
534 | if (!timer_pending(timer: &musb->dev_timer)) |
535 | last_timer = timeout; |
536 | else { |
537 | dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n" ); |
538 | return; |
539 | } |
540 | } |
541 | last_timer = timeout; |
542 | |
543 | dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n" , |
544 | usb_otg_state_string(musb->xceiv->otg->state), |
545 | (unsigned long)jiffies_to_msecs(timeout - jiffies)); |
546 | mod_timer(timer: &musb->dev_timer, expires: timeout); |
547 | } |
548 | |
549 | /* ticks of 60 MHz clock */ |
550 | #define DEVCLOCK 60000000 |
551 | #define OTG_TIMER_MS(msecs) ((msecs) \ |
552 | ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \ |
553 | | TUSB_DEV_OTG_TIMER_ENABLE) \ |
554 | : 0) |
555 | |
556 | static void tusb_musb_set_vbus(struct musb *musb, int is_on) |
557 | { |
558 | void __iomem *tbase = musb->ctrl_base; |
559 | u32 conf, prcm, timer; |
560 | u8 devctl; |
561 | struct usb_otg *otg = musb->xceiv->otg; |
562 | |
563 | /* HDRC controls CPEN, but beware current surges during device |
564 | * connect. They can trigger transient overcurrent conditions |
565 | * that must be ignored. |
566 | */ |
567 | |
568 | prcm = musb_readl(addr: tbase, TUSB_PRCM_MNGMT); |
569 | conf = musb_readl(addr: tbase, TUSB_DEV_CONF); |
570 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); |
571 | |
572 | if (is_on) { |
573 | timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE); |
574 | otg->default_a = 1; |
575 | musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; |
576 | devctl |= MUSB_DEVCTL_SESSION; |
577 | |
578 | conf |= TUSB_DEV_CONF_USB_HOST_MODE; |
579 | MUSB_HST_MODE(musb); |
580 | } else { |
581 | u32 otg_stat; |
582 | |
583 | timer = 0; |
584 | |
585 | /* If ID pin is grounded, we want to be a_idle */ |
586 | otg_stat = musb_readl(addr: tbase, TUSB_DEV_OTG_STAT); |
587 | if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) { |
588 | switch (musb->xceiv->otg->state) { |
589 | case OTG_STATE_A_WAIT_VRISE: |
590 | case OTG_STATE_A_WAIT_BCON: |
591 | musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL; |
592 | break; |
593 | case OTG_STATE_A_WAIT_VFALL: |
594 | musb->xceiv->otg->state = OTG_STATE_A_IDLE; |
595 | break; |
596 | default: |
597 | musb->xceiv->otg->state = OTG_STATE_A_IDLE; |
598 | } |
599 | musb->is_active = 0; |
600 | otg->default_a = 1; |
601 | MUSB_HST_MODE(musb); |
602 | } else { |
603 | musb->is_active = 0; |
604 | otg->default_a = 0; |
605 | musb->xceiv->otg->state = OTG_STATE_B_IDLE; |
606 | MUSB_DEV_MODE(musb); |
607 | } |
608 | |
609 | devctl &= ~MUSB_DEVCTL_SESSION; |
610 | conf &= ~TUSB_DEV_CONF_USB_HOST_MODE; |
611 | } |
612 | prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN); |
613 | |
614 | musb_writel(addr: tbase, TUSB_PRCM_MNGMT, data: prcm); |
615 | musb_writel(addr: tbase, TUSB_DEV_OTG_TIMER, data: timer); |
616 | musb_writel(addr: tbase, TUSB_DEV_CONF, data: conf); |
617 | musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); |
618 | |
619 | dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n" , |
620 | usb_otg_state_string(musb->xceiv->otg->state), |
621 | musb_readb(musb->mregs, MUSB_DEVCTL), |
622 | musb_readl(tbase, TUSB_DEV_OTG_STAT), |
623 | conf, prcm); |
624 | } |
625 | |
626 | /* |
627 | * Sets the mode to OTG, peripheral or host by changing the ID detection. |
628 | * Caller must take care of locking. |
629 | * |
630 | * Note that if a mini-A cable is plugged in the ID line will stay down as |
631 | * the weak ID pull-up is not able to pull the ID up. |
632 | */ |
633 | static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode) |
634 | { |
635 | void __iomem *tbase = musb->ctrl_base; |
636 | u32 otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf; |
637 | |
638 | otg_stat = musb_readl(addr: tbase, TUSB_DEV_OTG_STAT); |
639 | phy_otg_ctrl = musb_readl(addr: tbase, TUSB_PHY_OTG_CTRL); |
640 | phy_otg_ena = musb_readl(addr: tbase, TUSB_PHY_OTG_CTRL_ENABLE); |
641 | dev_conf = musb_readl(addr: tbase, TUSB_DEV_CONF); |
642 | |
643 | switch (musb_mode) { |
644 | |
645 | case MUSB_HOST: /* Disable PHY ID detect, ground ID */ |
646 | phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; |
647 | phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; |
648 | dev_conf |= TUSB_DEV_CONF_ID_SEL; |
649 | dev_conf &= ~TUSB_DEV_CONF_SOFT_ID; |
650 | break; |
651 | case MUSB_PERIPHERAL: /* Disable PHY ID detect, keep ID pull-up on */ |
652 | phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; |
653 | phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; |
654 | dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID); |
655 | break; |
656 | case MUSB_OTG: /* Use PHY ID detection */ |
657 | phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; |
658 | phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; |
659 | dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID); |
660 | break; |
661 | |
662 | default: |
663 | dev_dbg(musb->controller, "Trying to set mode %i\n" , musb_mode); |
664 | return -EINVAL; |
665 | } |
666 | |
667 | musb_writel(addr: tbase, TUSB_PHY_OTG_CTRL, |
668 | TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl); |
669 | musb_writel(addr: tbase, TUSB_PHY_OTG_CTRL_ENABLE, |
670 | TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena); |
671 | musb_writel(addr: tbase, TUSB_DEV_CONF, data: dev_conf); |
672 | |
673 | otg_stat = musb_readl(addr: tbase, TUSB_DEV_OTG_STAT); |
674 | if ((musb_mode == MUSB_PERIPHERAL) && |
675 | !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) |
676 | INFO("Cannot be peripheral with mini-A cable " |
677 | "otg_stat: %08x\n" , otg_stat); |
678 | |
679 | return 0; |
680 | } |
681 | |
682 | static inline unsigned long |
683 | tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase) |
684 | { |
685 | u32 otg_stat = musb_readl(addr: tbase, TUSB_DEV_OTG_STAT); |
686 | unsigned long idle_timeout = 0; |
687 | struct usb_otg *otg = musb->xceiv->otg; |
688 | |
689 | /* ID pin */ |
690 | if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) { |
691 | int default_a; |
692 | |
693 | default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS); |
694 | dev_dbg(musb->controller, "Default-%c\n" , default_a ? 'A' : 'B'); |
695 | otg->default_a = default_a; |
696 | tusb_musb_set_vbus(musb, is_on: default_a); |
697 | |
698 | /* Don't allow idling immediately */ |
699 | if (default_a) |
700 | idle_timeout = jiffies + (HZ * 3); |
701 | } |
702 | |
703 | /* VBUS state change */ |
704 | if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) { |
705 | |
706 | /* B-dev state machine: no vbus ~= disconnect */ |
707 | if (!otg->default_a) { |
708 | /* ? musb_root_disconnect(musb); */ |
709 | musb->port1_status &= |
710 | ~(USB_PORT_STAT_CONNECTION |
711 | | USB_PORT_STAT_ENABLE |
712 | | USB_PORT_STAT_LOW_SPEED |
713 | | USB_PORT_STAT_HIGH_SPEED |
714 | | USB_PORT_STAT_TEST |
715 | ); |
716 | |
717 | if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) { |
718 | dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n" ); |
719 | if (musb->xceiv->otg->state != OTG_STATE_B_IDLE) { |
720 | /* INTR_DISCONNECT can hide... */ |
721 | musb->xceiv->otg->state = OTG_STATE_B_IDLE; |
722 | musb->int_usb |= MUSB_INTR_DISCONNECT; |
723 | } |
724 | musb->is_active = 0; |
725 | } |
726 | dev_dbg(musb->controller, "vbus change, %s, otg %03x\n" , |
727 | usb_otg_state_string(musb->xceiv->otg->state), otg_stat); |
728 | idle_timeout = jiffies + (1 * HZ); |
729 | schedule_delayed_work(dwork: &musb->irq_work, delay: 0); |
730 | |
731 | } else /* A-dev state machine */ { |
732 | dev_dbg(musb->controller, "vbus change, %s, otg %03x\n" , |
733 | usb_otg_state_string(musb->xceiv->otg->state), otg_stat); |
734 | |
735 | switch (musb->xceiv->otg->state) { |
736 | case OTG_STATE_A_IDLE: |
737 | dev_dbg(musb->controller, "Got SRP, turning on VBUS\n" ); |
738 | musb_platform_set_vbus(musb, is_on: 1); |
739 | |
740 | /* CONNECT can wake if a_wait_bcon is set */ |
741 | if (musb->a_wait_bcon != 0) |
742 | musb->is_active = 0; |
743 | else |
744 | musb->is_active = 1; |
745 | |
746 | /* |
747 | * OPT FS A TD.4.6 needs few seconds for |
748 | * A_WAIT_VRISE |
749 | */ |
750 | idle_timeout = jiffies + (2 * HZ); |
751 | |
752 | break; |
753 | case OTG_STATE_A_WAIT_VRISE: |
754 | /* ignore; A-session-valid < VBUS_VALID/2, |
755 | * we monitor this with the timer |
756 | */ |
757 | break; |
758 | case OTG_STATE_A_WAIT_VFALL: |
759 | /* REVISIT this irq triggers during short |
760 | * spikes caused by enumeration ... |
761 | */ |
762 | if (musb->vbuserr_retry) { |
763 | musb->vbuserr_retry--; |
764 | tusb_musb_set_vbus(musb, is_on: 1); |
765 | } else { |
766 | musb->vbuserr_retry |
767 | = VBUSERR_RETRY_COUNT; |
768 | tusb_musb_set_vbus(musb, is_on: 0); |
769 | } |
770 | break; |
771 | default: |
772 | break; |
773 | } |
774 | } |
775 | } |
776 | |
777 | /* OTG timer expiration */ |
778 | if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) { |
779 | u8 devctl; |
780 | |
781 | dev_dbg(musb->controller, "%s timer, %03x\n" , |
782 | usb_otg_state_string(musb->xceiv->otg->state), otg_stat); |
783 | |
784 | switch (musb->xceiv->otg->state) { |
785 | case OTG_STATE_A_WAIT_VRISE: |
786 | /* VBUS has probably been valid for a while now, |
787 | * but may well have bounced out of range a bit |
788 | */ |
789 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); |
790 | if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) { |
791 | if ((devctl & MUSB_DEVCTL_VBUS) |
792 | != MUSB_DEVCTL_VBUS) { |
793 | dev_dbg(musb->controller, "devctl %02x\n" , devctl); |
794 | break; |
795 | } |
796 | musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON; |
797 | musb->is_active = 0; |
798 | idle_timeout = jiffies |
799 | + msecs_to_jiffies(m: musb->a_wait_bcon); |
800 | } else { |
801 | /* REVISIT report overcurrent to hub? */ |
802 | ERR("vbus too slow, devctl %02x\n" , devctl); |
803 | tusb_musb_set_vbus(musb, is_on: 0); |
804 | } |
805 | break; |
806 | case OTG_STATE_A_WAIT_BCON: |
807 | if (musb->a_wait_bcon != 0) |
808 | idle_timeout = jiffies |
809 | + msecs_to_jiffies(m: musb->a_wait_bcon); |
810 | break; |
811 | case OTG_STATE_A_SUSPEND: |
812 | break; |
813 | case OTG_STATE_B_WAIT_ACON: |
814 | break; |
815 | default: |
816 | break; |
817 | } |
818 | } |
819 | schedule_delayed_work(dwork: &musb->irq_work, delay: 0); |
820 | |
821 | return idle_timeout; |
822 | } |
823 | |
824 | static irqreturn_t tusb_musb_interrupt(int irq, void *__hci) |
825 | { |
826 | struct musb *musb = __hci; |
827 | void __iomem *tbase = musb->ctrl_base; |
828 | unsigned long flags, idle_timeout = 0; |
829 | u32 int_mask, int_src; |
830 | |
831 | spin_lock_irqsave(&musb->lock, flags); |
832 | |
833 | /* Mask all interrupts to allow using both edge and level GPIO irq */ |
834 | int_mask = musb_readl(addr: tbase, TUSB_INT_MASK); |
835 | musb_writel(addr: tbase, TUSB_INT_MASK, data: ~TUSB_INT_MASK_RESERVED_BITS); |
836 | |
837 | int_src = musb_readl(addr: tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS; |
838 | dev_dbg(musb->controller, "TUSB IRQ %08x\n" , int_src); |
839 | |
840 | musb->int_usb = (u8) int_src; |
841 | |
842 | /* Acknowledge wake-up source interrupts */ |
843 | if (int_src & TUSB_INT_SRC_DEV_WAKEUP) { |
844 | u32 reg; |
845 | u32 i; |
846 | |
847 | if (musb->tusb_revision == TUSB_REV_30) |
848 | tusb_wbus_quirk(musb, enabled: 0); |
849 | |
850 | /* there are issues re-locking the PLL on wakeup ... */ |
851 | |
852 | /* work around issue 8 */ |
853 | for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) { |
854 | musb_writel(addr: tbase, TUSB_SCRATCH_PAD, data: 0); |
855 | musb_writel(addr: tbase, TUSB_SCRATCH_PAD, data: i); |
856 | reg = musb_readl(addr: tbase, TUSB_SCRATCH_PAD); |
857 | if (reg == i) |
858 | break; |
859 | dev_dbg(musb->controller, "TUSB NOR not ready\n" ); |
860 | } |
861 | |
862 | /* work around issue 13 (2nd half) */ |
863 | tusb_set_clock_source(musb, mode: 1); |
864 | |
865 | reg = musb_readl(addr: tbase, TUSB_PRCM_WAKEUP_SOURCE); |
866 | musb_writel(addr: tbase, TUSB_PRCM_WAKEUP_CLEAR, data: reg); |
867 | if (reg & ~TUSB_PRCM_WNORCS) { |
868 | musb->is_active = 1; |
869 | schedule_delayed_work(dwork: &musb->irq_work, delay: 0); |
870 | } |
871 | dev_dbg(musb->controller, "wake %sactive %02x\n" , |
872 | musb->is_active ? "" : "in" , reg); |
873 | |
874 | /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */ |
875 | } |
876 | |
877 | if (int_src & TUSB_INT_SRC_USB_IP_CONN) |
878 | del_timer(timer: &musb->dev_timer); |
879 | |
880 | /* OTG state change reports (annoyingly) not issued by Mentor core */ |
881 | if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG |
882 | | TUSB_INT_SRC_OTG_TIMEOUT |
883 | | TUSB_INT_SRC_ID_STATUS_CHNG)) |
884 | idle_timeout = tusb_otg_ints(musb, int_src, tbase); |
885 | |
886 | /* |
887 | * Just clear the DMA interrupt if it comes as the completion for both |
888 | * TX and RX is handled by the DMA callback in tusb6010_omap |
889 | */ |
890 | if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) { |
891 | u32 dma_src = musb_readl(addr: tbase, TUSB_DMA_INT_SRC); |
892 | |
893 | dev_dbg(musb->controller, "DMA IRQ %08x\n" , dma_src); |
894 | musb_writel(addr: tbase, TUSB_DMA_INT_CLEAR, data: dma_src); |
895 | } |
896 | |
897 | /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */ |
898 | if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) { |
899 | u32 musb_src = musb_readl(addr: tbase, TUSB_USBIP_INT_SRC); |
900 | |
901 | musb_writel(addr: tbase, TUSB_USBIP_INT_CLEAR, data: musb_src); |
902 | musb->int_rx = (((musb_src >> 16) & 0xffff) << 1); |
903 | musb->int_tx = (musb_src & 0xffff); |
904 | } else { |
905 | musb->int_rx = 0; |
906 | musb->int_tx = 0; |
907 | } |
908 | |
909 | if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff)) |
910 | musb_interrupt(musb); |
911 | |
912 | /* Acknowledge TUSB interrupts. Clear only non-reserved bits */ |
913 | musb_writel(addr: tbase, TUSB_INT_SRC_CLEAR, |
914 | data: int_src & ~TUSB_INT_MASK_RESERVED_BITS); |
915 | |
916 | tusb_musb_try_idle(musb, timeout: idle_timeout); |
917 | |
918 | musb_writel(addr: tbase, TUSB_INT_MASK, data: int_mask); |
919 | spin_unlock_irqrestore(lock: &musb->lock, flags); |
920 | |
921 | return IRQ_HANDLED; |
922 | } |
923 | |
924 | static int dma_off; |
925 | |
926 | /* |
927 | * Enables TUSB6010. Caller must take care of locking. |
928 | * REVISIT: |
929 | * - Check what is unnecessary in MGC_HdrcStart() |
930 | */ |
931 | static void tusb_musb_enable(struct musb *musb) |
932 | { |
933 | void __iomem *tbase = musb->ctrl_base; |
934 | |
935 | /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF. |
936 | * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */ |
937 | musb_writel(addr: tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF); |
938 | |
939 | /* Setup TUSB interrupt, disable DMA and GPIO interrupts */ |
940 | musb_writel(addr: tbase, TUSB_USBIP_INT_MASK, data: 0); |
941 | musb_writel(addr: tbase, TUSB_DMA_INT_MASK, data: 0x7fffffff); |
942 | musb_writel(addr: tbase, TUSB_GPIO_INT_MASK, data: 0x1ff); |
943 | |
944 | /* Clear all subsystem interrups */ |
945 | musb_writel(addr: tbase, TUSB_USBIP_INT_CLEAR, data: 0x7fffffff); |
946 | musb_writel(addr: tbase, TUSB_DMA_INT_CLEAR, data: 0x7fffffff); |
947 | musb_writel(addr: tbase, TUSB_GPIO_INT_CLEAR, data: 0x1ff); |
948 | |
949 | /* Acknowledge pending interrupt(s) */ |
950 | musb_writel(addr: tbase, TUSB_INT_SRC_CLEAR, data: ~TUSB_INT_MASK_RESERVED_BITS); |
951 | |
952 | /* Only 0 clock cycles for minimum interrupt de-assertion time and |
953 | * interrupt polarity active low seems to work reliably here */ |
954 | musb_writel(addr: tbase, TUSB_INT_CTRL_CONF, |
955 | TUSB_INT_CTRL_CONF_INT_RELCYC(0)); |
956 | |
957 | irq_set_irq_type(irq: musb->nIrq, type: IRQ_TYPE_LEVEL_LOW); |
958 | |
959 | /* maybe force into the Default-A OTG state machine */ |
960 | if (!(musb_readl(addr: tbase, TUSB_DEV_OTG_STAT) |
961 | & TUSB_DEV_OTG_STAT_ID_STATUS)) |
962 | musb_writel(addr: tbase, TUSB_INT_SRC_SET, |
963 | TUSB_INT_SRC_ID_STATUS_CHNG); |
964 | |
965 | if (is_dma_capable() && dma_off) |
966 | printk(KERN_WARNING "%s %s: dma not reactivated\n" , |
967 | __FILE__, __func__); |
968 | else |
969 | dma_off = 1; |
970 | } |
971 | |
972 | /* |
973 | * Disables TUSB6010. Caller must take care of locking. |
974 | */ |
975 | static void tusb_musb_disable(struct musb *musb) |
976 | { |
977 | void __iomem *tbase = musb->ctrl_base; |
978 | |
979 | /* FIXME stop DMA, IRQs, timers, ... */ |
980 | |
981 | /* disable all IRQs */ |
982 | musb_writel(addr: tbase, TUSB_INT_MASK, data: ~TUSB_INT_MASK_RESERVED_BITS); |
983 | musb_writel(addr: tbase, TUSB_USBIP_INT_MASK, data: 0x7fffffff); |
984 | musb_writel(addr: tbase, TUSB_DMA_INT_MASK, data: 0x7fffffff); |
985 | musb_writel(addr: tbase, TUSB_GPIO_INT_MASK, data: 0x1ff); |
986 | |
987 | del_timer(timer: &musb->dev_timer); |
988 | |
989 | if (is_dma_capable() && !dma_off) { |
990 | printk(KERN_WARNING "%s %s: dma still active\n" , |
991 | __FILE__, __func__); |
992 | dma_off = 1; |
993 | } |
994 | } |
995 | |
996 | /* |
997 | * Sets up TUSB6010 CPU interface specific signals and registers |
998 | * Note: Settings optimized for OMAP24xx |
999 | */ |
1000 | static void tusb_setup_cpu_interface(struct musb *musb) |
1001 | { |
1002 | void __iomem *tbase = musb->ctrl_base; |
1003 | |
1004 | /* |
1005 | * Disable GPIO[5:0] pullups (used as output DMA requests) |
1006 | * Don't disable GPIO[7:6] as they are needed for wake-up. |
1007 | */ |
1008 | musb_writel(addr: tbase, TUSB_PULLUP_1_CTRL, data: 0x0000003F); |
1009 | |
1010 | /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */ |
1011 | musb_writel(addr: tbase, TUSB_PULLUP_2_CTRL, data: 0x01FFFFFF); |
1012 | |
1013 | /* Turn GPIO[5:0] to DMAREQ[5:0] signals */ |
1014 | musb_writel(addr: tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f)); |
1015 | |
1016 | /* Burst size 16x16 bits, all six DMA requests enabled, DMA request |
1017 | * de-assertion time 2 system clocks p 62 */ |
1018 | musb_writel(addr: tbase, TUSB_DMA_REQ_CONF, |
1019 | TUSB_DMA_REQ_CONF_BURST_SIZE(2) | |
1020 | TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) | |
1021 | TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2)); |
1022 | |
1023 | /* Set 0 wait count for synchronous burst access */ |
1024 | musb_writel(addr: tbase, TUSB_WAIT_COUNT, data: 1); |
1025 | } |
1026 | |
1027 | static int tusb_musb_start(struct musb *musb) |
1028 | { |
1029 | struct tusb6010_glue *glue = dev_get_drvdata(dev: musb->controller->parent); |
1030 | void __iomem *tbase = musb->ctrl_base; |
1031 | unsigned long flags; |
1032 | u32 reg; |
1033 | int ret; |
1034 | |
1035 | /* |
1036 | * Enable or disable power to TUSB6010. When enabling, turn on 3.3 V and |
1037 | * 1.5 V voltage regulators of PM companion chip. Companion chip will then |
1038 | * provide then PGOOD signal to TUSB6010 which will release it from reset. |
1039 | */ |
1040 | gpiod_set_value(desc: glue->enable, value: 1); |
1041 | |
1042 | /* Wait for 100ms until TUSB6010 pulls INT pin down */ |
1043 | ret = read_poll_timeout(gpiod_get_value, reg, !reg, 5000, 100000, true, |
1044 | glue->intpin); |
1045 | if (ret) { |
1046 | pr_err("tusb: Powerup response failed\n" ); |
1047 | return ret; |
1048 | } |
1049 | |
1050 | spin_lock_irqsave(&musb->lock, flags); |
1051 | |
1052 | if (musb_readl(addr: tbase, TUSB_PROD_TEST_RESET) != |
1053 | TUSB_PROD_TEST_RESET_VAL) { |
1054 | printk(KERN_ERR "tusb: Unable to detect TUSB6010\n" ); |
1055 | goto err; |
1056 | } |
1057 | |
1058 | musb->tusb_revision = tusb_get_revision(musb); |
1059 | tusb_print_revision(musb); |
1060 | if (musb->tusb_revision < 2) { |
1061 | printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n" , |
1062 | musb->tusb_revision); |
1063 | goto err; |
1064 | } |
1065 | |
1066 | /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when |
1067 | * NOR FLASH interface is used */ |
1068 | musb_writel(addr: tbase, TUSB_VLYNQ_CTRL, data: 8); |
1069 | |
1070 | /* Select PHY free running 60MHz as a system clock */ |
1071 | tusb_set_clock_source(musb, mode: 1); |
1072 | |
1073 | /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for |
1074 | * power saving, enable VBus detect and session end comparators, |
1075 | * enable IDpullup, enable VBus charging */ |
1076 | musb_writel(addr: tbase, TUSB_PRCM_MNGMT, |
1077 | TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) | |
1078 | TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN | |
1079 | TUSB_PRCM_MNGMT_OTG_SESS_END_EN | |
1080 | TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN | |
1081 | TUSB_PRCM_MNGMT_OTG_ID_PULLUP); |
1082 | tusb_setup_cpu_interface(musb); |
1083 | |
1084 | /* simplify: always sense/pullup ID pins, as if in OTG mode */ |
1085 | reg = musb_readl(addr: tbase, TUSB_PHY_OTG_CTRL_ENABLE); |
1086 | reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; |
1087 | musb_writel(addr: tbase, TUSB_PHY_OTG_CTRL_ENABLE, data: reg); |
1088 | |
1089 | reg = musb_readl(addr: tbase, TUSB_PHY_OTG_CTRL); |
1090 | reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; |
1091 | musb_writel(addr: tbase, TUSB_PHY_OTG_CTRL, data: reg); |
1092 | |
1093 | spin_unlock_irqrestore(lock: &musb->lock, flags); |
1094 | |
1095 | return 0; |
1096 | |
1097 | err: |
1098 | spin_unlock_irqrestore(lock: &musb->lock, flags); |
1099 | |
1100 | gpiod_set_value(desc: glue->enable, value: 0); |
1101 | msleep(msecs: 10); |
1102 | |
1103 | return -ENODEV; |
1104 | } |
1105 | |
1106 | static int tusb_musb_init(struct musb *musb) |
1107 | { |
1108 | struct platform_device *pdev; |
1109 | struct resource *mem; |
1110 | void __iomem *sync = NULL; |
1111 | int ret; |
1112 | |
1113 | musb->xceiv = usb_get_phy(type: USB_PHY_TYPE_USB2); |
1114 | if (IS_ERR_OR_NULL(ptr: musb->xceiv)) |
1115 | return -EPROBE_DEFER; |
1116 | |
1117 | pdev = to_platform_device(musb->controller); |
1118 | |
1119 | /* dma address for async dma */ |
1120 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1121 | if (!mem) { |
1122 | pr_debug("no async dma resource?\n" ); |
1123 | ret = -ENODEV; |
1124 | goto done; |
1125 | } |
1126 | musb->async = mem->start; |
1127 | |
1128 | /* dma address for sync dma */ |
1129 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
1130 | if (!mem) { |
1131 | pr_debug("no sync dma resource?\n" ); |
1132 | ret = -ENODEV; |
1133 | goto done; |
1134 | } |
1135 | musb->sync = mem->start; |
1136 | |
1137 | sync = ioremap(offset: mem->start, size: resource_size(res: mem)); |
1138 | if (!sync) { |
1139 | pr_debug("ioremap for sync failed\n" ); |
1140 | ret = -ENOMEM; |
1141 | goto done; |
1142 | } |
1143 | musb->sync_va = sync; |
1144 | |
1145 | /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400, |
1146 | * FIFOs at 0x600, TUSB at 0x800 |
1147 | */ |
1148 | musb->mregs += TUSB_BASE_OFFSET; |
1149 | |
1150 | ret = tusb_musb_start(musb); |
1151 | if (ret) { |
1152 | printk(KERN_ERR "Could not start tusb6010 (%d)\n" , |
1153 | ret); |
1154 | goto done; |
1155 | } |
1156 | musb->isr = tusb_musb_interrupt; |
1157 | |
1158 | musb->xceiv->set_power = tusb_draw_power; |
1159 | the_musb = musb; |
1160 | |
1161 | timer_setup(&musb->dev_timer, musb_do_idle, 0); |
1162 | |
1163 | done: |
1164 | if (ret < 0) { |
1165 | if (sync) |
1166 | iounmap(addr: sync); |
1167 | |
1168 | usb_put_phy(musb->xceiv); |
1169 | } |
1170 | return ret; |
1171 | } |
1172 | |
1173 | static int tusb_musb_exit(struct musb *musb) |
1174 | { |
1175 | struct tusb6010_glue *glue = dev_get_drvdata(dev: musb->controller->parent); |
1176 | |
1177 | del_timer_sync(timer: &musb->dev_timer); |
1178 | the_musb = NULL; |
1179 | |
1180 | gpiod_set_value(desc: glue->enable, value: 0); |
1181 | msleep(msecs: 10); |
1182 | |
1183 | iounmap(addr: musb->sync_va); |
1184 | |
1185 | usb_put_phy(musb->xceiv); |
1186 | return 0; |
1187 | } |
1188 | |
1189 | static const struct musb_platform_ops tusb_ops = { |
1190 | .quirks = MUSB_DMA_TUSB_OMAP | MUSB_IN_TUSB | |
1191 | MUSB_G_NO_SKB_RESERVE, |
1192 | .init = tusb_musb_init, |
1193 | .exit = tusb_musb_exit, |
1194 | |
1195 | .ep_offset = tusb_ep_offset, |
1196 | .ep_select = tusb_ep_select, |
1197 | .fifo_offset = tusb_fifo_offset, |
1198 | .readb = tusb_readb, |
1199 | .writeb = tusb_writeb, |
1200 | .read_fifo = tusb_read_fifo, |
1201 | .write_fifo = tusb_write_fifo, |
1202 | #ifdef CONFIG_USB_TUSB_OMAP_DMA |
1203 | .dma_init = tusb_dma_controller_create, |
1204 | .dma_exit = tusb_dma_controller_destroy, |
1205 | #endif |
1206 | .enable = tusb_musb_enable, |
1207 | .disable = tusb_musb_disable, |
1208 | |
1209 | .set_mode = tusb_musb_set_mode, |
1210 | .try_idle = tusb_musb_try_idle, |
1211 | |
1212 | .vbus_status = tusb_musb_vbus_status, |
1213 | .set_vbus = tusb_musb_set_vbus, |
1214 | }; |
1215 | |
1216 | static const struct platform_device_info tusb_dev_info = { |
1217 | .name = "musb-hdrc" , |
1218 | .id = PLATFORM_DEVID_AUTO, |
1219 | .dma_mask = DMA_BIT_MASK(32), |
1220 | }; |
1221 | |
1222 | static int tusb_probe(struct platform_device *pdev) |
1223 | { |
1224 | struct resource musb_resources[3]; |
1225 | struct musb_hdrc_platform_data *pdata = dev_get_platdata(dev: &pdev->dev); |
1226 | struct platform_device *musb; |
1227 | struct tusb6010_glue *glue; |
1228 | struct platform_device_info pinfo; |
1229 | int ret; |
1230 | |
1231 | glue = devm_kzalloc(dev: &pdev->dev, size: sizeof(*glue), GFP_KERNEL); |
1232 | if (!glue) |
1233 | return -ENOMEM; |
1234 | |
1235 | glue->dev = &pdev->dev; |
1236 | |
1237 | glue->enable = devm_gpiod_get(dev: glue->dev, con_id: "enable" , flags: GPIOD_OUT_LOW); |
1238 | if (IS_ERR(ptr: glue->enable)) |
1239 | return dev_err_probe(dev: glue->dev, err: PTR_ERR(ptr: glue->enable), |
1240 | fmt: "could not obtain power on/off GPIO\n" ); |
1241 | glue->intpin = devm_gpiod_get(dev: glue->dev, con_id: "int" , flags: GPIOD_IN); |
1242 | if (IS_ERR(ptr: glue->intpin)) |
1243 | return dev_err_probe(dev: glue->dev, err: PTR_ERR(ptr: glue->intpin), |
1244 | fmt: "could not obtain INT GPIO\n" ); |
1245 | |
1246 | pdata->platform_ops = &tusb_ops; |
1247 | |
1248 | usb_phy_generic_register(); |
1249 | platform_set_drvdata(pdev, data: glue); |
1250 | |
1251 | memset(musb_resources, 0x00, sizeof(*musb_resources) * |
1252 | ARRAY_SIZE(musb_resources)); |
1253 | |
1254 | musb_resources[0].name = pdev->resource[0].name; |
1255 | musb_resources[0].start = pdev->resource[0].start; |
1256 | musb_resources[0].end = pdev->resource[0].end; |
1257 | musb_resources[0].flags = pdev->resource[0].flags; |
1258 | |
1259 | musb_resources[1].name = pdev->resource[1].name; |
1260 | musb_resources[1].start = pdev->resource[1].start; |
1261 | musb_resources[1].end = pdev->resource[1].end; |
1262 | musb_resources[1].flags = pdev->resource[1].flags; |
1263 | |
1264 | musb_resources[2] = DEFINE_RES_IRQ_NAMED(gpiod_to_irq(glue->intpin), "mc" ); |
1265 | |
1266 | pinfo = tusb_dev_info; |
1267 | pinfo.parent = &pdev->dev; |
1268 | pinfo.res = musb_resources; |
1269 | pinfo.num_res = ARRAY_SIZE(musb_resources); |
1270 | pinfo.data = pdata; |
1271 | pinfo.size_data = sizeof(*pdata); |
1272 | |
1273 | glue->musb = musb = platform_device_register_full(pdevinfo: &pinfo); |
1274 | if (IS_ERR(ptr: musb)) { |
1275 | ret = PTR_ERR(ptr: musb); |
1276 | dev_err(&pdev->dev, "failed to register musb device: %d\n" , ret); |
1277 | return ret; |
1278 | } |
1279 | |
1280 | return 0; |
1281 | } |
1282 | |
1283 | static void tusb_remove(struct platform_device *pdev) |
1284 | { |
1285 | struct tusb6010_glue *glue = platform_get_drvdata(pdev); |
1286 | |
1287 | platform_device_unregister(glue->musb); |
1288 | usb_phy_generic_unregister(glue->phy); |
1289 | } |
1290 | |
1291 | static struct platform_driver tusb_driver = { |
1292 | .probe = tusb_probe, |
1293 | .remove_new = tusb_remove, |
1294 | .driver = { |
1295 | .name = "musb-tusb" , |
1296 | }, |
1297 | }; |
1298 | |
1299 | MODULE_DESCRIPTION("TUSB6010 MUSB Glue Layer" ); |
1300 | MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>" ); |
1301 | MODULE_LICENSE("GPL v2" ); |
1302 | module_platform_driver(tusb_driver); |
1303 | |