1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
2 | /************************************************************************ |
3 | * |
4 | * 16654.H Definitions for 16C654 UART used on EdgePorts |
5 | * |
6 | * Copyright (C) 1998 Inside Out Networks, Inc. |
7 | * |
8 | ************************************************************************/ |
9 | |
10 | #if !defined(_16654_H) |
11 | #define _16654_H |
12 | |
13 | /************************************************************************ |
14 | * |
15 | * D e f i n e s / T y p e d e f s |
16 | * |
17 | ************************************************************************/ |
18 | |
19 | // |
20 | // UART register numbers |
21 | // Numbers 0-7 are passed to the Edgeport directly. Numbers 8 and |
22 | // above are used internally to indicate that we must enable access |
23 | // to them via LCR bit 0x80 or LCR = 0xBF. |
24 | // The register number sent to the Edgeport is then (x & 0x7). |
25 | // |
26 | // Driver must not access registers that affect operation of the |
27 | // the EdgePort firmware -- that includes THR, RHR, IER, FCR. |
28 | |
29 | |
30 | #define THR 0 // ! Transmit Holding Register (Write) |
31 | #define RDR 0 // ! Receive Holding Register (Read) |
32 | #define IER 1 // ! Interrupt Enable Register |
33 | #define FCR 2 // ! Fifo Control Register (Write) |
34 | #define ISR 2 // Interrupt Status Register (Read) |
35 | #define LCR 3 // Line Control Register |
36 | #define MCR 4 // Modem Control Register |
37 | #define LSR 5 // Line Status Register |
38 | #define MSR 6 // Modem Status Register |
39 | #define SPR 7 // ScratchPad Register |
40 | #define DLL 8 // Bank2[ 0 ] Divisor Latch LSB |
41 | #define DLM 9 // Bank2[ 1 ] Divisor Latch MSB |
42 | #define EFR 10 // Bank2[ 2 ] Extended Function Register |
43 | //efine unused 11 // Bank2[ 3 ] |
44 | #define XON1 12 // Bank2[ 4 ] Xon-1 |
45 | #define XON2 13 // Bank2[ 5 ] Xon-2 |
46 | #define XOFF1 14 // Bank2[ 6 ] Xoff-1 |
47 | #define XOFF2 15 // Bank2[ 7 ] Xoff-2 |
48 | |
49 | #define NUM_16654_REGS 16 |
50 | |
51 | #define IS_REG_2ND_BANK(x) ((x) >= 8) |
52 | |
53 | // |
54 | // Bit definitions for each register |
55 | // |
56 | |
57 | #define IER_RX 0x01 // Enable receive interrupt |
58 | #define IER_TX 0x02 // Enable transmit interrupt |
59 | #define IER_RXS 0x04 // Enable receive status interrupt |
60 | #define IER_MDM 0x08 // Enable modem status interrupt |
61 | #define IER_SLEEP 0x10 // Enable sleep mode |
62 | #define IER_XOFF 0x20 // Enable s/w flow control (XOFF) interrupt |
63 | #define IER_RTS 0x40 // Enable RTS interrupt |
64 | #define IER_CTS 0x80 // Enable CTS interrupt |
65 | #define IER_ENABLE_ALL 0xFF // Enable all ints |
66 | |
67 | |
68 | #define FCR_FIFO_EN 0x01 // Enable FIFOs |
69 | #define FCR_RXCLR 0x02 // Reset Rx FIFO |
70 | #define FCR_TXCLR 0x04 // Reset Tx FIFO |
71 | #define FCR_DMA_BLK 0x08 // Enable DMA block mode |
72 | #define FCR_TX_LEVEL_MASK 0x30 // Mask for Tx FIFO Level |
73 | #define FCR_TX_LEVEL_8 0x00 // Tx FIFO Level = 8 bytes |
74 | #define FCR_TX_LEVEL_16 0x10 // Tx FIFO Level = 16 bytes |
75 | #define FCR_TX_LEVEL_32 0x20 // Tx FIFO Level = 32 bytes |
76 | #define FCR_TX_LEVEL_56 0x30 // Tx FIFO Level = 56 bytes |
77 | #define FCR_RX_LEVEL_MASK 0xC0 // Mask for Rx FIFO Level |
78 | #define FCR_RX_LEVEL_8 0x00 // Rx FIFO Level = 8 bytes |
79 | #define FCR_RX_LEVEL_16 0x40 // Rx FIFO Level = 16 bytes |
80 | #define FCR_RX_LEVEL_56 0x80 // Rx FIFO Level = 56 bytes |
81 | #define FCR_RX_LEVEL_60 0xC0 // Rx FIFO Level = 60 bytes |
82 | |
83 | |
84 | #define ISR_INT_MDM_STATUS 0x00 // Modem status int pending |
85 | #define ISR_INT_NONE 0x01 // No interrupt pending |
86 | #define ISR_INT_TXRDY 0x02 // Tx ready int pending |
87 | #define ISR_INT_RXRDY 0x04 // Rx ready int pending |
88 | #define ISR_INT_LINE_STATUS 0x06 // Line status int pending |
89 | #define ISR_INT_RX_TIMEOUT 0x0C // Rx timeout int pending |
90 | #define ISR_INT_RX_XOFF 0x10 // Rx Xoff int pending |
91 | #define ISR_INT_RTS_CTS 0x20 // RTS/CTS change int pending |
92 | #define ISR_FIFO_ENABLED 0xC0 // Bits set if FIFOs enabled |
93 | #define ISR_INT_BITS_MASK 0x3E // Mask to isolate valid int causes |
94 | |
95 | |
96 | #define LCR_BITS_5 0x00 // 5 bits/char |
97 | #define LCR_BITS_6 0x01 // 6 bits/char |
98 | #define LCR_BITS_7 0x02 // 7 bits/char |
99 | #define LCR_BITS_8 0x03 // 8 bits/char |
100 | #define LCR_BITS_MASK 0x03 // Mask for bits/char field |
101 | |
102 | #define LCR_STOP_1 0x00 // 1 stop bit |
103 | #define LCR_STOP_1_5 0x04 // 1.5 stop bits (if 5 bits/char) |
104 | #define LCR_STOP_2 0x04 // 2 stop bits (if 6-8 bits/char) |
105 | #define LCR_STOP_MASK 0x04 // Mask for stop bits field |
106 | |
107 | #define LCR_PAR_NONE 0x00 // No parity |
108 | #define LCR_PAR_ODD 0x08 // Odd parity |
109 | #define LCR_PAR_EVEN 0x18 // Even parity |
110 | #define LCR_PAR_MARK 0x28 // Force parity bit to 1 |
111 | #define LCR_PAR_SPACE 0x38 // Force parity bit to 0 |
112 | #define LCR_PAR_MASK 0x38 // Mask for parity field |
113 | |
114 | #define LCR_SET_BREAK 0x40 // Set Break condition |
115 | #define LCR_DL_ENABLE 0x80 // Enable access to divisor latch |
116 | |
117 | #define LCR_ACCESS_EFR 0xBF // Load this value to access DLL,DLM, |
118 | // and also the '654-only registers |
119 | // EFR, XON1, XON2, XOFF1, XOFF2 |
120 | |
121 | |
122 | #define MCR_DTR 0x01 // Assert DTR |
123 | #define MCR_RTS 0x02 // Assert RTS |
124 | #define MCR_OUT1 0x04 // Loopback only: Sets state of RI |
125 | #define MCR_MASTER_IE 0x08 // Enable interrupt outputs |
126 | #define MCR_LOOPBACK 0x10 // Set internal (digital) loopback mode |
127 | #define MCR_XON_ANY 0x20 // Enable any char to exit XOFF mode |
128 | #define MCR_IR_ENABLE 0x40 // Enable IrDA functions |
129 | #define MCR_BRG_DIV_4 0x80 // Divide baud rate clk by /4 instead of /1 |
130 | |
131 | |
132 | #define LSR_RX_AVAIL 0x01 // Rx data available |
133 | #define LSR_OVER_ERR 0x02 // Rx overrun |
134 | #define LSR_PAR_ERR 0x04 // Rx parity error |
135 | #define LSR_FRM_ERR 0x08 // Rx framing error |
136 | #define LSR_BREAK 0x10 // Rx break condition detected |
137 | #define LSR_TX_EMPTY 0x20 // Tx Fifo empty |
138 | #define LSR_TX_ALL_EMPTY 0x40 // Tx Fifo and shift register empty |
139 | #define LSR_FIFO_ERR 0x80 // Rx Fifo contains at least 1 erred char |
140 | |
141 | |
142 | #define EDGEPORT_MSR_DELTA_CTS 0x01 // CTS changed from last read |
143 | #define EDGEPORT_MSR_DELTA_DSR 0x02 // DSR changed from last read |
144 | #define EDGEPORT_MSR_DELTA_RI 0x04 // RI changed from 0 -> 1 |
145 | #define EDGEPORT_MSR_DELTA_CD 0x08 // CD changed from last read |
146 | #define EDGEPORT_MSR_CTS 0x10 // Current state of CTS |
147 | #define EDGEPORT_MSR_DSR 0x20 // Current state of DSR |
148 | #define EDGEPORT_MSR_RI 0x40 // Current state of RI |
149 | #define EDGEPORT_MSR_CD 0x80 // Current state of CD |
150 | |
151 | |
152 | |
153 | // Tx Rx |
154 | //------------------------------- |
155 | #define EFR_SWFC_NONE 0x00 // None None |
156 | #define EFR_SWFC_RX1 0x02 // None XOFF1 |
157 | #define EFR_SWFC_RX2 0x01 // None XOFF2 |
158 | #define EFR_SWFC_RX12 0x03 // None XOFF1 & XOFF2 |
159 | #define EFR_SWFC_TX1 0x08 // XOFF1 None |
160 | #define EFR_SWFC_TX1_RX1 0x0a // XOFF1 XOFF1 |
161 | #define EFR_SWFC_TX1_RX2 0x09 // XOFF1 XOFF2 |
162 | #define EFR_SWFC_TX1_RX12 0x0b // XOFF1 XOFF1 & XOFF2 |
163 | #define EFR_SWFC_TX2 0x04 // XOFF2 None |
164 | #define EFR_SWFC_TX2_RX1 0x06 // XOFF2 XOFF1 |
165 | #define EFR_SWFC_TX2_RX2 0x05 // XOFF2 XOFF2 |
166 | #define EFR_SWFC_TX2_RX12 0x07 // XOFF2 XOFF1 & XOFF2 |
167 | #define EFR_SWFC_TX12 0x0c // XOFF1 & XOFF2 None |
168 | #define EFR_SWFC_TX12_RX1 0x0e // XOFF1 & XOFF2 XOFF1 |
169 | #define EFR_SWFC_TX12_RX2 0x0d // XOFF1 & XOFF2 XOFF2 |
170 | #define EFR_SWFC_TX12_RX12 0x0f // XOFF1 & XOFF2 XOFF1 & XOFF2 |
171 | |
172 | #define EFR_TX_FC_MASK 0x0c // Mask to isolate Rx flow control |
173 | #define EFR_TX_FC_NONE 0x00 // No Tx Xon/Xoff flow control |
174 | #define EFR_TX_FC_X1 0x08 // Transmit Xon1/Xoff1 |
175 | #define EFR_TX_FC_X2 0x04 // Transmit Xon2/Xoff2 |
176 | #define EFR_TX_FC_X1_2 0x0c // Transmit Xon1&2/Xoff1&2 |
177 | |
178 | #define EFR_RX_FC_MASK 0x03 // Mask to isolate Rx flow control |
179 | #define EFR_RX_FC_NONE 0x00 // No Rx Xon/Xoff flow control |
180 | #define EFR_RX_FC_X1 0x02 // Receiver compares Xon1/Xoff1 |
181 | #define EFR_RX_FC_X2 0x01 // Receiver compares Xon2/Xoff2 |
182 | #define EFR_RX_FC_X1_2 0x03 // Receiver compares Xon1&2/Xoff1&2 |
183 | |
184 | |
185 | #define EFR_SWFC_MASK 0x0F // Mask for software flow control field |
186 | #define EFR_ENABLE_16654 0x10 // Enable 16C654 features |
187 | #define EFR_SPEC_DETECT 0x20 // Enable special character detect interrupt |
188 | #define EFR_AUTO_RTS 0x40 // Use RTS for Rx flow control |
189 | #define EFR_AUTO_CTS 0x80 // Use CTS for Tx flow control |
190 | |
191 | #endif // if !defined(_16654_H) |
192 | |
193 | |