1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* $Id: aty128fb.c,v 1.1.1.1.36.1 1999/12/11 09:03:05 Exp $ |
3 | * linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128 |
4 | * |
5 | * Copyright (C) 1999-2003, Brad Douglas <brad@neruo.com> |
6 | * Copyright (C) 1999, Anthony Tong <atong@uiuc.edu> |
7 | * |
8 | * Ani Joshi / Jeff Garzik |
9 | * - Code cleanup |
10 | * |
11 | * Michel Danzer <michdaen@iiic.ethz.ch> |
12 | * - 15/16 bit cleanup |
13 | * - fix panning |
14 | * |
15 | * Benjamin Herrenschmidt |
16 | * - pmac-specific PM stuff |
17 | * - various fixes & cleanups |
18 | * |
19 | * Andreas Hundt <andi@convergence.de> |
20 | * - FB_ACTIVATE fixes |
21 | * |
22 | * Paul Mackerras <paulus@samba.org> |
23 | * - Convert to new framebuffer API, |
24 | * fix colormap setting at 16 bits/pixel (565) |
25 | * |
26 | * Paul Mundt |
27 | * - PCI hotplug |
28 | * |
29 | * Jon Smirl <jonsmirl@yahoo.com> |
30 | * - PCI ID update |
31 | * - replace ROM BIOS search |
32 | * |
33 | * Based off of Geert's atyfb.c and vfb.c. |
34 | * |
35 | * TODO: |
36 | * - monitor sensing (DDC) |
37 | * - virtual display |
38 | * - other platform support (only ppc/x86 supported) |
39 | * - hardware cursor support |
40 | * |
41 | * Please cc: your patches to brad@neruo.com. |
42 | */ |
43 | |
44 | /* |
45 | * A special note of gratitude to ATI's devrel for providing documentation, |
46 | * example code and hardware. Thanks Nitya. -atong and brad |
47 | */ |
48 | |
49 | |
50 | #include <linux/aperture.h> |
51 | #include <linux/module.h> |
52 | #include <linux/moduleparam.h> |
53 | #include <linux/kernel.h> |
54 | #include <linux/errno.h> |
55 | #include <linux/string.h> |
56 | #include <linux/mm.h> |
57 | #include <linux/vmalloc.h> |
58 | #include <linux/delay.h> |
59 | #include <linux/interrupt.h> |
60 | #include <linux/uaccess.h> |
61 | #include <linux/fb.h> |
62 | #include <linux/init.h> |
63 | #include <linux/pci.h> |
64 | #include <linux/ioport.h> |
65 | #include <linux/console.h> |
66 | #include <linux/backlight.h> |
67 | #include <asm/io.h> |
68 | |
69 | #ifdef CONFIG_PPC_PMAC |
70 | #include <asm/machdep.h> |
71 | #include <asm/pmac_feature.h> |
72 | #include "../macmodes.h" |
73 | #endif |
74 | |
75 | #ifdef CONFIG_PMAC_BACKLIGHT |
76 | #include <asm/backlight.h> |
77 | #endif |
78 | |
79 | #ifdef CONFIG_BOOTX_TEXT |
80 | #include <asm/btext.h> |
81 | #endif /* CONFIG_BOOTX_TEXT */ |
82 | |
83 | #include <video/aty128.h> |
84 | |
85 | /* Debug flag */ |
86 | #undef DEBUG |
87 | |
88 | #ifdef DEBUG |
89 | #define DBG(fmt, args...) \ |
90 | printk(KERN_DEBUG "aty128fb: %s " fmt, __func__, ##args); |
91 | #else |
92 | #define DBG(fmt, args...) |
93 | #endif |
94 | |
95 | #ifndef CONFIG_PPC_PMAC |
96 | /* default mode */ |
97 | static const struct fb_var_screeninfo default_var = { |
98 | /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */ |
99 | 640, 480, 640, 480, 0, 0, 8, 0, |
100 | {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, |
101 | 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2, |
102 | 0, FB_VMODE_NONINTERLACED |
103 | }; |
104 | |
105 | #else /* CONFIG_PPC_PMAC */ |
106 | /* default to 1024x768 at 75Hz on PPC - this will work |
107 | * on the iMac, the usual 640x480 @ 60Hz doesn't. */ |
108 | static const struct fb_var_screeninfo default_var = { |
109 | /* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */ |
110 | 1024, 768, 1024, 768, 0, 0, 8, 0, |
111 | {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, |
112 | 0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3, |
113 | FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, |
114 | FB_VMODE_NONINTERLACED |
115 | }; |
116 | #endif /* CONFIG_PPC_PMAC */ |
117 | |
118 | /* default modedb mode */ |
119 | /* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */ |
120 | static const struct fb_videomode defaultmode = { |
121 | .refresh = 60, |
122 | .xres = 640, |
123 | .yres = 480, |
124 | .pixclock = 39722, |
125 | .left_margin = 48, |
126 | .right_margin = 16, |
127 | .upper_margin = 33, |
128 | .lower_margin = 10, |
129 | .hsync_len = 96, |
130 | .vsync_len = 2, |
131 | .sync = 0, |
132 | .vmode = FB_VMODE_NONINTERLACED |
133 | }; |
134 | |
135 | /* Chip generations */ |
136 | enum { |
137 | rage_128, |
138 | rage_128_pci, |
139 | rage_128_pro, |
140 | rage_128_pro_pci, |
141 | rage_M3, |
142 | rage_M3_pci, |
143 | rage_M4, |
144 | rage_128_ultra, |
145 | }; |
146 | |
147 | /* Must match above enum */ |
148 | static char * const r128_family[] = { |
149 | "AGP" , |
150 | "PCI" , |
151 | "PRO AGP" , |
152 | "PRO PCI" , |
153 | "M3 AGP" , |
154 | "M3 PCI" , |
155 | "M4 AGP" , |
156 | "Ultra AGP" , |
157 | }; |
158 | |
159 | /* |
160 | * PCI driver prototypes |
161 | */ |
162 | static int aty128_probe(struct pci_dev *pdev, |
163 | const struct pci_device_id *ent); |
164 | static void aty128_remove(struct pci_dev *pdev); |
165 | static int aty128_pci_suspend_late(struct device *dev, pm_message_t state); |
166 | static int __maybe_unused aty128_pci_suspend(struct device *dev); |
167 | static int __maybe_unused aty128_pci_hibernate(struct device *dev); |
168 | static int __maybe_unused aty128_pci_freeze(struct device *dev); |
169 | static int __maybe_unused aty128_pci_resume(struct device *dev); |
170 | static int aty128_do_resume(struct pci_dev *pdev); |
171 | |
172 | static const struct dev_pm_ops aty128_pci_pm_ops = { |
173 | .suspend = aty128_pci_suspend, |
174 | .resume = aty128_pci_resume, |
175 | .freeze = aty128_pci_freeze, |
176 | .thaw = aty128_pci_resume, |
177 | .poweroff = aty128_pci_hibernate, |
178 | .restore = aty128_pci_resume, |
179 | }; |
180 | |
181 | /* supported Rage128 chipsets */ |
182 | static const struct pci_device_id aty128_pci_tbl[] = { |
183 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LE, |
184 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3_pci }, |
185 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LF, |
186 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3 }, |
187 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_MF, |
188 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 }, |
189 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_ML, |
190 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 }, |
191 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PA, |
192 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, |
193 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PB, |
194 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, |
195 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PC, |
196 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, |
197 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PD, |
198 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci }, |
199 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PE, |
200 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, |
201 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PF, |
202 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, |
203 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PG, |
204 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, |
205 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PH, |
206 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, |
207 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PI, |
208 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, |
209 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PJ, |
210 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, |
211 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PK, |
212 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, |
213 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PL, |
214 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, |
215 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PM, |
216 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, |
217 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PN, |
218 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, |
219 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PO, |
220 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, |
221 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PP, |
222 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci }, |
223 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PQ, |
224 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, |
225 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PR, |
226 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci }, |
227 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PS, |
228 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, |
229 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PT, |
230 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, |
231 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PU, |
232 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, |
233 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PV, |
234 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, |
235 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PW, |
236 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, |
237 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PX, |
238 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, |
239 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RE, |
240 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci }, |
241 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RF, |
242 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, |
243 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RG, |
244 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, |
245 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RK, |
246 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci }, |
247 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RL, |
248 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, |
249 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SE, |
250 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, |
251 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SF, |
252 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci }, |
253 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SG, |
254 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, |
255 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SH, |
256 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, |
257 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SK, |
258 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, |
259 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SL, |
260 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, |
261 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SM, |
262 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, |
263 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SN, |
264 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, |
265 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TF, |
266 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, |
267 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TL, |
268 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, |
269 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TR, |
270 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, |
271 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TS, |
272 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, |
273 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TT, |
274 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, |
275 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TU, |
276 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, |
277 | { 0, } |
278 | }; |
279 | |
280 | MODULE_DEVICE_TABLE(pci, aty128_pci_tbl); |
281 | |
282 | static struct pci_driver aty128fb_driver = { |
283 | .name = "aty128fb" , |
284 | .id_table = aty128_pci_tbl, |
285 | .probe = aty128_probe, |
286 | .remove = aty128_remove, |
287 | .driver.pm = &aty128_pci_pm_ops, |
288 | }; |
289 | |
290 | /* packed BIOS settings */ |
291 | #ifndef CONFIG_PPC |
292 | typedef struct { |
293 | u8 clock_chip_type; |
294 | u8 struct_size; |
295 | u8 accelerator_entry; |
296 | u8 VGA_entry; |
297 | u16 VGA_table_offset; |
298 | u16 POST_table_offset; |
299 | u16 XCLK; |
300 | u16 MCLK; |
301 | u8 num_PLL_blocks; |
302 | u8 size_PLL_blocks; |
303 | u16 PCLK_ref_freq; |
304 | u16 PCLK_ref_divider; |
305 | u32 PCLK_min_freq; |
306 | u32 PCLK_max_freq; |
307 | u16 MCLK_ref_freq; |
308 | u16 MCLK_ref_divider; |
309 | u32 MCLK_min_freq; |
310 | u32 MCLK_max_freq; |
311 | u16 XCLK_ref_freq; |
312 | u16 XCLK_ref_divider; |
313 | u32 XCLK_min_freq; |
314 | u32 XCLK_max_freq; |
315 | } __attribute__ ((packed)) PLL_BLOCK; |
316 | #endif /* !CONFIG_PPC */ |
317 | |
318 | /* onboard memory information */ |
319 | struct aty128_meminfo { |
320 | u8 ML; |
321 | u8 MB; |
322 | u8 Trcd; |
323 | u8 Trp; |
324 | u8 Twr; |
325 | u8 CL; |
326 | u8 Tr2w; |
327 | u8 LoopLatency; |
328 | u8 DspOn; |
329 | u8 Rloop; |
330 | const char *name; |
331 | }; |
332 | |
333 | /* various memory configurations */ |
334 | static const struct aty128_meminfo sdr_128 = { |
335 | .ML = 4, |
336 | .MB = 4, |
337 | .Trcd = 3, |
338 | .Trp = 3, |
339 | .Twr = 1, |
340 | .CL = 3, |
341 | .Tr2w = 1, |
342 | .LoopLatency = 16, |
343 | .DspOn = 30, |
344 | .Rloop = 16, |
345 | .name = "128-bit SDR SGRAM (1:1)" , |
346 | }; |
347 | |
348 | static const struct aty128_meminfo sdr_sgram = { |
349 | .ML = 4, |
350 | .MB = 4, |
351 | .Trcd = 1, |
352 | .Trp = 2, |
353 | .Twr = 1, |
354 | .CL = 2, |
355 | .Tr2w = 1, |
356 | .LoopLatency = 16, |
357 | .DspOn = 24, |
358 | .Rloop = 16, |
359 | .name = "64-bit SDR SGRAM (2:1)" , |
360 | }; |
361 | |
362 | static const struct aty128_meminfo ddr_sgram = { |
363 | .ML = 4, |
364 | .MB = 4, |
365 | .Trcd = 3, |
366 | .Trp = 3, |
367 | .Twr = 2, |
368 | .CL = 3, |
369 | .Tr2w = 1, |
370 | .LoopLatency = 16, |
371 | .DspOn = 31, |
372 | .Rloop = 16, |
373 | .name = "64-bit DDR SGRAM" , |
374 | }; |
375 | |
376 | static const struct fb_fix_screeninfo aty128fb_fix = { |
377 | .id = "ATY Rage128" , |
378 | .type = FB_TYPE_PACKED_PIXELS, |
379 | .visual = FB_VISUAL_PSEUDOCOLOR, |
380 | .xpanstep = 8, |
381 | .ypanstep = 1, |
382 | .mmio_len = 0x2000, |
383 | .accel = FB_ACCEL_ATI_RAGE128, |
384 | }; |
385 | |
386 | static char *mode_option = NULL; |
387 | |
388 | #ifdef CONFIG_PPC_PMAC |
389 | static int default_vmode = VMODE_1024_768_60; |
390 | static int default_cmode = CMODE_8; |
391 | #endif |
392 | |
393 | static int default_crt_on = 0; |
394 | static int default_lcd_on = 1; |
395 | static bool mtrr = true; |
396 | |
397 | #ifdef CONFIG_FB_ATY128_BACKLIGHT |
398 | static int backlight = IS_BUILTIN(CONFIG_PMAC_BACKLIGHT); |
399 | #endif |
400 | |
401 | /* PLL constants */ |
402 | struct aty128_constants { |
403 | u32 ref_clk; |
404 | u32 ppll_min; |
405 | u32 ppll_max; |
406 | u32 ref_divider; |
407 | u32 xclk; |
408 | u32 fifo_width; |
409 | u32 fifo_depth; |
410 | }; |
411 | |
412 | struct aty128_crtc { |
413 | u32 gen_cntl; |
414 | u32 h_total, h_sync_strt_wid; |
415 | u32 v_total, v_sync_strt_wid; |
416 | u32 pitch; |
417 | u32 offset, offset_cntl; |
418 | u32 xoffset, yoffset; |
419 | u32 vxres, vyres; |
420 | u32 depth, bpp; |
421 | }; |
422 | |
423 | struct aty128_pll { |
424 | u32 post_divider; |
425 | u32 feedback_divider; |
426 | u32 vclk; |
427 | }; |
428 | |
429 | struct aty128_ddafifo { |
430 | u32 dda_config; |
431 | u32 dda_on_off; |
432 | }; |
433 | |
434 | /* register values for a specific mode */ |
435 | struct aty128fb_par { |
436 | struct aty128_crtc crtc; |
437 | struct aty128_pll pll; |
438 | struct aty128_ddafifo fifo_reg; |
439 | u32 accel_flags; |
440 | struct aty128_constants constants; /* PLL and others */ |
441 | void __iomem *regbase; /* remapped mmio */ |
442 | u32 vram_size; /* onboard video ram */ |
443 | int chip_gen; |
444 | const struct aty128_meminfo *mem; /* onboard mem info */ |
445 | int wc_cookie; |
446 | int blitter_may_be_busy; |
447 | int fifo_slots; /* free slots in FIFO (64 max) */ |
448 | |
449 | int crt_on, lcd_on; |
450 | struct pci_dev *pdev; |
451 | struct fb_info *next; |
452 | int asleep; |
453 | int lock_blank; |
454 | |
455 | u8 red[32]; /* see aty128fb_setcolreg */ |
456 | u8 green[64]; |
457 | u8 blue[32]; |
458 | u32 pseudo_palette[16]; /* used for TRUECOLOR */ |
459 | }; |
460 | |
461 | |
462 | #define round_div(n, d) ((n+(d/2))/d) |
463 | |
464 | static int aty128fb_check_var(struct fb_var_screeninfo *var, |
465 | struct fb_info *info); |
466 | static int aty128fb_set_par(struct fb_info *info); |
467 | static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, |
468 | u_int transp, struct fb_info *info); |
469 | static int aty128fb_pan_display(struct fb_var_screeninfo *var, |
470 | struct fb_info *fb); |
471 | static int aty128fb_blank(int blank, struct fb_info *fb); |
472 | static int aty128fb_ioctl(struct fb_info *info, u_int cmd, unsigned long arg); |
473 | static int aty128fb_sync(struct fb_info *info); |
474 | |
475 | /* |
476 | * Internal routines |
477 | */ |
478 | |
479 | static int aty128_encode_var(struct fb_var_screeninfo *var, |
480 | const struct aty128fb_par *par); |
481 | static int aty128_decode_var(struct fb_var_screeninfo *var, |
482 | struct aty128fb_par *par); |
483 | static void aty128_timings(struct aty128fb_par *par); |
484 | static void aty128_init_engine(struct aty128fb_par *par); |
485 | static void aty128_reset_engine(const struct aty128fb_par *par); |
486 | static void aty128_flush_pixel_cache(const struct aty128fb_par *par); |
487 | static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par); |
488 | static void wait_for_fifo(u16 entries, struct aty128fb_par *par); |
489 | static void wait_for_idle(struct aty128fb_par *par); |
490 | static u32 depth_to_dst(u32 depth); |
491 | |
492 | #ifdef CONFIG_FB_ATY128_BACKLIGHT |
493 | static void aty128_bl_set_power(struct fb_info *info, int power); |
494 | #endif |
495 | |
496 | #define BIOS_IN8(v) (readb(bios + (v))) |
497 | #define BIOS_IN16(v) (readb(bios + (v)) | \ |
498 | (readb(bios + (v) + 1) << 8)) |
499 | #define BIOS_IN32(v) (readb(bios + (v)) | \ |
500 | (readb(bios + (v) + 1) << 8) | \ |
501 | (readb(bios + (v) + 2) << 16) | \ |
502 | (readb(bios + (v) + 3) << 24)) |
503 | |
504 | |
505 | static const struct fb_ops aty128fb_ops = { |
506 | .owner = THIS_MODULE, |
507 | FB_DEFAULT_IOMEM_OPS, |
508 | .fb_check_var = aty128fb_check_var, |
509 | .fb_set_par = aty128fb_set_par, |
510 | .fb_setcolreg = aty128fb_setcolreg, |
511 | .fb_pan_display = aty128fb_pan_display, |
512 | .fb_blank = aty128fb_blank, |
513 | .fb_ioctl = aty128fb_ioctl, |
514 | .fb_sync = aty128fb_sync, |
515 | }; |
516 | |
517 | /* |
518 | * Functions to read from/write to the mmio registers |
519 | * - endian conversions may possibly be avoided by |
520 | * using the other register aperture. TODO. |
521 | */ |
522 | static inline u32 _aty_ld_le32(volatile unsigned int regindex, |
523 | const struct aty128fb_par *par) |
524 | { |
525 | return readl (addr: par->regbase + regindex); |
526 | } |
527 | |
528 | static inline void _aty_st_le32(volatile unsigned int regindex, u32 val, |
529 | const struct aty128fb_par *par) |
530 | { |
531 | writel (val, addr: par->regbase + regindex); |
532 | } |
533 | |
534 | static inline u8 _aty_ld_8(unsigned int regindex, |
535 | const struct aty128fb_par *par) |
536 | { |
537 | return readb (addr: par->regbase + regindex); |
538 | } |
539 | |
540 | static inline void _aty_st_8(unsigned int regindex, u8 val, |
541 | const struct aty128fb_par *par) |
542 | { |
543 | writeb (val, addr: par->regbase + regindex); |
544 | } |
545 | |
546 | #define aty_ld_le32(regindex) _aty_ld_le32(regindex, par) |
547 | #define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, par) |
548 | #define aty_ld_8(regindex) _aty_ld_8(regindex, par) |
549 | #define aty_st_8(regindex, val) _aty_st_8(regindex, val, par) |
550 | |
551 | /* |
552 | * Functions to read from/write to the pll registers |
553 | */ |
554 | |
555 | #define aty_ld_pll(pll_index) _aty_ld_pll(pll_index, par) |
556 | #define aty_st_pll(pll_index, val) _aty_st_pll(pll_index, val, par) |
557 | |
558 | |
559 | static u32 _aty_ld_pll(unsigned int pll_index, |
560 | const struct aty128fb_par *par) |
561 | { |
562 | aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x3F); |
563 | return aty_ld_le32(CLOCK_CNTL_DATA); |
564 | } |
565 | |
566 | |
567 | static void _aty_st_pll(unsigned int pll_index, u32 val, |
568 | const struct aty128fb_par *par) |
569 | { |
570 | aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN); |
571 | aty_st_le32(CLOCK_CNTL_DATA, val); |
572 | } |
573 | |
574 | |
575 | /* return true when the PLL has completed an atomic update */ |
576 | static int aty_pll_readupdate(const struct aty128fb_par *par) |
577 | { |
578 | return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); |
579 | } |
580 | |
581 | |
582 | static void aty_pll_wait_readupdate(const struct aty128fb_par *par) |
583 | { |
584 | unsigned long timeout = jiffies + HZ/100; // should be more than enough |
585 | int reset = 1; |
586 | |
587 | while (time_before(jiffies, timeout)) |
588 | if (aty_pll_readupdate(par)) { |
589 | reset = 0; |
590 | break; |
591 | } |
592 | |
593 | if (reset) /* reset engine?? */ |
594 | printk(KERN_DEBUG "aty128fb: PLL write timeout!\n" ); |
595 | } |
596 | |
597 | |
598 | /* tell PLL to update */ |
599 | static void aty_pll_writeupdate(const struct aty128fb_par *par) |
600 | { |
601 | aty_pll_wait_readupdate(par); |
602 | |
603 | aty_st_pll(PPLL_REF_DIV, |
604 | aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W); |
605 | } |
606 | |
607 | |
608 | /* write to the scratch register to test r/w functionality */ |
609 | static int register_test(const struct aty128fb_par *par) |
610 | { |
611 | u32 val; |
612 | int flag = 0; |
613 | |
614 | val = aty_ld_le32(BIOS_0_SCRATCH); |
615 | |
616 | aty_st_le32(BIOS_0_SCRATCH, 0x55555555); |
617 | if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) { |
618 | aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA); |
619 | |
620 | if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA) |
621 | flag = 1; |
622 | } |
623 | |
624 | aty_st_le32(BIOS_0_SCRATCH, val); // restore value |
625 | return flag; |
626 | } |
627 | |
628 | |
629 | /* |
630 | * Accelerator engine functions |
631 | */ |
632 | static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par) |
633 | { |
634 | int i; |
635 | |
636 | for (;;) { |
637 | for (i = 0; i < 2000000; i++) { |
638 | par->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff; |
639 | if (par->fifo_slots >= entries) |
640 | return; |
641 | } |
642 | aty128_reset_engine(par); |
643 | } |
644 | } |
645 | |
646 | |
647 | static void wait_for_idle(struct aty128fb_par *par) |
648 | { |
649 | int i; |
650 | |
651 | do_wait_for_fifo(entries: 64, par); |
652 | |
653 | for (;;) { |
654 | for (i = 0; i < 2000000; i++) { |
655 | if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) { |
656 | aty128_flush_pixel_cache(par); |
657 | par->blitter_may_be_busy = 0; |
658 | return; |
659 | } |
660 | } |
661 | aty128_reset_engine(par); |
662 | } |
663 | } |
664 | |
665 | |
666 | static void wait_for_fifo(u16 entries, struct aty128fb_par *par) |
667 | { |
668 | if (par->fifo_slots < entries) |
669 | do_wait_for_fifo(entries: 64, par); |
670 | par->fifo_slots -= entries; |
671 | } |
672 | |
673 | |
674 | static void aty128_flush_pixel_cache(const struct aty128fb_par *par) |
675 | { |
676 | int i; |
677 | u32 tmp; |
678 | |
679 | tmp = aty_ld_le32(PC_NGUI_CTLSTAT); |
680 | tmp &= ~(0x00ff); |
681 | tmp |= 0x00ff; |
682 | aty_st_le32(PC_NGUI_CTLSTAT, tmp); |
683 | |
684 | for (i = 0; i < 2000000; i++) |
685 | if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY)) |
686 | break; |
687 | } |
688 | |
689 | |
690 | static void aty128_reset_engine(const struct aty128fb_par *par) |
691 | { |
692 | u32 gen_reset_cntl, clock_cntl_index, mclk_cntl; |
693 | |
694 | aty128_flush_pixel_cache(par); |
695 | |
696 | clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX); |
697 | mclk_cntl = aty_ld_pll(MCLK_CNTL); |
698 | |
699 | aty_st_pll(MCLK_CNTL, mclk_cntl | 0x00030000); |
700 | |
701 | gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL); |
702 | aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI); |
703 | aty_ld_le32(GEN_RESET_CNTL); |
704 | aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI)); |
705 | aty_ld_le32(GEN_RESET_CNTL); |
706 | |
707 | aty_st_pll(MCLK_CNTL, mclk_cntl); |
708 | aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index); |
709 | aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl); |
710 | |
711 | /* use old pio mode */ |
712 | aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4); |
713 | |
714 | DBG("engine reset" ); |
715 | } |
716 | |
717 | |
718 | static void aty128_init_engine(struct aty128fb_par *par) |
719 | { |
720 | u32 pitch_value; |
721 | |
722 | wait_for_idle(par); |
723 | |
724 | /* 3D scaler not spoken here */ |
725 | wait_for_fifo(entries: 1, par); |
726 | aty_st_le32(SCALE_3D_CNTL, 0x00000000); |
727 | |
728 | aty128_reset_engine(par); |
729 | |
730 | pitch_value = par->crtc.pitch; |
731 | if (par->crtc.bpp == 24) { |
732 | pitch_value = pitch_value * 3; |
733 | } |
734 | |
735 | wait_for_fifo(entries: 4, par); |
736 | /* setup engine offset registers */ |
737 | aty_st_le32(DEFAULT_OFFSET, 0x00000000); |
738 | |
739 | /* setup engine pitch registers */ |
740 | aty_st_le32(DEFAULT_PITCH, pitch_value); |
741 | |
742 | /* set the default scissor register to max dimensions */ |
743 | aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF); |
744 | |
745 | /* set the drawing controls registers */ |
746 | aty_st_le32(DP_GUI_MASTER_CNTL, |
747 | GMC_SRC_PITCH_OFFSET_DEFAULT | |
748 | GMC_DST_PITCH_OFFSET_DEFAULT | |
749 | GMC_SRC_CLIP_DEFAULT | |
750 | GMC_DST_CLIP_DEFAULT | |
751 | GMC_BRUSH_SOLIDCOLOR | |
752 | (depth_to_dst(par->crtc.depth) << 8) | |
753 | GMC_SRC_DSTCOLOR | |
754 | GMC_BYTE_ORDER_MSB_TO_LSB | |
755 | GMC_DP_CONVERSION_TEMP_6500 | |
756 | ROP3_PATCOPY | |
757 | GMC_DP_SRC_RECT | |
758 | GMC_3D_FCN_EN_CLR | |
759 | GMC_DST_CLR_CMP_FCN_CLEAR | |
760 | GMC_AUX_CLIP_CLEAR | |
761 | GMC_WRITE_MASK_SET); |
762 | |
763 | wait_for_fifo(entries: 8, par); |
764 | /* clear the line drawing registers */ |
765 | aty_st_le32(DST_BRES_ERR, 0); |
766 | aty_st_le32(DST_BRES_INC, 0); |
767 | aty_st_le32(DST_BRES_DEC, 0); |
768 | |
769 | /* set brush color registers */ |
770 | aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */ |
771 | aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */ |
772 | |
773 | /* set source color registers */ |
774 | aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF); /* white */ |
775 | aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000); /* black */ |
776 | |
777 | /* default write mask */ |
778 | aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF); |
779 | |
780 | /* Wait for all the writes to be completed before returning */ |
781 | wait_for_idle(par); |
782 | } |
783 | |
784 | |
785 | /* convert depth values to their register representation */ |
786 | static u32 depth_to_dst(u32 depth) |
787 | { |
788 | if (depth <= 8) |
789 | return DST_8BPP; |
790 | else if (depth <= 15) |
791 | return DST_15BPP; |
792 | else if (depth == 16) |
793 | return DST_16BPP; |
794 | else if (depth <= 24) |
795 | return DST_24BPP; |
796 | else if (depth <= 32) |
797 | return DST_32BPP; |
798 | |
799 | return -EINVAL; |
800 | } |
801 | |
802 | /* |
803 | * PLL informations retreival |
804 | */ |
805 | |
806 | |
807 | #ifndef __sparc__ |
808 | static void __iomem *aty128_map_ROM(const struct aty128fb_par *par, |
809 | struct pci_dev *dev) |
810 | { |
811 | u16 dptr; |
812 | u8 rom_type; |
813 | void __iomem *bios; |
814 | size_t rom_size; |
815 | |
816 | /* Fix from ATI for problem with Rage128 hardware not leaving ROM enabled */ |
817 | unsigned int temp; |
818 | temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG); |
819 | temp &= 0x00ffffffu; |
820 | temp |= 0x04 << 24; |
821 | aty_st_le32(RAGE128_MPP_TB_CONFIG, temp); |
822 | temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG); |
823 | |
824 | bios = pci_map_rom(pdev: dev, size: &rom_size); |
825 | |
826 | if (!bios) { |
827 | printk(KERN_ERR "aty128fb: ROM failed to map\n" ); |
828 | return NULL; |
829 | } |
830 | |
831 | /* Very simple test to make sure it appeared */ |
832 | if (BIOS_IN16(0) != 0xaa55) { |
833 | printk(KERN_DEBUG "aty128fb: Invalid ROM signature %x should " |
834 | " be 0xaa55\n" , BIOS_IN16(0)); |
835 | goto failed; |
836 | } |
837 | |
838 | /* Look for the PCI data to check the ROM type */ |
839 | dptr = BIOS_IN16(0x18); |
840 | |
841 | /* Check the PCI data signature. If it's wrong, we still assume a normal |
842 | * x86 ROM for now, until I've verified this works everywhere. |
843 | * The goal here is more to phase out Open Firmware images. |
844 | * |
845 | * Currently, we only look at the first PCI data, we could iteratre and |
846 | * deal with them all, and we should use fb_bios_start relative to start |
847 | * of image and not relative start of ROM, but so far, I never found a |
848 | * dual-image ATI card. |
849 | * |
850 | * typedef struct { |
851 | * u32 signature; + 0x00 |
852 | * u16 vendor; + 0x04 |
853 | * u16 device; + 0x06 |
854 | * u16 reserved_1; + 0x08 |
855 | * u16 dlen; + 0x0a |
856 | * u8 drevision; + 0x0c |
857 | * u8 class_hi; + 0x0d |
858 | * u16 class_lo; + 0x0e |
859 | * u16 ilen; + 0x10 |
860 | * u16 irevision; + 0x12 |
861 | * u8 type; + 0x14 |
862 | * u8 indicator; + 0x15 |
863 | * u16 reserved_2; + 0x16 |
864 | * } pci_data_t; |
865 | */ |
866 | if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) { |
867 | printk(KERN_WARNING "aty128fb: PCI DATA signature in ROM incorrect: %08x\n" , |
868 | BIOS_IN32(dptr)); |
869 | goto anyway; |
870 | } |
871 | rom_type = BIOS_IN8(dptr + 0x14); |
872 | switch(rom_type) { |
873 | case 0: |
874 | printk(KERN_INFO "aty128fb: Found Intel x86 BIOS ROM Image\n" ); |
875 | break; |
876 | case 1: |
877 | printk(KERN_INFO "aty128fb: Found Open Firmware ROM Image\n" ); |
878 | goto failed; |
879 | case 2: |
880 | printk(KERN_INFO "aty128fb: Found HP PA-RISC ROM Image\n" ); |
881 | goto failed; |
882 | default: |
883 | printk(KERN_INFO "aty128fb: Found unknown type %d ROM Image\n" , |
884 | rom_type); |
885 | goto failed; |
886 | } |
887 | anyway: |
888 | return bios; |
889 | |
890 | failed: |
891 | pci_unmap_rom(pdev: dev, rom: bios); |
892 | return NULL; |
893 | } |
894 | |
895 | static void aty128_get_pllinfo(struct aty128fb_par *par, |
896 | unsigned char __iomem *bios) |
897 | { |
898 | unsigned int bios_hdr; |
899 | unsigned int bios_pll; |
900 | |
901 | bios_hdr = BIOS_IN16(0x48); |
902 | bios_pll = BIOS_IN16(bios_hdr + 0x30); |
903 | |
904 | par->constants.ppll_max = BIOS_IN32(bios_pll + 0x16); |
905 | par->constants.ppll_min = BIOS_IN32(bios_pll + 0x12); |
906 | par->constants.xclk = BIOS_IN16(bios_pll + 0x08); |
907 | par->constants.ref_divider = BIOS_IN16(bios_pll + 0x10); |
908 | par->constants.ref_clk = BIOS_IN16(bios_pll + 0x0e); |
909 | |
910 | DBG("ppll_max %d ppll_min %d xclk %d ref_divider %d ref clock %d\n" , |
911 | par->constants.ppll_max, par->constants.ppll_min, |
912 | par->constants.xclk, par->constants.ref_divider, |
913 | par->constants.ref_clk); |
914 | |
915 | } |
916 | |
917 | #ifdef CONFIG_X86 |
918 | static void __iomem *aty128_find_mem_vbios(struct aty128fb_par *par) |
919 | { |
920 | /* I simplified this code as we used to miss the signatures in |
921 | * a lot of case. It's now closer to XFree, we just don't check |
922 | * for signatures at all... Something better will have to be done |
923 | * if we end up having conflicts |
924 | */ |
925 | u32 segstart; |
926 | unsigned char __iomem *rom_base = NULL; |
927 | |
928 | for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) { |
929 | rom_base = ioremap(offset: segstart, size: 0x10000); |
930 | if (rom_base == NULL) |
931 | return NULL; |
932 | if (readb(addr: rom_base) == 0x55 && readb(addr: rom_base + 1) == 0xaa) |
933 | break; |
934 | iounmap(addr: rom_base); |
935 | rom_base = NULL; |
936 | } |
937 | return rom_base; |
938 | } |
939 | #endif |
940 | #endif /* ndef(__sparc__) */ |
941 | |
942 | /* fill in known card constants if pll_block is not available */ |
943 | static void aty128_timings(struct aty128fb_par *par) |
944 | { |
945 | #ifdef CONFIG_PPC |
946 | /* instead of a table lookup, assume OF has properly |
947 | * setup the PLL registers and use their values |
948 | * to set the XCLK values and reference divider values */ |
949 | |
950 | u32 x_mpll_ref_fb_div; |
951 | u32 xclk_cntl; |
952 | u32 Nx, M; |
953 | static const unsigned int PostDivSet[] = { 0, 1, 2, 4, 8, 3, 6, 12 }; |
954 | #endif |
955 | |
956 | if (!par->constants.ref_clk) |
957 | par->constants.ref_clk = 2950; |
958 | |
959 | #ifdef CONFIG_PPC |
960 | x_mpll_ref_fb_div = aty_ld_pll(X_MPLL_REF_FB_DIV); |
961 | xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7; |
962 | Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8; |
963 | M = x_mpll_ref_fb_div & 0x0000ff; |
964 | |
965 | par->constants.xclk = round_div((2 * Nx * par->constants.ref_clk), |
966 | (M * PostDivSet[xclk_cntl])); |
967 | |
968 | par->constants.ref_divider = |
969 | aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK; |
970 | #endif |
971 | |
972 | if (!par->constants.ref_divider) { |
973 | par->constants.ref_divider = 0x3b; |
974 | |
975 | aty_st_pll(X_MPLL_REF_FB_DIV, 0x004c4c1e); |
976 | aty_pll_writeupdate(par); |
977 | } |
978 | aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider); |
979 | aty_pll_writeupdate(par); |
980 | |
981 | /* from documentation */ |
982 | if (!par->constants.ppll_min) |
983 | par->constants.ppll_min = 12500; |
984 | if (!par->constants.ppll_max) |
985 | par->constants.ppll_max = 25000; /* 23000 on some cards? */ |
986 | if (!par->constants.xclk) |
987 | par->constants.xclk = 0x1d4d; /* same as mclk */ |
988 | |
989 | par->constants.fifo_width = 128; |
990 | par->constants.fifo_depth = 32; |
991 | |
992 | switch (aty_ld_le32(MEM_CNTL) & 0x3) { |
993 | case 0: |
994 | par->mem = &sdr_128; |
995 | break; |
996 | case 1: |
997 | par->mem = &sdr_sgram; |
998 | break; |
999 | case 2: |
1000 | par->mem = &ddr_sgram; |
1001 | break; |
1002 | default: |
1003 | par->mem = &sdr_sgram; |
1004 | } |
1005 | } |
1006 | |
1007 | |
1008 | |
1009 | /* |
1010 | * CRTC programming |
1011 | */ |
1012 | |
1013 | /* Program the CRTC registers */ |
1014 | static void aty128_set_crtc(const struct aty128_crtc *crtc, |
1015 | const struct aty128fb_par *par) |
1016 | { |
1017 | aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl); |
1018 | aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total); |
1019 | aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); |
1020 | aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total); |
1021 | aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); |
1022 | aty_st_le32(CRTC_PITCH, crtc->pitch); |
1023 | aty_st_le32(CRTC_OFFSET, crtc->offset); |
1024 | aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl); |
1025 | /* Disable ATOMIC updating. Is this the right place? */ |
1026 | aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~(0x00030000)); |
1027 | } |
1028 | |
1029 | |
1030 | static int aty128_var_to_crtc(const struct fb_var_screeninfo *var, |
1031 | struct aty128_crtc *crtc, |
1032 | const struct aty128fb_par *par) |
1033 | { |
1034 | u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp, dst; |
1035 | u32 left, right, upper, lower, hslen, vslen, sync, vmode; |
1036 | u32 h_total, h_disp, h_sync_strt, h_sync_wid, h_sync_pol; |
1037 | u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync; |
1038 | u32 depth, bytpp; |
1039 | u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 }; |
1040 | |
1041 | /* input */ |
1042 | xres = var->xres; |
1043 | yres = var->yres; |
1044 | vxres = var->xres_virtual; |
1045 | vyres = var->yres_virtual; |
1046 | xoffset = var->xoffset; |
1047 | yoffset = var->yoffset; |
1048 | bpp = var->bits_per_pixel; |
1049 | left = var->left_margin; |
1050 | right = var->right_margin; |
1051 | upper = var->upper_margin; |
1052 | lower = var->lower_margin; |
1053 | hslen = var->hsync_len; |
1054 | vslen = var->vsync_len; |
1055 | sync = var->sync; |
1056 | vmode = var->vmode; |
1057 | |
1058 | if (bpp != 16) |
1059 | depth = bpp; |
1060 | else |
1061 | depth = (var->green.length == 6) ? 16 : 15; |
1062 | |
1063 | /* check for mode eligibility |
1064 | * accept only non interlaced modes */ |
1065 | if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED) |
1066 | return -EINVAL; |
1067 | |
1068 | /* convert (and round up) and validate */ |
1069 | xres = (xres + 7) & ~7; |
1070 | xoffset = (xoffset + 7) & ~7; |
1071 | |
1072 | if (vxres < xres + xoffset) |
1073 | vxres = xres + xoffset; |
1074 | |
1075 | if (vyres < yres + yoffset) |
1076 | vyres = yres + yoffset; |
1077 | |
1078 | /* convert depth into ATI register depth */ |
1079 | dst = depth_to_dst(depth); |
1080 | |
1081 | if (dst == -EINVAL) { |
1082 | printk(KERN_ERR "aty128fb: Invalid depth or RGBA\n" ); |
1083 | return -EINVAL; |
1084 | } |
1085 | |
1086 | /* convert register depth to bytes per pixel */ |
1087 | bytpp = mode_bytpp[dst]; |
1088 | |
1089 | /* make sure there is enough video ram for the mode */ |
1090 | if ((u32)(vxres * vyres * bytpp) > par->vram_size) { |
1091 | printk(KERN_ERR "aty128fb: Not enough memory for mode\n" ); |
1092 | return -EINVAL; |
1093 | } |
1094 | |
1095 | h_disp = (xres >> 3) - 1; |
1096 | h_total = (((xres + right + hslen + left) >> 3) - 1) & 0xFFFFL; |
1097 | |
1098 | v_disp = yres - 1; |
1099 | v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL; |
1100 | |
1101 | /* check to make sure h_total and v_total are in range */ |
1102 | if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) { |
1103 | printk(KERN_ERR "aty128fb: invalid width ranges\n" ); |
1104 | return -EINVAL; |
1105 | } |
1106 | |
1107 | h_sync_wid = (hslen + 7) >> 3; |
1108 | if (h_sync_wid == 0) |
1109 | h_sync_wid = 1; |
1110 | else if (h_sync_wid > 0x3f) /* 0x3f = max hwidth */ |
1111 | h_sync_wid = 0x3f; |
1112 | |
1113 | h_sync_strt = (h_disp << 3) + right; |
1114 | |
1115 | v_sync_wid = vslen; |
1116 | if (v_sync_wid == 0) |
1117 | v_sync_wid = 1; |
1118 | else if (v_sync_wid > 0x1f) /* 0x1f = max vwidth */ |
1119 | v_sync_wid = 0x1f; |
1120 | |
1121 | v_sync_strt = v_disp + lower; |
1122 | |
1123 | h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1; |
1124 | v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1; |
1125 | |
1126 | c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0; |
1127 | |
1128 | crtc->gen_cntl = 0x3000000L | c_sync | (dst << 8); |
1129 | |
1130 | crtc->h_total = h_total | (h_disp << 16); |
1131 | crtc->v_total = v_total | (v_disp << 16); |
1132 | |
1133 | crtc->h_sync_strt_wid = h_sync_strt | (h_sync_wid << 16) | |
1134 | (h_sync_pol << 23); |
1135 | crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) | |
1136 | (v_sync_pol << 23); |
1137 | |
1138 | crtc->pitch = vxres >> 3; |
1139 | |
1140 | crtc->offset = 0; |
1141 | |
1142 | if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) |
1143 | crtc->offset_cntl = 0x00010000; |
1144 | else |
1145 | crtc->offset_cntl = 0; |
1146 | |
1147 | crtc->vxres = vxres; |
1148 | crtc->vyres = vyres; |
1149 | crtc->xoffset = xoffset; |
1150 | crtc->yoffset = yoffset; |
1151 | crtc->depth = depth; |
1152 | crtc->bpp = bpp; |
1153 | |
1154 | return 0; |
1155 | } |
1156 | |
1157 | |
1158 | static int aty128_pix_width_to_var(int pix_width, struct fb_var_screeninfo *var) |
1159 | { |
1160 | |
1161 | /* fill in pixel info */ |
1162 | var->red.msb_right = 0; |
1163 | var->green.msb_right = 0; |
1164 | var->blue.offset = 0; |
1165 | var->blue.msb_right = 0; |
1166 | var->transp.offset = 0; |
1167 | var->transp.length = 0; |
1168 | var->transp.msb_right = 0; |
1169 | switch (pix_width) { |
1170 | case CRTC_PIX_WIDTH_8BPP: |
1171 | var->bits_per_pixel = 8; |
1172 | var->red.offset = 0; |
1173 | var->red.length = 8; |
1174 | var->green.offset = 0; |
1175 | var->green.length = 8; |
1176 | var->blue.length = 8; |
1177 | break; |
1178 | case CRTC_PIX_WIDTH_15BPP: |
1179 | var->bits_per_pixel = 16; |
1180 | var->red.offset = 10; |
1181 | var->red.length = 5; |
1182 | var->green.offset = 5; |
1183 | var->green.length = 5; |
1184 | var->blue.length = 5; |
1185 | break; |
1186 | case CRTC_PIX_WIDTH_16BPP: |
1187 | var->bits_per_pixel = 16; |
1188 | var->red.offset = 11; |
1189 | var->red.length = 5; |
1190 | var->green.offset = 5; |
1191 | var->green.length = 6; |
1192 | var->blue.length = 5; |
1193 | break; |
1194 | case CRTC_PIX_WIDTH_24BPP: |
1195 | var->bits_per_pixel = 24; |
1196 | var->red.offset = 16; |
1197 | var->red.length = 8; |
1198 | var->green.offset = 8; |
1199 | var->green.length = 8; |
1200 | var->blue.length = 8; |
1201 | break; |
1202 | case CRTC_PIX_WIDTH_32BPP: |
1203 | var->bits_per_pixel = 32; |
1204 | var->red.offset = 16; |
1205 | var->red.length = 8; |
1206 | var->green.offset = 8; |
1207 | var->green.length = 8; |
1208 | var->blue.length = 8; |
1209 | var->transp.offset = 24; |
1210 | var->transp.length = 8; |
1211 | break; |
1212 | default: |
1213 | printk(KERN_ERR "aty128fb: Invalid pixel width\n" ); |
1214 | return -EINVAL; |
1215 | } |
1216 | |
1217 | return 0; |
1218 | } |
1219 | |
1220 | |
1221 | static int aty128_crtc_to_var(const struct aty128_crtc *crtc, |
1222 | struct fb_var_screeninfo *var) |
1223 | { |
1224 | u32 xres, yres, left, right, upper, lower, hslen, vslen, sync; |
1225 | u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol; |
1226 | u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync; |
1227 | u32 pix_width; |
1228 | |
1229 | /* fun with masking */ |
1230 | h_total = crtc->h_total & 0x1ff; |
1231 | h_disp = (crtc->h_total >> 16) & 0xff; |
1232 | h_sync_strt = (crtc->h_sync_strt_wid >> 3) & 0x1ff; |
1233 | h_sync_dly = crtc->h_sync_strt_wid & 0x7; |
1234 | h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x3f; |
1235 | h_sync_pol = (crtc->h_sync_strt_wid >> 23) & 0x1; |
1236 | v_total = crtc->v_total & 0x7ff; |
1237 | v_disp = (crtc->v_total >> 16) & 0x7ff; |
1238 | v_sync_strt = crtc->v_sync_strt_wid & 0x7ff; |
1239 | v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f; |
1240 | v_sync_pol = (crtc->v_sync_strt_wid >> 23) & 0x1; |
1241 | c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0; |
1242 | pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK; |
1243 | |
1244 | /* do conversions */ |
1245 | xres = (h_disp + 1) << 3; |
1246 | yres = v_disp + 1; |
1247 | left = ((h_total - h_sync_strt - h_sync_wid) << 3) - h_sync_dly; |
1248 | right = ((h_sync_strt - h_disp) << 3) + h_sync_dly; |
1249 | hslen = h_sync_wid << 3; |
1250 | upper = v_total - v_sync_strt - v_sync_wid; |
1251 | lower = v_sync_strt - v_disp; |
1252 | vslen = v_sync_wid; |
1253 | sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) | |
1254 | (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) | |
1255 | (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0); |
1256 | |
1257 | aty128_pix_width_to_var(pix_width, var); |
1258 | |
1259 | var->xres = xres; |
1260 | var->yres = yres; |
1261 | var->xres_virtual = crtc->vxres; |
1262 | var->yres_virtual = crtc->vyres; |
1263 | var->xoffset = crtc->xoffset; |
1264 | var->yoffset = crtc->yoffset; |
1265 | var->left_margin = left; |
1266 | var->right_margin = right; |
1267 | var->upper_margin = upper; |
1268 | var->lower_margin = lower; |
1269 | var->hsync_len = hslen; |
1270 | var->vsync_len = vslen; |
1271 | var->sync = sync; |
1272 | var->vmode = FB_VMODE_NONINTERLACED; |
1273 | |
1274 | return 0; |
1275 | } |
1276 | |
1277 | static void aty128_set_crt_enable(struct aty128fb_par *par, int on) |
1278 | { |
1279 | if (on) { |
1280 | aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) | |
1281 | CRT_CRTC_ON); |
1282 | aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) | |
1283 | DAC_PALETTE2_SNOOP_EN)); |
1284 | } else |
1285 | aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) & |
1286 | ~CRT_CRTC_ON); |
1287 | } |
1288 | |
1289 | static void aty128_set_lcd_enable(struct aty128fb_par *par, int on) |
1290 | { |
1291 | u32 reg; |
1292 | #ifdef CONFIG_FB_ATY128_BACKLIGHT |
1293 | struct fb_info *info = pci_get_drvdata(pdev: par->pdev); |
1294 | #endif |
1295 | |
1296 | if (on) { |
1297 | reg = aty_ld_le32(LVDS_GEN_CNTL); |
1298 | reg |= LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION; |
1299 | reg &= ~LVDS_DISPLAY_DIS; |
1300 | aty_st_le32(LVDS_GEN_CNTL, reg); |
1301 | #ifdef CONFIG_FB_ATY128_BACKLIGHT |
1302 | aty128_bl_set_power(info, power: FB_BLANK_UNBLANK); |
1303 | #endif |
1304 | } else { |
1305 | #ifdef CONFIG_FB_ATY128_BACKLIGHT |
1306 | aty128_bl_set_power(info, power: FB_BLANK_POWERDOWN); |
1307 | #endif |
1308 | reg = aty_ld_le32(LVDS_GEN_CNTL); |
1309 | reg |= LVDS_DISPLAY_DIS; |
1310 | aty_st_le32(LVDS_GEN_CNTL, reg); |
1311 | mdelay(100); |
1312 | reg &= ~(LVDS_ON /*| LVDS_EN*/); |
1313 | aty_st_le32(LVDS_GEN_CNTL, reg); |
1314 | } |
1315 | } |
1316 | |
1317 | static void aty128_set_pll(struct aty128_pll *pll, |
1318 | const struct aty128fb_par *par) |
1319 | { |
1320 | u32 div3; |
1321 | |
1322 | /* register values for post dividers */ |
1323 | static const unsigned char post_conv[] = { |
1324 | 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 |
1325 | }; |
1326 | |
1327 | /* select PPLL_DIV_3 */ |
1328 | aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8)); |
1329 | |
1330 | /* reset PLL */ |
1331 | aty_st_pll(PPLL_CNTL, |
1332 | aty_ld_pll(PPLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN); |
1333 | |
1334 | /* write the reference divider */ |
1335 | aty_pll_wait_readupdate(par); |
1336 | aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider & 0x3ff); |
1337 | aty_pll_writeupdate(par); |
1338 | |
1339 | div3 = aty_ld_pll(PPLL_DIV_3); |
1340 | div3 &= ~PPLL_FB3_DIV_MASK; |
1341 | div3 |= pll->feedback_divider; |
1342 | div3 &= ~PPLL_POST3_DIV_MASK; |
1343 | div3 |= post_conv[pll->post_divider] << 16; |
1344 | |
1345 | /* write feedback and post dividers */ |
1346 | aty_pll_wait_readupdate(par); |
1347 | aty_st_pll(PPLL_DIV_3, div3); |
1348 | aty_pll_writeupdate(par); |
1349 | |
1350 | aty_pll_wait_readupdate(par); |
1351 | aty_st_pll(HTOTAL_CNTL, 0); /* no horiz crtc adjustment */ |
1352 | aty_pll_writeupdate(par); |
1353 | |
1354 | /* clear the reset, just in case */ |
1355 | aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~PPLL_RESET); |
1356 | } |
1357 | |
1358 | |
1359 | static int aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll, |
1360 | const struct aty128fb_par *par) |
1361 | { |
1362 | const struct aty128_constants c = par->constants; |
1363 | static const unsigned char post_dividers[] = { 1, 2, 4, 8, 3, 6, 12 }; |
1364 | u32 output_freq; |
1365 | u32 vclk; /* in .01 MHz */ |
1366 | int i = 0; |
1367 | u32 n, d; |
1368 | |
1369 | vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */ |
1370 | |
1371 | /* adjust pixel clock if necessary */ |
1372 | if (vclk > c.ppll_max) |
1373 | vclk = c.ppll_max; |
1374 | if (vclk * 12 < c.ppll_min) |
1375 | vclk = c.ppll_min/12; |
1376 | |
1377 | /* now, find an acceptable divider */ |
1378 | for (i = 0; i < ARRAY_SIZE(post_dividers); i++) { |
1379 | output_freq = post_dividers[i] * vclk; |
1380 | if (output_freq >= c.ppll_min && output_freq <= c.ppll_max) { |
1381 | pll->post_divider = post_dividers[i]; |
1382 | break; |
1383 | } |
1384 | } |
1385 | |
1386 | if (i == ARRAY_SIZE(post_dividers)) |
1387 | return -EINVAL; |
1388 | |
1389 | /* calculate feedback divider */ |
1390 | n = c.ref_divider * output_freq; |
1391 | d = c.ref_clk; |
1392 | |
1393 | pll->feedback_divider = round_div(n, d); |
1394 | pll->vclk = vclk; |
1395 | |
1396 | DBG("post %d feedback %d vlck %d output %d ref_divider %d " |
1397 | "vclk_per: %d\n" , pll->post_divider, |
1398 | pll->feedback_divider, vclk, output_freq, |
1399 | c.ref_divider, period_in_ps); |
1400 | |
1401 | return 0; |
1402 | } |
1403 | |
1404 | |
1405 | static int aty128_pll_to_var(const struct aty128_pll *pll, |
1406 | struct fb_var_screeninfo *var) |
1407 | { |
1408 | var->pixclock = 100000000 / pll->vclk; |
1409 | |
1410 | return 0; |
1411 | } |
1412 | |
1413 | |
1414 | static void aty128_set_fifo(const struct aty128_ddafifo *dsp, |
1415 | const struct aty128fb_par *par) |
1416 | { |
1417 | aty_st_le32(DDA_CONFIG, dsp->dda_config); |
1418 | aty_st_le32(DDA_ON_OFF, dsp->dda_on_off); |
1419 | } |
1420 | |
1421 | |
1422 | static int aty128_ddafifo(struct aty128_ddafifo *dsp, |
1423 | const struct aty128_pll *pll, |
1424 | u32 depth, |
1425 | const struct aty128fb_par *par) |
1426 | { |
1427 | const struct aty128_meminfo *m = par->mem; |
1428 | u32 xclk = par->constants.xclk; |
1429 | u32 fifo_width = par->constants.fifo_width; |
1430 | u32 fifo_depth = par->constants.fifo_depth; |
1431 | s32 x, b, p, ron, roff; |
1432 | u32 n, d, bpp; |
1433 | |
1434 | /* round up to multiple of 8 */ |
1435 | bpp = (depth+7) & ~7; |
1436 | |
1437 | n = xclk * fifo_width; |
1438 | d = pll->vclk * bpp; |
1439 | x = round_div(n, d); |
1440 | |
1441 | ron = 4 * m->MB + |
1442 | 3 * ((m->Trcd - 2 > 0) ? m->Trcd - 2 : 0) + |
1443 | 2 * m->Trp + |
1444 | m->Twr + |
1445 | m->CL + |
1446 | m->Tr2w + |
1447 | x; |
1448 | |
1449 | DBG("x %x\n" , x); |
1450 | |
1451 | b = 0; |
1452 | while (x) { |
1453 | x >>= 1; |
1454 | b++; |
1455 | } |
1456 | p = b + 1; |
1457 | |
1458 | ron <<= (11 - p); |
1459 | |
1460 | n <<= (11 - p); |
1461 | x = round_div(n, d); |
1462 | roff = x * (fifo_depth - 4); |
1463 | |
1464 | if ((ron + m->Rloop) >= roff) { |
1465 | printk(KERN_ERR "aty128fb: Mode out of range!\n" ); |
1466 | return -EINVAL; |
1467 | } |
1468 | |
1469 | DBG("p: %x rloop: %x x: %x ron: %x roff: %x\n" , |
1470 | p, m->Rloop, x, ron, roff); |
1471 | |
1472 | dsp->dda_config = p << 16 | m->Rloop << 20 | x; |
1473 | dsp->dda_on_off = ron << 16 | roff; |
1474 | |
1475 | return 0; |
1476 | } |
1477 | |
1478 | |
1479 | /* |
1480 | * This actually sets the video mode. |
1481 | */ |
1482 | static int aty128fb_set_par(struct fb_info *info) |
1483 | { |
1484 | struct aty128fb_par *par = info->par; |
1485 | u32 config; |
1486 | int err; |
1487 | |
1488 | if ((err = aty128_decode_var(var: &info->var, par)) != 0) |
1489 | return err; |
1490 | |
1491 | if (par->blitter_may_be_busy) |
1492 | wait_for_idle(par); |
1493 | |
1494 | /* clear all registers that may interfere with mode setting */ |
1495 | aty_st_le32(OVR_CLR, 0); |
1496 | aty_st_le32(OVR_WID_LEFT_RIGHT, 0); |
1497 | aty_st_le32(OVR_WID_TOP_BOTTOM, 0); |
1498 | aty_st_le32(OV0_SCALE_CNTL, 0); |
1499 | aty_st_le32(MPP_TB_CONFIG, 0); |
1500 | aty_st_le32(MPP_GP_CONFIG, 0); |
1501 | aty_st_le32(SUBPIC_CNTL, 0); |
1502 | aty_st_le32(VIPH_CONTROL, 0); |
1503 | aty_st_le32(I2C_CNTL_1, 0); /* turn off i2c */ |
1504 | aty_st_le32(GEN_INT_CNTL, 0); /* turn off interrupts */ |
1505 | aty_st_le32(CAP0_TRIG_CNTL, 0); |
1506 | aty_st_le32(CAP1_TRIG_CNTL, 0); |
1507 | |
1508 | aty_st_8(CRTC_EXT_CNTL + 1, 4); /* turn video off */ |
1509 | |
1510 | aty128_set_crtc(crtc: &par->crtc, par); |
1511 | aty128_set_pll(pll: &par->pll, par); |
1512 | aty128_set_fifo(dsp: &par->fifo_reg, par); |
1513 | |
1514 | config = aty_ld_le32(CNFG_CNTL) & ~3; |
1515 | |
1516 | #if defined(__BIG_ENDIAN) |
1517 | if (par->crtc.bpp == 32) |
1518 | config |= 2; /* make aperture do 32 bit swapping */ |
1519 | else if (par->crtc.bpp == 16) |
1520 | config |= 1; /* make aperture do 16 bit swapping */ |
1521 | #endif |
1522 | |
1523 | aty_st_le32(CNFG_CNTL, config); |
1524 | aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */ |
1525 | |
1526 | info->fix.line_length = (par->crtc.vxres * par->crtc.bpp) >> 3; |
1527 | info->fix.visual = par->crtc.bpp == 8 ? FB_VISUAL_PSEUDOCOLOR |
1528 | : FB_VISUAL_DIRECTCOLOR; |
1529 | |
1530 | if (par->chip_gen == rage_M3) { |
1531 | aty128_set_crt_enable(par, on: par->crt_on); |
1532 | aty128_set_lcd_enable(par, on: par->lcd_on); |
1533 | } |
1534 | if (par->accel_flags & FB_ACCELF_TEXT) |
1535 | aty128_init_engine(par); |
1536 | |
1537 | #ifdef CONFIG_BOOTX_TEXT |
1538 | btext_update_display(info->fix.smem_start, |
1539 | (((par->crtc.h_total>>16) & 0xff)+1)*8, |
1540 | ((par->crtc.v_total>>16) & 0x7ff)+1, |
1541 | par->crtc.bpp, |
1542 | par->crtc.vxres*par->crtc.bpp/8); |
1543 | #endif /* CONFIG_BOOTX_TEXT */ |
1544 | |
1545 | return 0; |
1546 | } |
1547 | |
1548 | /* |
1549 | * encode/decode the User Defined Part of the Display |
1550 | */ |
1551 | |
1552 | static int aty128_decode_var(struct fb_var_screeninfo *var, |
1553 | struct aty128fb_par *par) |
1554 | { |
1555 | int err; |
1556 | struct aty128_crtc crtc; |
1557 | struct aty128_pll pll; |
1558 | struct aty128_ddafifo fifo_reg; |
1559 | |
1560 | if ((err = aty128_var_to_crtc(var, crtc: &crtc, par))) |
1561 | return err; |
1562 | |
1563 | if ((err = aty128_var_to_pll(period_in_ps: var->pixclock, pll: &pll, par))) |
1564 | return err; |
1565 | |
1566 | if ((err = aty128_ddafifo(dsp: &fifo_reg, pll: &pll, depth: crtc.depth, par))) |
1567 | return err; |
1568 | |
1569 | par->crtc = crtc; |
1570 | par->pll = pll; |
1571 | par->fifo_reg = fifo_reg; |
1572 | par->accel_flags = var->accel_flags; |
1573 | |
1574 | return 0; |
1575 | } |
1576 | |
1577 | |
1578 | static int aty128_encode_var(struct fb_var_screeninfo *var, |
1579 | const struct aty128fb_par *par) |
1580 | { |
1581 | int err; |
1582 | |
1583 | if ((err = aty128_crtc_to_var(crtc: &par->crtc, var))) |
1584 | return err; |
1585 | |
1586 | if ((err = aty128_pll_to_var(pll: &par->pll, var))) |
1587 | return err; |
1588 | |
1589 | var->nonstd = 0; |
1590 | var->activate = 0; |
1591 | |
1592 | var->height = -1; |
1593 | var->width = -1; |
1594 | var->accel_flags = par->accel_flags; |
1595 | |
1596 | return 0; |
1597 | } |
1598 | |
1599 | |
1600 | static int aty128fb_check_var(struct fb_var_screeninfo *var, |
1601 | struct fb_info *info) |
1602 | { |
1603 | struct aty128fb_par par; |
1604 | int err; |
1605 | |
1606 | par = *(struct aty128fb_par *)info->par; |
1607 | if ((err = aty128_decode_var(var, par: &par)) != 0) |
1608 | return err; |
1609 | aty128_encode_var(var, par: &par); |
1610 | return 0; |
1611 | } |
1612 | |
1613 | |
1614 | /* |
1615 | * Pan or Wrap the Display |
1616 | */ |
1617 | static int aty128fb_pan_display(struct fb_var_screeninfo *var, |
1618 | struct fb_info *fb) |
1619 | { |
1620 | struct aty128fb_par *par = fb->par; |
1621 | u32 xoffset, yoffset; |
1622 | u32 offset; |
1623 | u32 xres, yres; |
1624 | |
1625 | xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3; |
1626 | yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1; |
1627 | |
1628 | xoffset = (var->xoffset +7) & ~7; |
1629 | yoffset = var->yoffset; |
1630 | |
1631 | if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres) |
1632 | return -EINVAL; |
1633 | |
1634 | par->crtc.xoffset = xoffset; |
1635 | par->crtc.yoffset = yoffset; |
1636 | |
1637 | offset = ((yoffset * par->crtc.vxres + xoffset) * (par->crtc.bpp >> 3)) |
1638 | & ~7; |
1639 | |
1640 | if (par->crtc.bpp == 24) |
1641 | offset += 8 * (offset % 3); /* Must be multiple of 8 and 3 */ |
1642 | |
1643 | aty_st_le32(CRTC_OFFSET, offset); |
1644 | |
1645 | return 0; |
1646 | } |
1647 | |
1648 | |
1649 | /* |
1650 | * Helper function to store a single palette register |
1651 | */ |
1652 | static void aty128_st_pal(u_int regno, u_int red, u_int green, u_int blue, |
1653 | struct aty128fb_par *par) |
1654 | { |
1655 | if (par->chip_gen == rage_M3) { |
1656 | aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & |
1657 | ~DAC_PALETTE_ACCESS_CNTL); |
1658 | } |
1659 | |
1660 | aty_st_8(PALETTE_INDEX, regno); |
1661 | aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue); |
1662 | } |
1663 | |
1664 | static int aty128fb_sync(struct fb_info *info) |
1665 | { |
1666 | struct aty128fb_par *par = info->par; |
1667 | |
1668 | if (par->blitter_may_be_busy) |
1669 | wait_for_idle(par); |
1670 | return 0; |
1671 | } |
1672 | |
1673 | #ifndef MODULE |
1674 | static int aty128fb_setup(char *options) |
1675 | { |
1676 | char *this_opt; |
1677 | |
1678 | if (!options || !*options) |
1679 | return 0; |
1680 | |
1681 | while ((this_opt = strsep(&options, "," )) != NULL) { |
1682 | if (!strncmp(this_opt, "lcd:" , 4)) { |
1683 | default_lcd_on = simple_strtoul(this_opt+4, NULL, 0); |
1684 | continue; |
1685 | } else if (!strncmp(this_opt, "crt:" , 4)) { |
1686 | default_crt_on = simple_strtoul(this_opt+4, NULL, 0); |
1687 | continue; |
1688 | } else if (!strncmp(this_opt, "backlight:" , 10)) { |
1689 | #ifdef CONFIG_FB_ATY128_BACKLIGHT |
1690 | backlight = simple_strtoul(this_opt+10, NULL, 0); |
1691 | #endif |
1692 | continue; |
1693 | } |
1694 | if(!strncmp(this_opt, "nomtrr" , 6)) { |
1695 | mtrr = false; |
1696 | continue; |
1697 | } |
1698 | #ifdef CONFIG_PPC_PMAC |
1699 | /* vmode and cmode deprecated */ |
1700 | if (!strncmp(this_opt, "vmode:" , 6)) { |
1701 | unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0); |
1702 | if (vmode > 0 && vmode <= VMODE_MAX) |
1703 | default_vmode = vmode; |
1704 | continue; |
1705 | } else if (!strncmp(this_opt, "cmode:" , 6)) { |
1706 | unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0); |
1707 | switch (cmode) { |
1708 | case 0: |
1709 | case 8: |
1710 | default_cmode = CMODE_8; |
1711 | break; |
1712 | case 15: |
1713 | case 16: |
1714 | default_cmode = CMODE_16; |
1715 | break; |
1716 | case 24: |
1717 | case 32: |
1718 | default_cmode = CMODE_32; |
1719 | break; |
1720 | } |
1721 | continue; |
1722 | } |
1723 | #endif /* CONFIG_PPC_PMAC */ |
1724 | mode_option = this_opt; |
1725 | } |
1726 | return 0; |
1727 | } |
1728 | #endif /* MODULE */ |
1729 | |
1730 | /* Backlight */ |
1731 | #ifdef CONFIG_FB_ATY128_BACKLIGHT |
1732 | #define MAX_LEVEL 0xFF |
1733 | |
1734 | static int aty128_bl_get_level_brightness(struct aty128fb_par *par, |
1735 | int level) |
1736 | { |
1737 | struct fb_info *info = pci_get_drvdata(pdev: par->pdev); |
1738 | int atylevel; |
1739 | |
1740 | /* Get and convert the value */ |
1741 | /* No locking of bl_curve since we read a single value */ |
1742 | atylevel = MAX_LEVEL - |
1743 | (info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL); |
1744 | |
1745 | if (atylevel < 0) |
1746 | atylevel = 0; |
1747 | else if (atylevel > MAX_LEVEL) |
1748 | atylevel = MAX_LEVEL; |
1749 | |
1750 | return atylevel; |
1751 | } |
1752 | |
1753 | /* We turn off the LCD completely instead of just dimming the backlight. |
1754 | * This provides greater power saving and the display is useless without |
1755 | * backlight anyway |
1756 | */ |
1757 | #define BACKLIGHT_LVDS_OFF |
1758 | /* That one prevents proper CRT output with LCD off */ |
1759 | #undef BACKLIGHT_DAC_OFF |
1760 | |
1761 | static int aty128_bl_update_status(struct backlight_device *bd) |
1762 | { |
1763 | struct aty128fb_par *par = bl_get_data(bl_dev: bd); |
1764 | unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL); |
1765 | int level; |
1766 | |
1767 | if (!par->lcd_on) |
1768 | level = 0; |
1769 | else |
1770 | level = backlight_get_brightness(bd); |
1771 | |
1772 | reg |= LVDS_BL_MOD_EN | LVDS_BLON; |
1773 | if (level > 0) { |
1774 | reg |= LVDS_DIGION; |
1775 | if (!(reg & LVDS_ON)) { |
1776 | reg &= ~LVDS_BLON; |
1777 | aty_st_le32(LVDS_GEN_CNTL, reg); |
1778 | aty_ld_le32(LVDS_GEN_CNTL); |
1779 | mdelay(10); |
1780 | reg |= LVDS_BLON; |
1781 | aty_st_le32(LVDS_GEN_CNTL, reg); |
1782 | } |
1783 | reg &= ~LVDS_BL_MOD_LEVEL_MASK; |
1784 | reg |= (aty128_bl_get_level_brightness(par, level) << |
1785 | LVDS_BL_MOD_LEVEL_SHIFT); |
1786 | #ifdef BACKLIGHT_LVDS_OFF |
1787 | reg |= LVDS_ON | LVDS_EN; |
1788 | reg &= ~LVDS_DISPLAY_DIS; |
1789 | #endif |
1790 | aty_st_le32(LVDS_GEN_CNTL, reg); |
1791 | #ifdef BACKLIGHT_DAC_OFF |
1792 | aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN)); |
1793 | #endif |
1794 | } else { |
1795 | reg &= ~LVDS_BL_MOD_LEVEL_MASK; |
1796 | reg |= (aty128_bl_get_level_brightness(par, level: 0) << |
1797 | LVDS_BL_MOD_LEVEL_SHIFT); |
1798 | #ifdef BACKLIGHT_LVDS_OFF |
1799 | reg |= LVDS_DISPLAY_DIS; |
1800 | aty_st_le32(LVDS_GEN_CNTL, reg); |
1801 | aty_ld_le32(LVDS_GEN_CNTL); |
1802 | udelay(10); |
1803 | reg &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION); |
1804 | #endif |
1805 | aty_st_le32(LVDS_GEN_CNTL, reg); |
1806 | #ifdef BACKLIGHT_DAC_OFF |
1807 | aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN); |
1808 | #endif |
1809 | } |
1810 | |
1811 | return 0; |
1812 | } |
1813 | |
1814 | static const struct backlight_ops aty128_bl_data = { |
1815 | .update_status = aty128_bl_update_status, |
1816 | }; |
1817 | |
1818 | static void aty128_bl_set_power(struct fb_info *info, int power) |
1819 | { |
1820 | if (info->bl_dev) { |
1821 | info->bl_dev->props.power = power; |
1822 | backlight_update_status(bd: info->bl_dev); |
1823 | } |
1824 | } |
1825 | |
1826 | static void aty128_bl_init(struct aty128fb_par *par) |
1827 | { |
1828 | struct backlight_properties props; |
1829 | struct fb_info *info = pci_get_drvdata(pdev: par->pdev); |
1830 | struct backlight_device *bd; |
1831 | char name[12]; |
1832 | |
1833 | /* Could be extended to Rage128Pro LVDS output too */ |
1834 | if (par->chip_gen != rage_M3) |
1835 | return; |
1836 | |
1837 | #ifdef CONFIG_PMAC_BACKLIGHT |
1838 | if (!pmac_has_backlight_type("ati" )) |
1839 | return; |
1840 | #endif |
1841 | |
1842 | snprintf(buf: name, size: sizeof(name), fmt: "aty128bl%d" , info->node); |
1843 | |
1844 | memset(&props, 0, sizeof(struct backlight_properties)); |
1845 | props.type = BACKLIGHT_RAW; |
1846 | props.max_brightness = FB_BACKLIGHT_LEVELS - 1; |
1847 | bd = backlight_device_register(name, dev: info->device, devdata: par, ops: &aty128_bl_data, |
1848 | props: &props); |
1849 | if (IS_ERR(ptr: bd)) { |
1850 | info->bl_dev = NULL; |
1851 | printk(KERN_WARNING "aty128: Backlight registration failed\n" ); |
1852 | goto error; |
1853 | } |
1854 | |
1855 | info->bl_dev = bd; |
1856 | fb_bl_default_curve(fb_info: info, off: 0, |
1857 | min: 63 * FB_BACKLIGHT_MAX / MAX_LEVEL, |
1858 | max: 219 * FB_BACKLIGHT_MAX / MAX_LEVEL); |
1859 | |
1860 | bd->props.brightness = bd->props.max_brightness; |
1861 | bd->props.power = FB_BLANK_UNBLANK; |
1862 | backlight_update_status(bd); |
1863 | |
1864 | printk("aty128: Backlight initialized (%s)\n" , name); |
1865 | |
1866 | return; |
1867 | |
1868 | error: |
1869 | return; |
1870 | } |
1871 | |
1872 | static void aty128_bl_exit(struct backlight_device *bd) |
1873 | { |
1874 | backlight_device_unregister(bd); |
1875 | printk("aty128: Backlight unloaded\n" ); |
1876 | } |
1877 | #endif /* CONFIG_FB_ATY128_BACKLIGHT */ |
1878 | |
1879 | /* |
1880 | * Initialisation |
1881 | */ |
1882 | |
1883 | #ifdef CONFIG_PPC_PMAC__disabled |
1884 | static void aty128_early_resume(void *data) |
1885 | { |
1886 | struct aty128fb_par *par = data; |
1887 | |
1888 | if (!console_trylock()) |
1889 | return; |
1890 | pci_restore_state(par->pdev); |
1891 | aty128_do_resume(par->pdev); |
1892 | console_unlock(); |
1893 | } |
1894 | #endif /* CONFIG_PPC_PMAC */ |
1895 | |
1896 | static int aty128_init(struct pci_dev *pdev, const struct pci_device_id *ent) |
1897 | { |
1898 | struct fb_info *info = pci_get_drvdata(pdev); |
1899 | struct aty128fb_par *par = info->par; |
1900 | struct fb_var_screeninfo var; |
1901 | char video_card[50]; |
1902 | u8 chip_rev; |
1903 | u32 dac; |
1904 | |
1905 | /* Get the chip revision */ |
1906 | chip_rev = (aty_ld_le32(CNFG_CNTL) >> 16) & 0x1F; |
1907 | |
1908 | strcpy(p: video_card, q: "Rage128 XX " ); |
1909 | video_card[8] = ent->device >> 8; |
1910 | video_card[9] = ent->device & 0xFF; |
1911 | |
1912 | /* range check to make sure */ |
1913 | if (ent->driver_data < ARRAY_SIZE(r128_family)) |
1914 | strlcat(p: video_card, q: r128_family[ent->driver_data], |
1915 | avail: sizeof(video_card)); |
1916 | |
1917 | printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] " , video_card, chip_rev); |
1918 | |
1919 | if (par->vram_size % (1024 * 1024) == 0) |
1920 | printk("%dM %s\n" , par->vram_size / (1024*1024), par->mem->name); |
1921 | else |
1922 | printk("%dk %s\n" , par->vram_size / 1024, par->mem->name); |
1923 | |
1924 | par->chip_gen = ent->driver_data; |
1925 | |
1926 | /* fill in info */ |
1927 | info->fbops = &aty128fb_ops; |
1928 | |
1929 | par->lcd_on = default_lcd_on; |
1930 | par->crt_on = default_crt_on; |
1931 | |
1932 | var = default_var; |
1933 | #ifdef CONFIG_PPC_PMAC |
1934 | if (machine_is(powermac)) { |
1935 | /* Indicate sleep capability */ |
1936 | if (par->chip_gen == rage_M3) { |
1937 | pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, NULL, 0, 1); |
1938 | #if 0 /* Disable the early video resume hack for now as it's causing problems, |
1939 | * among others we now rely on the PCI core restoring the config space |
1940 | * for us, which isn't the case with that hack, and that code path causes |
1941 | * various things to be called with interrupts off while they shouldn't. |
1942 | * I'm leaving the code in as it can be useful for debugging purposes |
1943 | */ |
1944 | pmac_set_early_video_resume(aty128_early_resume, par); |
1945 | #endif |
1946 | } |
1947 | |
1948 | /* Find default mode */ |
1949 | if (mode_option) { |
1950 | if (!mac_find_mode(&var, info, mode_option, 8)) |
1951 | var = default_var; |
1952 | } else { |
1953 | if (default_vmode <= 0 || default_vmode > VMODE_MAX) |
1954 | default_vmode = VMODE_1024_768_60; |
1955 | |
1956 | /* iMacs need that resolution |
1957 | * PowerMac2,1 first r128 iMacs |
1958 | * PowerMac2,2 summer 2000 iMacs |
1959 | * PowerMac4,1 january 2001 iMacs "flower power" |
1960 | */ |
1961 | if (of_machine_is_compatible("PowerMac2,1" ) || |
1962 | of_machine_is_compatible("PowerMac2,2" ) || |
1963 | of_machine_is_compatible("PowerMac4,1" )) |
1964 | default_vmode = VMODE_1024_768_75; |
1965 | |
1966 | /* iBook SE */ |
1967 | if (of_machine_is_compatible("PowerBook2,2" )) |
1968 | default_vmode = VMODE_800_600_60; |
1969 | |
1970 | /* PowerBook Firewire (Pismo), iBook Dual USB */ |
1971 | if (of_machine_is_compatible("PowerBook3,1" ) || |
1972 | of_machine_is_compatible("PowerBook4,1" )) |
1973 | default_vmode = VMODE_1024_768_60; |
1974 | |
1975 | /* PowerBook Titanium */ |
1976 | if (of_machine_is_compatible("PowerBook3,2" )) |
1977 | default_vmode = VMODE_1152_768_60; |
1978 | |
1979 | if (default_cmode > 16) |
1980 | default_cmode = CMODE_32; |
1981 | else if (default_cmode > 8) |
1982 | default_cmode = CMODE_16; |
1983 | else |
1984 | default_cmode = CMODE_8; |
1985 | |
1986 | if (mac_vmode_to_var(default_vmode, default_cmode, &var)) |
1987 | var = default_var; |
1988 | } |
1989 | } else |
1990 | #endif /* CONFIG_PPC_PMAC */ |
1991 | { |
1992 | if (mode_option) |
1993 | if (fb_find_mode(var: &var, info, mode_option, NULL, |
1994 | dbsize: 0, default_mode: &defaultmode, default_bpp: 8) == 0) |
1995 | var = default_var; |
1996 | } |
1997 | |
1998 | var.accel_flags &= ~FB_ACCELF_TEXT; |
1999 | // var.accel_flags |= FB_ACCELF_TEXT;/* FIXME Will add accel later */ |
2000 | |
2001 | if (aty128fb_check_var(var: &var, info)) { |
2002 | printk(KERN_ERR "aty128fb: Cannot set default mode.\n" ); |
2003 | return 0; |
2004 | } |
2005 | |
2006 | /* setup the DAC the way we like it */ |
2007 | dac = aty_ld_le32(DAC_CNTL); |
2008 | dac |= (DAC_8BIT_EN | DAC_RANGE_CNTL); |
2009 | dac |= DAC_MASK; |
2010 | if (par->chip_gen == rage_M3) |
2011 | dac |= DAC_PALETTE2_SNOOP_EN; |
2012 | aty_st_le32(DAC_CNTL, dac); |
2013 | |
2014 | /* turn off bus mastering, just in case */ |
2015 | aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS); |
2016 | |
2017 | info->var = var; |
2018 | fb_alloc_cmap(cmap: &info->cmap, len: 256, transp: 0); |
2019 | |
2020 | var.activate = FB_ACTIVATE_NOW; |
2021 | |
2022 | aty128_init_engine(par); |
2023 | |
2024 | par->pdev = pdev; |
2025 | par->asleep = 0; |
2026 | par->lock_blank = 0; |
2027 | |
2028 | if (register_framebuffer(fb_info: info) < 0) |
2029 | return 0; |
2030 | |
2031 | #ifdef CONFIG_FB_ATY128_BACKLIGHT |
2032 | if (backlight) |
2033 | aty128_bl_init(par); |
2034 | #endif |
2035 | |
2036 | fb_info(info, "%s frame buffer device on %s\n" , |
2037 | info->fix.id, video_card); |
2038 | |
2039 | return 1; /* success! */ |
2040 | } |
2041 | |
2042 | #ifdef CONFIG_PCI |
2043 | /* register a card ++ajoshi */ |
2044 | static int aty128_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
2045 | { |
2046 | unsigned long fb_addr, reg_addr; |
2047 | struct aty128fb_par *par; |
2048 | struct fb_info *info; |
2049 | int err; |
2050 | #ifndef __sparc__ |
2051 | void __iomem *bios = NULL; |
2052 | #endif |
2053 | |
2054 | err = aperture_remove_conflicting_pci_devices(pdev, name: "aty128fb" ); |
2055 | if (err) |
2056 | return err; |
2057 | |
2058 | /* Enable device in PCI config */ |
2059 | if ((err = pci_enable_device(dev: pdev))) { |
2060 | printk(KERN_ERR "aty128fb: Cannot enable PCI device: %d\n" , |
2061 | err); |
2062 | return -ENODEV; |
2063 | } |
2064 | |
2065 | fb_addr = pci_resource_start(pdev, 0); |
2066 | if (!request_mem_region(fb_addr, pci_resource_len(pdev, 0), |
2067 | "aty128fb FB" )) { |
2068 | printk(KERN_ERR "aty128fb: cannot reserve frame " |
2069 | "buffer memory\n" ); |
2070 | return -ENODEV; |
2071 | } |
2072 | |
2073 | reg_addr = pci_resource_start(pdev, 2); |
2074 | if (!request_mem_region(reg_addr, pci_resource_len(pdev, 2), |
2075 | "aty128fb MMIO" )) { |
2076 | printk(KERN_ERR "aty128fb: cannot reserve MMIO region\n" ); |
2077 | goto err_free_fb; |
2078 | } |
2079 | |
2080 | /* We have the resources. Now virtualize them */ |
2081 | info = framebuffer_alloc(size: sizeof(struct aty128fb_par), dev: &pdev->dev); |
2082 | if (!info) |
2083 | goto err_free_mmio; |
2084 | |
2085 | par = info->par; |
2086 | |
2087 | info->pseudo_palette = par->pseudo_palette; |
2088 | |
2089 | /* Virtualize mmio region */ |
2090 | info->fix.mmio_start = reg_addr; |
2091 | par->regbase = pci_ioremap_bar(pdev, bar: 2); |
2092 | if (!par->regbase) |
2093 | goto err_free_info; |
2094 | |
2095 | /* Grab memory size from the card */ |
2096 | // How does this relate to the resource length from the PCI hardware? |
2097 | par->vram_size = aty_ld_le32(CNFG_MEMSIZE) & 0x03FFFFFF; |
2098 | |
2099 | /* Virtualize the framebuffer */ |
2100 | info->screen_base = ioremap_wc(offset: fb_addr, size: par->vram_size); |
2101 | if (!info->screen_base) |
2102 | goto err_unmap_out; |
2103 | |
2104 | /* Set up info->fix */ |
2105 | info->fix = aty128fb_fix; |
2106 | info->fix.smem_start = fb_addr; |
2107 | info->fix.smem_len = par->vram_size; |
2108 | info->fix.mmio_start = reg_addr; |
2109 | |
2110 | /* If we can't test scratch registers, something is seriously wrong */ |
2111 | if (!register_test(par)) { |
2112 | printk(KERN_ERR "aty128fb: Can't write to video register!\n" ); |
2113 | goto err_out; |
2114 | } |
2115 | |
2116 | #ifndef __sparc__ |
2117 | bios = aty128_map_ROM(par, dev: pdev); |
2118 | #ifdef CONFIG_X86 |
2119 | if (bios == NULL) |
2120 | bios = aty128_find_mem_vbios(par); |
2121 | #endif |
2122 | if (bios == NULL) |
2123 | printk(KERN_INFO "aty128fb: BIOS not located, guessing timings.\n" ); |
2124 | else { |
2125 | printk(KERN_INFO "aty128fb: Rage128 BIOS located\n" ); |
2126 | aty128_get_pllinfo(par, bios); |
2127 | pci_unmap_rom(pdev, rom: bios); |
2128 | } |
2129 | #endif /* __sparc__ */ |
2130 | |
2131 | aty128_timings(par); |
2132 | pci_set_drvdata(pdev, data: info); |
2133 | |
2134 | if (!aty128_init(pdev, ent)) |
2135 | goto err_out; |
2136 | |
2137 | if (mtrr) |
2138 | par->wc_cookie = arch_phys_wc_add(base: info->fix.smem_start, |
2139 | size: par->vram_size); |
2140 | return 0; |
2141 | |
2142 | err_out: |
2143 | iounmap(addr: info->screen_base); |
2144 | err_unmap_out: |
2145 | iounmap(addr: par->regbase); |
2146 | err_free_info: |
2147 | framebuffer_release(info); |
2148 | err_free_mmio: |
2149 | release_mem_region(pci_resource_start(pdev, 2), |
2150 | pci_resource_len(pdev, 2)); |
2151 | err_free_fb: |
2152 | release_mem_region(pci_resource_start(pdev, 0), |
2153 | pci_resource_len(pdev, 0)); |
2154 | return -ENODEV; |
2155 | } |
2156 | |
2157 | static void aty128_remove(struct pci_dev *pdev) |
2158 | { |
2159 | struct fb_info *info = pci_get_drvdata(pdev); |
2160 | struct aty128fb_par *par; |
2161 | |
2162 | if (!info) |
2163 | return; |
2164 | |
2165 | par = info->par; |
2166 | |
2167 | #ifdef CONFIG_FB_ATY128_BACKLIGHT |
2168 | aty128_bl_exit(bd: info->bl_dev); |
2169 | #endif |
2170 | |
2171 | unregister_framebuffer(fb_info: info); |
2172 | |
2173 | arch_phys_wc_del(handle: par->wc_cookie); |
2174 | iounmap(addr: par->regbase); |
2175 | iounmap(addr: info->screen_base); |
2176 | |
2177 | release_mem_region(pci_resource_start(pdev, 0), |
2178 | pci_resource_len(pdev, 0)); |
2179 | release_mem_region(pci_resource_start(pdev, 2), |
2180 | pci_resource_len(pdev, 2)); |
2181 | framebuffer_release(info); |
2182 | } |
2183 | #endif /* CONFIG_PCI */ |
2184 | |
2185 | |
2186 | |
2187 | /* |
2188 | * Blank the display. |
2189 | */ |
2190 | static int aty128fb_blank(int blank, struct fb_info *fb) |
2191 | { |
2192 | struct aty128fb_par *par = fb->par; |
2193 | u8 state; |
2194 | |
2195 | if (par->lock_blank || par->asleep) |
2196 | return 0; |
2197 | |
2198 | switch (blank) { |
2199 | case FB_BLANK_NORMAL: |
2200 | state = 4; |
2201 | break; |
2202 | case FB_BLANK_VSYNC_SUSPEND: |
2203 | state = 6; |
2204 | break; |
2205 | case FB_BLANK_HSYNC_SUSPEND: |
2206 | state = 5; |
2207 | break; |
2208 | case FB_BLANK_POWERDOWN: |
2209 | state = 7; |
2210 | break; |
2211 | case FB_BLANK_UNBLANK: |
2212 | default: |
2213 | state = 0; |
2214 | break; |
2215 | } |
2216 | aty_st_8(CRTC_EXT_CNTL+1, state); |
2217 | |
2218 | if (par->chip_gen == rage_M3) { |
2219 | aty128_set_crt_enable(par, on: par->crt_on && !blank); |
2220 | aty128_set_lcd_enable(par, on: par->lcd_on && !blank); |
2221 | } |
2222 | |
2223 | return 0; |
2224 | } |
2225 | |
2226 | /* |
2227 | * Set a single color register. The values supplied are already |
2228 | * rounded down to the hardware's capabilities (according to the |
2229 | * entries in the var structure). Return != 0 for invalid regno. |
2230 | */ |
2231 | static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, |
2232 | u_int transp, struct fb_info *info) |
2233 | { |
2234 | struct aty128fb_par *par = info->par; |
2235 | |
2236 | if (regno > 255 |
2237 | || (par->crtc.depth == 16 && regno > 63) |
2238 | || (par->crtc.depth == 15 && regno > 31)) |
2239 | return 1; |
2240 | |
2241 | red >>= 8; |
2242 | green >>= 8; |
2243 | blue >>= 8; |
2244 | |
2245 | if (regno < 16) { |
2246 | int i; |
2247 | u32 *pal = info->pseudo_palette; |
2248 | |
2249 | switch (par->crtc.depth) { |
2250 | case 15: |
2251 | pal[regno] = (regno << 10) | (regno << 5) | regno; |
2252 | break; |
2253 | case 16: |
2254 | pal[regno] = (regno << 11) | (regno << 6) | regno; |
2255 | break; |
2256 | case 24: |
2257 | pal[regno] = (regno << 16) | (regno << 8) | regno; |
2258 | break; |
2259 | case 32: |
2260 | i = (regno << 8) | regno; |
2261 | pal[regno] = (i << 16) | i; |
2262 | break; |
2263 | } |
2264 | } |
2265 | |
2266 | if (par->crtc.depth == 16 && regno > 0) { |
2267 | /* |
2268 | * With the 5-6-5 split of bits for RGB at 16 bits/pixel, we |
2269 | * have 32 slots for R and B values but 64 slots for G values. |
2270 | * Thus the R and B values go in one slot but the G value |
2271 | * goes in a different slot, and we have to avoid disturbing |
2272 | * the other fields in the slots we touch. |
2273 | */ |
2274 | par->green[regno] = green; |
2275 | if (regno < 32) { |
2276 | par->red[regno] = red; |
2277 | par->blue[regno] = blue; |
2278 | aty128_st_pal(regno: regno * 8, red, green: par->green[regno*2], |
2279 | blue, par); |
2280 | } |
2281 | red = par->red[regno/2]; |
2282 | blue = par->blue[regno/2]; |
2283 | regno <<= 2; |
2284 | } else if (par->crtc.bpp == 16) |
2285 | regno <<= 3; |
2286 | aty128_st_pal(regno, red, green, blue, par); |
2287 | |
2288 | return 0; |
2289 | } |
2290 | |
2291 | #define ATY_MIRROR_LCD_ON 0x00000001 |
2292 | #define ATY_MIRROR_CRT_ON 0x00000002 |
2293 | |
2294 | /* out param: u32* backlight value: 0 to 15 */ |
2295 | #define FBIO_ATY128_GET_MIRROR _IOR('@', 1, __u32) |
2296 | /* in param: u32* backlight value: 0 to 15 */ |
2297 | #define FBIO_ATY128_SET_MIRROR _IOW('@', 2, __u32) |
2298 | |
2299 | static int aty128fb_ioctl(struct fb_info *info, u_int cmd, u_long arg) |
2300 | { |
2301 | struct aty128fb_par *par = info->par; |
2302 | u32 value; |
2303 | int rc; |
2304 | |
2305 | switch (cmd) { |
2306 | case FBIO_ATY128_SET_MIRROR: |
2307 | if (par->chip_gen != rage_M3) |
2308 | return -EINVAL; |
2309 | rc = get_user(value, (__u32 __user *)arg); |
2310 | if (rc) |
2311 | return rc; |
2312 | par->lcd_on = (value & 0x01) != 0; |
2313 | par->crt_on = (value & 0x02) != 0; |
2314 | if (!par->crt_on && !par->lcd_on) |
2315 | par->lcd_on = 1; |
2316 | aty128_set_crt_enable(par, on: par->crt_on); |
2317 | aty128_set_lcd_enable(par, on: par->lcd_on); |
2318 | return 0; |
2319 | case FBIO_ATY128_GET_MIRROR: |
2320 | if (par->chip_gen != rage_M3) |
2321 | return -EINVAL; |
2322 | value = (par->crt_on << 1) | par->lcd_on; |
2323 | return put_user(value, (__u32 __user *)arg); |
2324 | } |
2325 | return -EINVAL; |
2326 | } |
2327 | |
2328 | static void aty128_set_suspend(struct aty128fb_par *par, int suspend) |
2329 | { |
2330 | u32 pmgt; |
2331 | |
2332 | if (!par->pdev->pm_cap) |
2333 | return; |
2334 | |
2335 | /* Set the chip into the appropriate suspend mode (we use D2, |
2336 | * D3 would require a complete re-initialisation of the chip, |
2337 | * including PCI config registers, clocks, AGP configuration, ...) |
2338 | * |
2339 | * For resume, the core will have already brought us back to D0 |
2340 | */ |
2341 | if (suspend) { |
2342 | /* Make sure CRTC2 is reset. Remove that the day we decide to |
2343 | * actually use CRTC2 and replace it with real code for disabling |
2344 | * the CRTC2 output during sleep |
2345 | */ |
2346 | aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) & |
2347 | ~(CRTC2_EN)); |
2348 | |
2349 | /* Set the power management mode to be PCI based */ |
2350 | /* Use this magic value for now */ |
2351 | pmgt = 0x0c005407; |
2352 | aty_st_pll(POWER_MANAGEMENT, pmgt); |
2353 | (void)aty_ld_pll(POWER_MANAGEMENT); |
2354 | aty_st_le32(BUS_CNTL1, 0x00000010); |
2355 | aty_st_le32(MEM_POWER_MISC, 0x0c830000); |
2356 | msleep(msecs: 100); |
2357 | } |
2358 | } |
2359 | |
2360 | static int aty128_pci_suspend_late(struct device *dev, pm_message_t state) |
2361 | { |
2362 | struct pci_dev *pdev = to_pci_dev(dev); |
2363 | struct fb_info *info = pci_get_drvdata(pdev); |
2364 | struct aty128fb_par *par = info->par; |
2365 | |
2366 | /* We don't do anything but D2, for now we return 0, but |
2367 | * we may want to change that. How do we know if the BIOS |
2368 | * can properly take care of D3 ? Also, with swsusp, we |
2369 | * know we'll be rebooted, ... |
2370 | */ |
2371 | #ifndef CONFIG_PPC_PMAC |
2372 | /* HACK ALERT ! Once I find a proper way to say to each driver |
2373 | * individually what will happen with it's PCI slot, I'll change |
2374 | * that. On laptops, the AGP slot is just unclocked, so D2 is |
2375 | * expected, while on desktops, the card is powered off |
2376 | */ |
2377 | return 0; |
2378 | #endif /* CONFIG_PPC_PMAC */ |
2379 | |
2380 | if (state.event == pdev->dev.power.power_state.event) |
2381 | return 0; |
2382 | |
2383 | printk(KERN_DEBUG "aty128fb: suspending...\n" ); |
2384 | |
2385 | console_lock(); |
2386 | |
2387 | fb_set_suspend(info, state: 1); |
2388 | |
2389 | /* Make sure engine is reset */ |
2390 | wait_for_idle(par); |
2391 | aty128_reset_engine(par); |
2392 | wait_for_idle(par); |
2393 | |
2394 | /* Blank display and LCD */ |
2395 | aty128fb_blank(blank: FB_BLANK_POWERDOWN, fb: info); |
2396 | |
2397 | /* Sleep */ |
2398 | par->asleep = 1; |
2399 | par->lock_blank = 1; |
2400 | |
2401 | #ifdef CONFIG_PPC_PMAC |
2402 | /* On powermac, we have hooks to properly suspend/resume AGP now, |
2403 | * use them here. We'll ultimately need some generic support here, |
2404 | * but the generic code isn't quite ready for that yet |
2405 | */ |
2406 | pmac_suspend_agp_for_card(pdev); |
2407 | #endif /* CONFIG_PPC_PMAC */ |
2408 | |
2409 | /* We need a way to make sure the fbdev layer will _not_ touch the |
2410 | * framebuffer before we put the chip to suspend state. On 2.4, I |
2411 | * used dummy fb ops, 2.5 need proper support for this at the |
2412 | * fbdev level |
2413 | */ |
2414 | if (state.event != PM_EVENT_ON) |
2415 | aty128_set_suspend(par, suspend: 1); |
2416 | |
2417 | console_unlock(); |
2418 | |
2419 | pdev->dev.power.power_state = state; |
2420 | |
2421 | return 0; |
2422 | } |
2423 | |
2424 | static int __maybe_unused aty128_pci_suspend(struct device *dev) |
2425 | { |
2426 | return aty128_pci_suspend_late(dev, PMSG_SUSPEND); |
2427 | } |
2428 | |
2429 | static int __maybe_unused aty128_pci_hibernate(struct device *dev) |
2430 | { |
2431 | return aty128_pci_suspend_late(dev, PMSG_HIBERNATE); |
2432 | } |
2433 | |
2434 | static int __maybe_unused aty128_pci_freeze(struct device *dev) |
2435 | { |
2436 | return aty128_pci_suspend_late(dev, PMSG_FREEZE); |
2437 | } |
2438 | |
2439 | static int aty128_do_resume(struct pci_dev *pdev) |
2440 | { |
2441 | struct fb_info *info = pci_get_drvdata(pdev); |
2442 | struct aty128fb_par *par = info->par; |
2443 | |
2444 | if (pdev->dev.power.power_state.event == PM_EVENT_ON) |
2445 | return 0; |
2446 | |
2447 | /* PCI state will have been restored by the core, so |
2448 | * we should be in D0 now with our config space fully |
2449 | * restored |
2450 | */ |
2451 | |
2452 | /* Wakeup chip */ |
2453 | aty128_set_suspend(par, suspend: 0); |
2454 | par->asleep = 0; |
2455 | |
2456 | /* Restore display & engine */ |
2457 | aty128_reset_engine(par); |
2458 | wait_for_idle(par); |
2459 | aty128fb_set_par(info); |
2460 | fb_pan_display(info, var: &info->var); |
2461 | fb_set_cmap(cmap: &info->cmap, fb_info: info); |
2462 | |
2463 | /* Refresh */ |
2464 | fb_set_suspend(info, state: 0); |
2465 | |
2466 | /* Unblank */ |
2467 | par->lock_blank = 0; |
2468 | aty128fb_blank(blank: 0, fb: info); |
2469 | |
2470 | #ifdef CONFIG_PPC_PMAC |
2471 | /* On powermac, we have hooks to properly suspend/resume AGP now, |
2472 | * use them here. We'll ultimately need some generic support here, |
2473 | * but the generic code isn't quite ready for that yet |
2474 | */ |
2475 | pmac_resume_agp_for_card(pdev); |
2476 | #endif /* CONFIG_PPC_PMAC */ |
2477 | |
2478 | pdev->dev.power.power_state = PMSG_ON; |
2479 | |
2480 | printk(KERN_DEBUG "aty128fb: resumed !\n" ); |
2481 | |
2482 | return 0; |
2483 | } |
2484 | |
2485 | static int __maybe_unused aty128_pci_resume(struct device *dev) |
2486 | { |
2487 | int rc; |
2488 | |
2489 | console_lock(); |
2490 | rc = aty128_do_resume(to_pci_dev(dev)); |
2491 | console_unlock(); |
2492 | |
2493 | return rc; |
2494 | } |
2495 | |
2496 | |
2497 | static int aty128fb_init(void) |
2498 | { |
2499 | #ifndef MODULE |
2500 | char *option = NULL; |
2501 | #endif |
2502 | |
2503 | if (fb_modesetting_disabled(drvname: "aty128fb" )) |
2504 | return -ENODEV; |
2505 | |
2506 | #ifndef MODULE |
2507 | if (fb_get_options(name: "aty128fb" , option: &option)) |
2508 | return -ENODEV; |
2509 | aty128fb_setup(options: option); |
2510 | #endif |
2511 | |
2512 | return pci_register_driver(&aty128fb_driver); |
2513 | } |
2514 | |
2515 | static void __exit aty128fb_exit(void) |
2516 | { |
2517 | pci_unregister_driver(dev: &aty128fb_driver); |
2518 | } |
2519 | |
2520 | module_init(aty128fb_init); |
2521 | |
2522 | module_exit(aty128fb_exit); |
2523 | |
2524 | MODULE_AUTHOR("(c)1999-2003 Brad Douglas <brad@neruo.com>" ); |
2525 | MODULE_DESCRIPTION("FBDev driver for ATI Rage128 / Pro cards" ); |
2526 | MODULE_LICENSE("GPL" ); |
2527 | module_param(mode_option, charp, 0); |
2528 | MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" " ); |
2529 | module_param_named(nomtrr, mtrr, invbool, 0); |
2530 | MODULE_PARM_DESC(nomtrr, "bool: Disable MTRR support (0 or 1=disabled) (default=0)" ); |
2531 | |