1/*
2 * Permedia2 framebuffer driver.
3 *
4 * 2.5/2.6 driver:
5 * Copyright (c) 2003 Jim Hague (jim.hague@acm.org)
6 *
7 * based on 2.4 driver:
8 * Copyright (c) 1998-2000 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
9 * Copyright (c) 1999 Jakub Jelinek (jakub@redhat.com)
10 *
11 * and additional input from James Simmon's port of Hannu Mallat's tdfx
12 * driver.
13 *
14 * I have a Creative Graphics Blaster Exxtreme card - pm2fb on x86. I
15 * have no access to other pm2fb implementations. Sparc (and thus
16 * hopefully other big-endian) devices now work, thanks to a lot of
17 * testing work by Ron Murray. I have no access to CVision hardware,
18 * and therefore for now I am omitting the CVision code.
19 *
20 * Multiple boards support has been on the TODO list for ages.
21 * Don't expect this to change.
22 *
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive for
25 * more details.
26 *
27 *
28 */
29
30#include <linux/module.h>
31#include <linux/moduleparam.h>
32#include <linux/kernel.h>
33#include <linux/errno.h>
34#include <linux/string.h>
35#include <linux/mm.h>
36#include <linux/slab.h>
37#include <linux/delay.h>
38#include <linux/fb.h>
39#include <linux/init.h>
40#include <linux/pci.h>
41#include <video/permedia2.h>
42#include <video/cvisionppc.h>
43
44#if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
45#error "The endianness of the target host has not been defined."
46#endif
47
48#if !defined(CONFIG_PCI)
49#error "Only generic PCI cards supported."
50#endif
51
52#undef PM2FB_MASTER_DEBUG
53#ifdef PM2FB_MASTER_DEBUG
54#define DPRINTK(a, b...) \
55 printk(KERN_DEBUG "pm2fb: %s: " a, __func__ , ## b)
56#else
57#define DPRINTK(a, b...)
58#endif
59
60#define PM2_PIXMAP_SIZE (1600 * 4)
61
62/*
63 * Driver data
64 */
65static int hwcursor = 1;
66static char *mode_option;
67
68/*
69 * The XFree GLINT driver will (I think to implement hardware cursor
70 * support on TVP4010 and similar where there is no RAMDAC - see
71 * comment in set_video) always request +ve sync regardless of what
72 * the mode requires. This screws me because I have a Sun
73 * fixed-frequency monitor which absolutely has to have -ve sync. So
74 * these flags allow the user to specify that requests for +ve sync
75 * should be silently turned in -ve sync.
76 */
77static bool lowhsync;
78static bool lowvsync;
79static bool noaccel;
80static bool nomtrr;
81
82/*
83 * The hardware state of the graphics card that isn't part of the
84 * screeninfo.
85 */
86struct pm2fb_par
87{
88 pm2type_t type; /* Board type */
89 unsigned char __iomem *v_regs;/* virtual address of p_regs */
90 u32 memclock; /* memclock */
91 u32 video; /* video flags before blanking */
92 u32 mem_config; /* MemConfig reg at probe */
93 u32 mem_control; /* MemControl reg at probe */
94 u32 boot_address; /* BootAddress reg at probe */
95 u32 palette[16];
96 int wc_cookie;
97};
98
99/*
100 * Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo
101 * if we don't use modedb.
102 */
103static struct fb_fix_screeninfo pm2fb_fix = {
104 .id = "",
105 .type = FB_TYPE_PACKED_PIXELS,
106 .visual = FB_VISUAL_PSEUDOCOLOR,
107 .xpanstep = 1,
108 .ypanstep = 1,
109 .ywrapstep = 0,
110 .accel = FB_ACCEL_3DLABS_PERMEDIA2,
111};
112
113/*
114 * Default video mode. In case the modedb doesn't work.
115 */
116static const struct fb_var_screeninfo pm2fb_var = {
117 /* "640x480, 8 bpp @ 60 Hz */
118 .xres = 640,
119 .yres = 480,
120 .xres_virtual = 640,
121 .yres_virtual = 480,
122 .bits_per_pixel = 8,
123 .red = {0, 8, 0},
124 .blue = {0, 8, 0},
125 .green = {0, 8, 0},
126 .activate = FB_ACTIVATE_NOW,
127 .height = -1,
128 .width = -1,
129 .accel_flags = 0,
130 .pixclock = 39721,
131 .left_margin = 40,
132 .right_margin = 24,
133 .upper_margin = 32,
134 .lower_margin = 11,
135 .hsync_len = 96,
136 .vsync_len = 2,
137 .vmode = FB_VMODE_NONINTERLACED
138};
139
140/*
141 * Utility functions
142 */
143
144static inline u32 pm2_RD(struct pm2fb_par *p, s32 off)
145{
146 return fb_readl(p->v_regs + off);
147}
148
149static inline void pm2_WR(struct pm2fb_par *p, s32 off, u32 v)
150{
151 fb_writel(v, p->v_regs + off);
152}
153
154static inline u32 pm2_RDAC_RD(struct pm2fb_par *p, s32 idx)
155{
156 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);
157 mb();
158 return pm2_RD(p, PM2R_RD_INDEXED_DATA);
159}
160
161static inline u32 pm2v_RDAC_RD(struct pm2fb_par *p, s32 idx)
162{
163 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
164 mb();
165 return pm2_RD(p, PM2VR_RD_INDEXED_DATA);
166}
167
168static inline void pm2_RDAC_WR(struct pm2fb_par *p, s32 idx, u32 v)
169{
170 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);
171 wmb();
172 pm2_WR(p, PM2R_RD_INDEXED_DATA, v);
173 wmb();
174}
175
176static inline void pm2v_RDAC_WR(struct pm2fb_par *p, s32 idx, u32 v)
177{
178 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
179 wmb();
180 pm2_WR(p, PM2VR_RD_INDEXED_DATA, v);
181 wmb();
182}
183
184#ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
185#define WAIT_FIFO(p, a)
186#else
187static inline void WAIT_FIFO(struct pm2fb_par *p, u32 a)
188{
189 while (pm2_RD(p, PM2R_IN_FIFO_SPACE) < a)
190 cpu_relax();
191}
192#endif
193
194/*
195 * partial products for the supported horizontal resolutions.
196 */
197#define PACKPP(p0, p1, p2) (((p2) << 6) | ((p1) << 3) | (p0))
198static const struct {
199 u16 width;
200 u16 pp;
201} pp_table[] = {
202 { 32, PACKPP(1, 0, 0) }, { 64, PACKPP(1, 1, 0) },
203 { 96, PACKPP(1, 1, 1) }, { 128, PACKPP(2, 1, 1) },
204 { 160, PACKPP(2, 2, 1) }, { 192, PACKPP(2, 2, 2) },
205 { 224, PACKPP(3, 2, 1) }, { 256, PACKPP(3, 2, 2) },
206 { 288, PACKPP(3, 3, 1) }, { 320, PACKPP(3, 3, 2) },
207 { 384, PACKPP(3, 3, 3) }, { 416, PACKPP(4, 3, 1) },
208 { 448, PACKPP(4, 3, 2) }, { 512, PACKPP(4, 3, 3) },
209 { 544, PACKPP(4, 4, 1) }, { 576, PACKPP(4, 4, 2) },
210 { 640, PACKPP(4, 4, 3) }, { 768, PACKPP(4, 4, 4) },
211 { 800, PACKPP(5, 4, 1) }, { 832, PACKPP(5, 4, 2) },
212 { 896, PACKPP(5, 4, 3) }, { 1024, PACKPP(5, 4, 4) },
213 { 1056, PACKPP(5, 5, 1) }, { 1088, PACKPP(5, 5, 2) },
214 { 1152, PACKPP(5, 5, 3) }, { 1280, PACKPP(5, 5, 4) },
215 { 1536, PACKPP(5, 5, 5) }, { 1568, PACKPP(6, 5, 1) },
216 { 1600, PACKPP(6, 5, 2) }, { 1664, PACKPP(6, 5, 3) },
217 { 1792, PACKPP(6, 5, 4) }, { 2048, PACKPP(6, 5, 5) },
218 { 0, 0 } };
219
220static u32 partprod(u32 xres)
221{
222 int i;
223
224 for (i = 0; pp_table[i].width && pp_table[i].width != xres; i++)
225 ;
226 if (pp_table[i].width == 0)
227 DPRINTK("invalid width %u\n", xres);
228 return pp_table[i].pp;
229}
230
231static u32 to3264(u32 timing, int bpp, int is64)
232{
233 switch (bpp) {
234 case 24:
235 timing *= 3;
236 /* fall through */
237 case 8:
238 timing >>= 1;
239 /* fall through */
240 case 16:
241 timing >>= 1;
242 case 32:
243 break;
244 }
245 if (is64)
246 timing >>= 1;
247 return timing;
248}
249
250static void pm2_mnp(u32 clk, unsigned char *mm, unsigned char *nn,
251 unsigned char *pp)
252{
253 unsigned char m;
254 unsigned char n;
255 unsigned char p;
256 u32 f;
257 s32 curr;
258 s32 delta = 100000;
259
260 *mm = *nn = *pp = 0;
261 for (n = 2; n < 15; n++) {
262 for (m = 2; m; m++) {
263 f = PM2_REFERENCE_CLOCK * m / n;
264 if (f >= 150000 && f <= 300000) {
265 for (p = 0; p < 5; p++, f >>= 1) {
266 curr = (clk > f) ? clk - f : f - clk;
267 if (curr < delta) {
268 delta = curr;
269 *mm = m;
270 *nn = n;
271 *pp = p;
272 }
273 }
274 }
275 }
276 }
277}
278
279static void pm2v_mnp(u32 clk, unsigned char *mm, unsigned char *nn,
280 unsigned char *pp)
281{
282 unsigned char m;
283 unsigned char n;
284 unsigned char p;
285 u32 f;
286 s32 delta = 1000;
287
288 *mm = *nn = *pp = 0;
289 for (m = 1; m < 128; m++) {
290 for (n = 2 * m + 1; n; n++) {
291 for (p = 0; p < 2; p++) {
292 f = (PM2_REFERENCE_CLOCK >> (p + 1)) * n / m;
293 if (clk > f - delta && clk < f + delta) {
294 delta = (clk > f) ? clk - f : f - clk;
295 *mm = m;
296 *nn = n;
297 *pp = p;
298 }
299 }
300 }
301 }
302}
303
304static void clear_palette(struct pm2fb_par *p)
305{
306 int i = 256;
307
308 WAIT_FIFO(p, 1);
309 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, 0);
310 wmb();
311 while (i--) {
312 WAIT_FIFO(p, 3);
313 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
314 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
315 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
316 }
317}
318
319static void reset_card(struct pm2fb_par *p)
320{
321 if (p->type == PM2_TYPE_PERMEDIA2V)
322 pm2_WR(p, PM2VR_RD_INDEX_HIGH, 0);
323 pm2_WR(p, PM2R_RESET_STATUS, 0);
324 mb();
325 while (pm2_RD(p, PM2R_RESET_STATUS) & PM2F_BEING_RESET)
326 cpu_relax();
327 mb();
328#ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
329 DPRINTK("FIFO disconnect enabled\n");
330 pm2_WR(p, PM2R_FIFO_DISCON, 1);
331 mb();
332#endif
333
334 /* Restore stashed memory config information from probe */
335 WAIT_FIFO(p, 3);
336 pm2_WR(p, PM2R_MEM_CONTROL, p->mem_control);
337 pm2_WR(p, PM2R_BOOT_ADDRESS, p->boot_address);
338 wmb();
339 pm2_WR(p, PM2R_MEM_CONFIG, p->mem_config);
340}
341
342static void reset_config(struct pm2fb_par *p)
343{
344 WAIT_FIFO(p, 53);
345 pm2_WR(p, PM2R_CHIP_CONFIG, pm2_RD(p, PM2R_CHIP_CONFIG) &
346 ~(PM2F_VGA_ENABLE | PM2F_VGA_FIXED));
347 pm2_WR(p, PM2R_BYPASS_WRITE_MASK, ~(0L));
348 pm2_WR(p, PM2R_FRAMEBUFFER_WRITE_MASK, ~(0L));
349 pm2_WR(p, PM2R_FIFO_CONTROL, 0);
350 pm2_WR(p, PM2R_APERTURE_ONE, 0);
351 pm2_WR(p, PM2R_APERTURE_TWO, 0);
352 pm2_WR(p, PM2R_RASTERIZER_MODE, 0);
353 pm2_WR(p, PM2R_DELTA_MODE, PM2F_DELTA_ORDER_RGB);
354 pm2_WR(p, PM2R_LB_READ_FORMAT, 0);
355 pm2_WR(p, PM2R_LB_WRITE_FORMAT, 0);
356 pm2_WR(p, PM2R_LB_READ_MODE, 0);
357 pm2_WR(p, PM2R_LB_SOURCE_OFFSET, 0);
358 pm2_WR(p, PM2R_FB_SOURCE_OFFSET, 0);
359 pm2_WR(p, PM2R_FB_PIXEL_OFFSET, 0);
360 pm2_WR(p, PM2R_FB_WINDOW_BASE, 0);
361 pm2_WR(p, PM2R_LB_WINDOW_BASE, 0);
362 pm2_WR(p, PM2R_FB_SOFT_WRITE_MASK, ~(0L));
363 pm2_WR(p, PM2R_FB_HARD_WRITE_MASK, ~(0L));
364 pm2_WR(p, PM2R_FB_READ_PIXEL, 0);
365 pm2_WR(p, PM2R_DITHER_MODE, 0);
366 pm2_WR(p, PM2R_AREA_STIPPLE_MODE, 0);
367 pm2_WR(p, PM2R_DEPTH_MODE, 0);
368 pm2_WR(p, PM2R_STENCIL_MODE, 0);
369 pm2_WR(p, PM2R_TEXTURE_ADDRESS_MODE, 0);
370 pm2_WR(p, PM2R_TEXTURE_READ_MODE, 0);
371 pm2_WR(p, PM2R_TEXEL_LUT_MODE, 0);
372 pm2_WR(p, PM2R_YUV_MODE, 0);
373 pm2_WR(p, PM2R_COLOR_DDA_MODE, 0);
374 pm2_WR(p, PM2R_TEXTURE_COLOR_MODE, 0);
375 pm2_WR(p, PM2R_FOG_MODE, 0);
376 pm2_WR(p, PM2R_ALPHA_BLEND_MODE, 0);
377 pm2_WR(p, PM2R_LOGICAL_OP_MODE, 0);
378 pm2_WR(p, PM2R_STATISTICS_MODE, 0);
379 pm2_WR(p, PM2R_SCISSOR_MODE, 0);
380 pm2_WR(p, PM2R_FILTER_MODE, PM2F_SYNCHRONIZATION);
381 pm2_WR(p, PM2R_RD_PIXEL_MASK, 0xff);
382 switch (p->type) {
383 case PM2_TYPE_PERMEDIA2:
384 pm2_RDAC_WR(p, PM2I_RD_MODE_CONTROL, 0); /* no overlay */
385 pm2_RDAC_WR(p, PM2I_RD_CURSOR_CONTROL, 0);
386 pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, PM2F_RD_PALETTE_WIDTH_8);
387 pm2_RDAC_WR(p, PM2I_RD_COLOR_KEY_CONTROL, 0);
388 pm2_RDAC_WR(p, PM2I_RD_OVERLAY_KEY, 0);
389 pm2_RDAC_WR(p, PM2I_RD_RED_KEY, 0);
390 pm2_RDAC_WR(p, PM2I_RD_GREEN_KEY, 0);
391 pm2_RDAC_WR(p, PM2I_RD_BLUE_KEY, 0);
392 break;
393 case PM2_TYPE_PERMEDIA2V:
394 pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1); /* 8bit */
395 break;
396 }
397}
398
399static void set_aperture(struct pm2fb_par *p, u32 depth)
400{
401 /*
402 * The hardware is little-endian. When used in big-endian
403 * hosts, the on-chip aperture settings are used where
404 * possible to translate from host to card byte order.
405 */
406 WAIT_FIFO(p, 2);
407#ifdef __LITTLE_ENDIAN
408 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);
409#else
410 switch (depth) {
411 case 24: /* RGB->BGR */
412 /*
413 * We can't use the aperture to translate host to
414 * card byte order here, so we switch to BGR mode
415 * in pm2fb_set_par().
416 */
417 case 8: /* B->B */
418 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);
419 break;
420 case 16: /* HL->LH */
421 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_HALFWORDSWAP);
422 break;
423 case 32: /* RGBA->ABGR */
424 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_BYTESWAP);
425 break;
426 }
427#endif
428
429 /* We don't use aperture two, so this may be superflous */
430 pm2_WR(p, PM2R_APERTURE_TWO, PM2F_APERTURE_STANDARD);
431}
432
433static void set_color(struct pm2fb_par *p, unsigned char regno,
434 unsigned char r, unsigned char g, unsigned char b)
435{
436 WAIT_FIFO(p, 4);
437 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, regno);
438 wmb();
439 pm2_WR(p, PM2R_RD_PALETTE_DATA, r);
440 wmb();
441 pm2_WR(p, PM2R_RD_PALETTE_DATA, g);
442 wmb();
443 pm2_WR(p, PM2R_RD_PALETTE_DATA, b);
444}
445
446static void set_memclock(struct pm2fb_par *par, u32 clk)
447{
448 int i;
449 unsigned char m, n, p;
450
451 switch (par->type) {
452 case PM2_TYPE_PERMEDIA2V:
453 pm2v_mnp(clk/2, &m, &n, &p);
454 WAIT_FIFO(par, 12);
455 pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_MCLK_CONTROL >> 8);
456 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 0);
457 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_PRESCALE, m);
458 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_FEEDBACK, n);
459 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_POSTSCALE, p);
460 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 1);
461 rmb();
462 for (i = 256; i; i--)
463 if (pm2v_RDAC_RD(par, PM2VI_RD_MCLK_CONTROL) & 2)
464 break;
465 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
466 break;
467 case PM2_TYPE_PERMEDIA2:
468 pm2_mnp(clk, &m, &n, &p);
469 WAIT_FIFO(par, 10);
470 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 6);
471 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_1, m);
472 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_2, n);
473 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 8|p);
474 pm2_RDAC_RD(par, PM2I_RD_MEMORY_CLOCK_STATUS);
475 rmb();
476 for (i = 256; i; i--)
477 if (pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED)
478 break;
479 break;
480 }
481}
482
483static void set_pixclock(struct pm2fb_par *par, u32 clk)
484{
485 int i;
486 unsigned char m, n, p;
487
488 switch (par->type) {
489 case PM2_TYPE_PERMEDIA2:
490 pm2_mnp(clk, &m, &n, &p);
491 WAIT_FIFO(par, 10);
492 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 0);
493 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A1, m);
494 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A2, n);
495 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 8|p);
496 pm2_RDAC_RD(par, PM2I_RD_PIXEL_CLOCK_STATUS);
497 rmb();
498 for (i = 256; i; i--)
499 if (pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED)
500 break;
501 break;
502 case PM2_TYPE_PERMEDIA2V:
503 pm2v_mnp(clk/2, &m, &n, &p);
504 WAIT_FIFO(par, 8);
505 pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_CLK0_PRESCALE >> 8);
506 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_PRESCALE, m);
507 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_FEEDBACK, n);
508 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_POSTSCALE, p);
509 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
510 break;
511 }
512}
513
514static void set_video(struct pm2fb_par *p, u32 video)
515{
516 u32 tmp;
517 u32 vsync = video;
518
519 DPRINTK("video = 0x%x\n", video);
520
521 /*
522 * The hardware cursor needs +vsync to recognise vert retrace.
523 * We may not be using the hardware cursor, but the X Glint
524 * driver may well. So always set +hsync/+vsync and then set
525 * the RAMDAC to invert the sync if necessary.
526 */
527 vsync &= ~(PM2F_HSYNC_MASK | PM2F_VSYNC_MASK);
528 vsync |= PM2F_HSYNC_ACT_HIGH | PM2F_VSYNC_ACT_HIGH;
529
530 WAIT_FIFO(p, 3);
531 pm2_WR(p, PM2R_VIDEO_CONTROL, vsync);
532
533 switch (p->type) {
534 case PM2_TYPE_PERMEDIA2:
535 tmp = PM2F_RD_PALETTE_WIDTH_8;
536 if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)
537 tmp |= 4; /* invert hsync */
538 if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
539 tmp |= 8; /* invert vsync */
540 pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, tmp);
541 break;
542 case PM2_TYPE_PERMEDIA2V:
543 tmp = 0;
544 if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)
545 tmp |= 1; /* invert hsync */
546 if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
547 tmp |= 4; /* invert vsync */
548 pm2v_RDAC_WR(p, PM2VI_RD_SYNC_CONTROL, tmp);
549 break;
550 }
551}
552
553/*
554 * pm2fb_check_var - Optional function. Validates a var passed in.
555 * @var: frame buffer variable screen structure
556 * @info: frame buffer structure that represents a single frame buffer
557 *
558 * Checks to see if the hardware supports the state requested by
559 * var passed in.
560 *
561 * Returns negative errno on error, or zero on success.
562 */
563static int pm2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
564{
565 u32 lpitch;
566
567 if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 &&
568 var->bits_per_pixel != 24 && var->bits_per_pixel != 32) {
569 DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
570 return -EINVAL;
571 }
572
573 if (var->xres != var->xres_virtual) {
574 DPRINTK("virtual x resolution != "
575 "physical x resolution not supported\n");
576 return -EINVAL;
577 }
578
579 if (var->yres > var->yres_virtual) {
580 DPRINTK("virtual y resolution < "
581 "physical y resolution not possible\n");
582 return -EINVAL;
583 }
584
585 /* permedia cannot blit over 2048 */
586 if (var->yres_virtual > 2047) {
587 var->yres_virtual = 2047;
588 }
589
590 if (var->xoffset) {
591 DPRINTK("xoffset not supported\n");
592 return -EINVAL;
593 }
594
595 if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
596 DPRINTK("interlace not supported\n");
597 return -EINVAL;
598 }
599
600 var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */
601 lpitch = var->xres * ((var->bits_per_pixel + 7) >> 3);
602
603 if (var->xres < 320 || var->xres > 1600) {
604 DPRINTK("width not supported: %u\n", var->xres);
605 return -EINVAL;
606 }
607
608 if (var->yres < 200 || var->yres > 1200) {
609 DPRINTK("height not supported: %u\n", var->yres);
610 return -EINVAL;
611 }
612
613 if (lpitch * var->yres_virtual > info->fix.smem_len) {
614 DPRINTK("no memory for screen (%ux%ux%u)\n",
615 var->xres, var->yres_virtual, var->bits_per_pixel);
616 return -EINVAL;
617 }
618
619 if (PICOS2KHZ(var->pixclock) > PM2_MAX_PIXCLOCK) {
620 DPRINTK("pixclock too high (%ldKHz)\n",
621 PICOS2KHZ(var->pixclock));
622 return -EINVAL;
623 }
624
625 var->transp.offset = 0;
626 var->transp.length = 0;
627 switch (var->bits_per_pixel) {
628 case 8:
629 var->red.length = 8;
630 var->green.length = 8;
631 var->blue.length = 8;
632 break;
633 case 16:
634 var->red.offset = 11;
635 var->red.length = 5;
636 var->green.offset = 5;
637 var->green.length = 6;
638 var->blue.offset = 0;
639 var->blue.length = 5;
640 break;
641 case 32:
642 var->transp.offset = 24;
643 var->transp.length = 8;
644 var->red.offset = 16;
645 var->green.offset = 8;
646 var->blue.offset = 0;
647 var->red.length = 8;
648 var->green.length = 8;
649 var->blue.length = 8;
650 break;
651 case 24:
652#ifdef __BIG_ENDIAN
653 var->red.offset = 0;
654 var->blue.offset = 16;
655#else
656 var->red.offset = 16;
657 var->blue.offset = 0;
658#endif
659 var->green.offset = 8;
660 var->red.length = 8;
661 var->green.length = 8;
662 var->blue.length = 8;
663 break;
664 }
665 var->height = -1;
666 var->width = -1;
667
668 var->accel_flags = 0; /* Can't mmap if this is on */
669
670 DPRINTK("Checking graphics mode at %dx%d depth %d\n",
671 var->xres, var->yres, var->bits_per_pixel);
672 return 0;
673}
674
675/**
676 * pm2fb_set_par - Alters the hardware state.
677 * @info: frame buffer structure that represents a single frame buffer
678 *
679 * Using the fb_var_screeninfo in fb_info we set the resolution of the
680 * this particular framebuffer.
681 */
682static int pm2fb_set_par(struct fb_info *info)
683{
684 struct pm2fb_par *par = info->par;
685 u32 pixclock;
686 u32 width = (info->var.xres_virtual + 7) & ~7;
687 u32 height = info->var.yres_virtual;
688 u32 depth = (info->var.bits_per_pixel + 7) & ~7;
689 u32 hsstart, hsend, hbend, htotal;
690 u32 vsstart, vsend, vbend, vtotal;
691 u32 stride;
692 u32 base;
693 u32 video = 0;
694 u32 clrmode = PM2F_RD_COLOR_MODE_RGB | PM2F_RD_GUI_ACTIVE;
695 u32 txtmap = 0;
696 u32 pixsize = 0;
697 u32 clrformat = 0;
698 u32 misc = 1; /* 8-bit DAC */
699 u32 xres = (info->var.xres + 31) & ~31;
700 int data64;
701
702 reset_card(par);
703 reset_config(par);
704 clear_palette(par);
705 if (par->memclock)
706 set_memclock(par, par->memclock);
707
708 depth = (depth > 32) ? 32 : depth;
709 data64 = depth > 8 || par->type == PM2_TYPE_PERMEDIA2V;
710
711 pixclock = PICOS2KHZ(info->var.pixclock);
712 if (pixclock > PM2_MAX_PIXCLOCK) {
713 DPRINTK("pixclock too high (%uKHz)\n", pixclock);
714 return -EINVAL;
715 }
716
717 hsstart = to3264(info->var.right_margin, depth, data64);
718 hsend = hsstart + to3264(info->var.hsync_len, depth, data64);
719 hbend = hsend + to3264(info->var.left_margin, depth, data64);
720 htotal = to3264(xres, depth, data64) + hbend - 1;
721 vsstart = (info->var.lower_margin)
722 ? info->var.lower_margin - 1
723 : 0; /* FIXME! */
724 vsend = info->var.lower_margin + info->var.vsync_len - 1;
725 vbend = info->var.lower_margin + info->var.vsync_len +
726 info->var.upper_margin;
727 vtotal = info->var.yres + vbend - 1;
728 stride = to3264(width, depth, 1);
729 base = to3264(info->var.yoffset * xres + info->var.xoffset, depth, 1);
730 if (data64)
731 video |= PM2F_DATA_64_ENABLE;
732
733 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) {
734 if (lowhsync) {
735 DPRINTK("ignoring +hsync, using -hsync.\n");
736 video |= PM2F_HSYNC_ACT_LOW;
737 } else
738 video |= PM2F_HSYNC_ACT_HIGH;
739 } else
740 video |= PM2F_HSYNC_ACT_LOW;
741
742 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) {
743 if (lowvsync) {
744 DPRINTK("ignoring +vsync, using -vsync.\n");
745 video |= PM2F_VSYNC_ACT_LOW;
746 } else
747 video |= PM2F_VSYNC_ACT_HIGH;
748 } else
749 video |= PM2F_VSYNC_ACT_LOW;
750
751 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
752 DPRINTK("interlaced not supported\n");
753 return -EINVAL;
754 }
755 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE)
756 video |= PM2F_LINE_DOUBLE;
757 if ((info->var.activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
758 video |= PM2F_VIDEO_ENABLE;
759 par->video = video;
760
761 info->fix.visual =
762 (depth == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
763 info->fix.line_length = info->var.xres * depth / 8;
764 info->cmap.len = 256;
765
766 /*
767 * Settings calculated. Now write them out.
768 */
769 if (par->type == PM2_TYPE_PERMEDIA2V) {
770 WAIT_FIFO(par, 1);
771 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
772 }
773
774 set_aperture(par, depth);
775
776 mb();
777 WAIT_FIFO(par, 19);
778 switch (depth) {
779 case 8:
780 pm2_WR(par, PM2R_FB_READ_PIXEL, 0);
781 clrformat = 0x2e;
782 break;
783 case 16:
784 pm2_WR(par, PM2R_FB_READ_PIXEL, 1);
785 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB565;
786 txtmap = PM2F_TEXTEL_SIZE_16;
787 pixsize = 1;
788 clrformat = 0x70;
789 misc |= 8;
790 break;
791 case 32:
792 pm2_WR(par, PM2R_FB_READ_PIXEL, 2);
793 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGBA8888;
794 txtmap = PM2F_TEXTEL_SIZE_32;
795 pixsize = 2;
796 clrformat = 0x20;
797 misc |= 8;
798 break;
799 case 24:
800 pm2_WR(par, PM2R_FB_READ_PIXEL, 4);
801 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB888;
802 txtmap = PM2F_TEXTEL_SIZE_24;
803 pixsize = 4;
804 clrformat = 0x20;
805 misc |= 8;
806 break;
807 }
808 pm2_WR(par, PM2R_FB_WRITE_MODE, PM2F_FB_WRITE_ENABLE);
809 pm2_WR(par, PM2R_FB_READ_MODE, partprod(xres));
810 pm2_WR(par, PM2R_LB_READ_MODE, partprod(xres));
811 pm2_WR(par, PM2R_TEXTURE_MAP_FORMAT, txtmap | partprod(xres));
812 pm2_WR(par, PM2R_H_TOTAL, htotal);
813 pm2_WR(par, PM2R_HS_START, hsstart);
814 pm2_WR(par, PM2R_HS_END, hsend);
815 pm2_WR(par, PM2R_HG_END, hbend);
816 pm2_WR(par, PM2R_HB_END, hbend);
817 pm2_WR(par, PM2R_V_TOTAL, vtotal);
818 pm2_WR(par, PM2R_VS_START, vsstart);
819 pm2_WR(par, PM2R_VS_END, vsend);
820 pm2_WR(par, PM2R_VB_END, vbend);
821 pm2_WR(par, PM2R_SCREEN_STRIDE, stride);
822 wmb();
823 pm2_WR(par, PM2R_WINDOW_ORIGIN, 0);
824 pm2_WR(par, PM2R_SCREEN_SIZE, (height << 16) | width);
825 pm2_WR(par, PM2R_SCISSOR_MODE, PM2F_SCREEN_SCISSOR_ENABLE);
826 wmb();
827 pm2_WR(par, PM2R_SCREEN_BASE, base);
828 wmb();
829 set_video(par, video);
830 WAIT_FIFO(par, 10);
831 switch (par->type) {
832 case PM2_TYPE_PERMEDIA2:
833 pm2_RDAC_WR(par, PM2I_RD_COLOR_MODE, clrmode);
834 pm2_RDAC_WR(par, PM2I_RD_COLOR_KEY_CONTROL,
835 (depth == 8) ? 0 : PM2F_COLOR_KEY_TEST_OFF);
836 break;
837 case PM2_TYPE_PERMEDIA2V:
838 pm2v_RDAC_WR(par, PM2VI_RD_DAC_CONTROL, 0);
839 pm2v_RDAC_WR(par, PM2VI_RD_PIXEL_SIZE, pixsize);
840 pm2v_RDAC_WR(par, PM2VI_RD_COLOR_FORMAT, clrformat);
841 pm2v_RDAC_WR(par, PM2VI_RD_MISC_CONTROL, misc);
842 pm2v_RDAC_WR(par, PM2VI_RD_OVERLAY_KEY, 0);
843 break;
844 }
845 set_pixclock(par, pixclock);
846 DPRINTK("Setting graphics mode at %dx%d depth %d\n",
847 info->var.xres, info->var.yres, info->var.bits_per_pixel);
848 return 0;
849}
850
851/**
852 * pm2fb_setcolreg - Sets a color register.
853 * @regno: boolean, 0 copy local, 1 get_user() function
854 * @red: frame buffer colormap structure
855 * @green: The green value which can be up to 16 bits wide
856 * @blue: The blue value which can be up to 16 bits wide.
857 * @transp: If supported the alpha value which can be up to 16 bits wide.
858 * @info: frame buffer info structure
859 *
860 * Set a single color register. The values supplied have a 16 bit
861 * magnitude which needs to be scaled in this function for the hardware.
862 * Pretty much a direct lift from tdfxfb.c.
863 *
864 * Returns negative errno on error, or zero on success.
865 */
866static int pm2fb_setcolreg(unsigned regno, unsigned red, unsigned green,
867 unsigned blue, unsigned transp,
868 struct fb_info *info)
869{
870 struct pm2fb_par *par = info->par;
871
872 if (regno >= info->cmap.len) /* no. of hw registers */
873 return -EINVAL;
874 /*
875 * Program hardware... do anything you want with transp
876 */
877
878 /* grayscale works only partially under directcolor */
879 /* grayscale = 0.30*R + 0.59*G + 0.11*B */
880 if (info->var.grayscale)
881 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
882
883 /* Directcolor:
884 * var->{color}.offset contains start of bitfield
885 * var->{color}.length contains length of bitfield
886 * {hardwarespecific} contains width of DAC
887 * cmap[X] is programmed to
888 * (X << red.offset) | (X << green.offset) | (X << blue.offset)
889 * RAMDAC[X] is programmed to (red, green, blue)
890 *
891 * Pseudocolor:
892 * uses offset = 0 && length = DAC register width.
893 * var->{color}.offset is 0
894 * var->{color}.length contains width of DAC
895 * cmap is not used
896 * DAC[X] is programmed to (red, green, blue)
897 * Truecolor:
898 * does not use RAMDAC (usually has 3 of them).
899 * var->{color}.offset contains start of bitfield
900 * var->{color}.length contains length of bitfield
901 * cmap is programmed to
902 * (red << red.offset) | (green << green.offset) |
903 * (blue << blue.offset) | (transp << transp.offset)
904 * RAMDAC does not exist
905 */
906#define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF -(val)) >> 16)
907 switch (info->fix.visual) {
908 case FB_VISUAL_TRUECOLOR:
909 case FB_VISUAL_PSEUDOCOLOR:
910 red = CNVT_TOHW(red, info->var.red.length);
911 green = CNVT_TOHW(green, info->var.green.length);
912 blue = CNVT_TOHW(blue, info->var.blue.length);
913 transp = CNVT_TOHW(transp, info->var.transp.length);
914 break;
915 case FB_VISUAL_DIRECTCOLOR:
916 /* example here assumes 8 bit DAC. Might be different
917 * for your hardware */
918 red = CNVT_TOHW(red, 8);
919 green = CNVT_TOHW(green, 8);
920 blue = CNVT_TOHW(blue, 8);
921 /* hey, there is bug in transp handling... */
922 transp = CNVT_TOHW(transp, 8);
923 break;
924 }
925#undef CNVT_TOHW
926 /* Truecolor has hardware independent palette */
927 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
928 u32 v;
929
930 if (regno >= 16)
931 return -EINVAL;
932
933 v = (red << info->var.red.offset) |
934 (green << info->var.green.offset) |
935 (blue << info->var.blue.offset) |
936 (transp << info->var.transp.offset);
937
938 switch (info->var.bits_per_pixel) {
939 case 8:
940 break;
941 case 16:
942 case 24:
943 case 32:
944 par->palette[regno] = v;
945 break;
946 }
947 return 0;
948 } else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR)
949 set_color(par, regno, red, green, blue);
950
951 return 0;
952}
953
954/**
955 * pm2fb_pan_display - Pans the display.
956 * @var: frame buffer variable screen structure
957 * @info: frame buffer structure that represents a single frame buffer
958 *
959 * Pan (or wrap, depending on the `vmode' field) the display using the
960 * `xoffset' and `yoffset' fields of the `var' structure.
961 * If the values don't fit, return -EINVAL.
962 *
963 * Returns negative errno on error, or zero on success.
964 *
965 */
966static int pm2fb_pan_display(struct fb_var_screeninfo *var,
967 struct fb_info *info)
968{
969 struct pm2fb_par *p = info->par;
970 u32 base;
971 u32 depth = (info->var.bits_per_pixel + 7) & ~7;
972 u32 xres = (info->var.xres + 31) & ~31;
973
974 depth = (depth > 32) ? 32 : depth;
975 base = to3264(var->yoffset * xres + var->xoffset, depth, 1);
976 WAIT_FIFO(p, 1);
977 pm2_WR(p, PM2R_SCREEN_BASE, base);
978 return 0;
979}
980
981/**
982 * pm2fb_blank - Blanks the display.
983 * @blank_mode: the blank mode we want.
984 * @info: frame buffer structure that represents a single frame buffer
985 *
986 * Blank the screen if blank_mode != 0, else unblank. Return 0 if
987 * blanking succeeded, != 0 if un-/blanking failed due to e.g. a
988 * video mode which doesn't support it. Implements VESA suspend
989 * and powerdown modes on hardware that supports disabling hsync/vsync:
990 * blank_mode == 2: suspend vsync
991 * blank_mode == 3: suspend hsync
992 * blank_mode == 4: powerdown
993 *
994 * Returns negative errno on error, or zero on success.
995 *
996 */
997static int pm2fb_blank(int blank_mode, struct fb_info *info)
998{
999 struct pm2fb_par *par = info->par;
1000 u32 video = par->video;
1001
1002 DPRINTK("blank_mode %d\n", blank_mode);
1003
1004 switch (blank_mode) {
1005 case FB_BLANK_UNBLANK:
1006 /* Screen: On */
1007 video |= PM2F_VIDEO_ENABLE;
1008 break;
1009 case FB_BLANK_NORMAL:
1010 /* Screen: Off */
1011 video &= ~PM2F_VIDEO_ENABLE;
1012 break;
1013 case FB_BLANK_VSYNC_SUSPEND:
1014 /* VSync: Off */
1015 video &= ~(PM2F_VSYNC_MASK | PM2F_BLANK_LOW);
1016 break;
1017 case FB_BLANK_HSYNC_SUSPEND:
1018 /* HSync: Off */
1019 video &= ~(PM2F_HSYNC_MASK | PM2F_BLANK_LOW);
1020 break;
1021 case FB_BLANK_POWERDOWN:
1022 /* HSync: Off, VSync: Off */
1023 video &= ~(PM2F_VSYNC_MASK | PM2F_HSYNC_MASK | PM2F_BLANK_LOW);
1024 break;
1025 }
1026 set_video(par, video);
1027 return 0;
1028}
1029
1030static int pm2fb_sync(struct fb_info *info)
1031{
1032 struct pm2fb_par *par = info->par;
1033
1034 WAIT_FIFO(par, 1);
1035 pm2_WR(par, PM2R_SYNC, 0);
1036 mb();
1037 do {
1038 while (pm2_RD(par, PM2R_OUT_FIFO_WORDS) == 0)
1039 cpu_relax();
1040 } while (pm2_RD(par, PM2R_OUT_FIFO) != PM2TAG(PM2R_SYNC));
1041
1042 return 0;
1043}
1044
1045static void pm2fb_fillrect(struct fb_info *info,
1046 const struct fb_fillrect *region)
1047{
1048 struct pm2fb_par *par = info->par;
1049 struct fb_fillrect modded;
1050 int vxres, vyres;
1051 u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
1052 ((u32 *)info->pseudo_palette)[region->color] : region->color;
1053
1054 if (info->state != FBINFO_STATE_RUNNING)
1055 return;
1056 if ((info->flags & FBINFO_HWACCEL_DISABLED) ||
1057 region->rop != ROP_COPY ) {
1058 cfb_fillrect(info, region);
1059 return;
1060 }
1061
1062 vxres = info->var.xres_virtual;
1063 vyres = info->var.yres_virtual;
1064
1065 memcpy(&modded, region, sizeof(struct fb_fillrect));
1066
1067 if (!modded.width || !modded.height ||
1068 modded.dx >= vxres || modded.dy >= vyres)
1069 return;
1070
1071 if (modded.dx + modded.width > vxres)
1072 modded.width = vxres - modded.dx;
1073 if (modded.dy + modded.height > vyres)
1074 modded.height = vyres - modded.dy;
1075
1076 if (info->var.bits_per_pixel == 8)
1077 color |= color << 8;
1078 if (info->var.bits_per_pixel <= 16)
1079 color |= color << 16;
1080
1081 WAIT_FIFO(par, 3);
1082 pm2_WR(par, PM2R_CONFIG, PM2F_CONFIG_FB_WRITE_ENABLE);
1083 pm2_WR(par, PM2R_RECTANGLE_ORIGIN, (modded.dy << 16) | modded.dx);
1084 pm2_WR(par, PM2R_RECTANGLE_SIZE, (modded.height << 16) | modded.width);
1085 if (info->var.bits_per_pixel != 24) {
1086 WAIT_FIFO(par, 2);
1087 pm2_WR(par, PM2R_FB_BLOCK_COLOR, color);
1088 wmb();
1089 pm2_WR(par, PM2R_RENDER,
1090 PM2F_RENDER_RECTANGLE | PM2F_RENDER_FASTFILL);
1091 } else {
1092 WAIT_FIFO(par, 4);
1093 pm2_WR(par, PM2R_COLOR_DDA_MODE, 1);
1094 pm2_WR(par, PM2R_CONSTANT_COLOR, color);
1095 wmb();
1096 pm2_WR(par, PM2R_RENDER,
1097 PM2F_RENDER_RECTANGLE |
1098 PM2F_INCREASE_X | PM2F_INCREASE_Y );
1099 pm2_WR(par, PM2R_COLOR_DDA_MODE, 0);
1100 }
1101}
1102
1103static void pm2fb_copyarea(struct fb_info *info,
1104 const struct fb_copyarea *area)
1105{
1106 struct pm2fb_par *par = info->par;
1107 struct fb_copyarea modded;
1108 u32 vxres, vyres;
1109
1110 if (info->state != FBINFO_STATE_RUNNING)
1111 return;
1112 if (info->flags & FBINFO_HWACCEL_DISABLED) {
1113 cfb_copyarea(info, area);
1114 return;
1115 }
1116
1117 memcpy(&modded, area, sizeof(struct fb_copyarea));
1118
1119 vxres = info->var.xres_virtual;
1120 vyres = info->var.yres_virtual;
1121
1122 if (!modded.width || !modded.height ||
1123 modded.sx >= vxres || modded.sy >= vyres ||
1124 modded.dx >= vxres || modded.dy >= vyres)
1125 return;
1126
1127 if (modded.sx + modded.width > vxres)
1128 modded.width = vxres - modded.sx;
1129 if (modded.dx + modded.width > vxres)
1130 modded.width = vxres - modded.dx;
1131 if (modded.sy + modded.height > vyres)
1132 modded.height = vyres - modded.sy;
1133 if (modded.dy + modded.height > vyres)
1134 modded.height = vyres - modded.dy;
1135
1136 WAIT_FIFO(par, 5);
1137 pm2_WR(par, PM2R_CONFIG, PM2F_CONFIG_FB_WRITE_ENABLE |
1138 PM2F_CONFIG_FB_READ_SOURCE_ENABLE);
1139 pm2_WR(par, PM2R_FB_SOURCE_DELTA,
1140 ((modded.sy - modded.dy) & 0xfff) << 16 |
1141 ((modded.sx - modded.dx) & 0xfff));
1142 pm2_WR(par, PM2R_RECTANGLE_ORIGIN, (modded.dy << 16) | modded.dx);
1143 pm2_WR(par, PM2R_RECTANGLE_SIZE, (modded.height << 16) | modded.width);
1144 wmb();
1145 pm2_WR(par, PM2R_RENDER, PM2F_RENDER_RECTANGLE |
1146 (modded.dx < modded.sx ? PM2F_INCREASE_X : 0) |
1147 (modded.dy < modded.sy ? PM2F_INCREASE_Y : 0));
1148}
1149
1150static void pm2fb_imageblit(struct fb_info *info, const struct fb_image *image)
1151{
1152 struct pm2fb_par *par = info->par;
1153 u32 height = image->height;
1154 u32 fgx, bgx;
1155 const u32 *src = (const u32 *)image->data;
1156 u32 xres = (info->var.xres + 31) & ~31;
1157 int raster_mode = 1; /* invert bits */
1158
1159#ifdef __LITTLE_ENDIAN
1160 raster_mode |= 3 << 7; /* reverse byte order */
1161#endif
1162
1163 if (info->state != FBINFO_STATE_RUNNING)
1164 return;
1165 if (info->flags & FBINFO_HWACCEL_DISABLED || image->depth != 1) {
1166 cfb_imageblit(info, image);
1167 return;
1168 }
1169 switch (info->fix.visual) {
1170 case FB_VISUAL_PSEUDOCOLOR:
1171 fgx = image->fg_color;
1172 bgx = image->bg_color;
1173 break;
1174 case FB_VISUAL_TRUECOLOR:
1175 default:
1176 fgx = par->palette[image->fg_color];
1177 bgx = par->palette[image->bg_color];
1178 break;
1179 }
1180 if (info->var.bits_per_pixel == 8) {
1181 fgx |= fgx << 8;
1182 bgx |= bgx << 8;
1183 }
1184 if (info->var.bits_per_pixel <= 16) {
1185 fgx |= fgx << 16;
1186 bgx |= bgx << 16;
1187 }
1188
1189 WAIT_FIFO(par, 13);
1190 pm2_WR(par, PM2R_FB_READ_MODE, partprod(xres));
1191 pm2_WR(par, PM2R_SCISSOR_MIN_XY,
1192 ((image->dy & 0xfff) << 16) | (image->dx & 0x0fff));
1193 pm2_WR(par, PM2R_SCISSOR_MAX_XY,
1194 (((image->dy + image->height) & 0x0fff) << 16) |
1195 ((image->dx + image->width) & 0x0fff));
1196 pm2_WR(par, PM2R_SCISSOR_MODE, 1);
1197 /* GXcopy & UNIT_ENABLE */
1198 pm2_WR(par, PM2R_LOGICAL_OP_MODE, (0x3 << 1) | 1);
1199 pm2_WR(par, PM2R_RECTANGLE_ORIGIN,
1200 ((image->dy & 0xfff) << 16) | (image->dx & 0x0fff));
1201 pm2_WR(par, PM2R_RECTANGLE_SIZE,
1202 ((image->height & 0x0fff) << 16) |
1203 ((image->width) & 0x0fff));
1204 if (info->var.bits_per_pixel == 24) {
1205 pm2_WR(par, PM2R_COLOR_DDA_MODE, 1);
1206 /* clear area */
1207 pm2_WR(par, PM2R_CONSTANT_COLOR, bgx);
1208 pm2_WR(par, PM2R_RENDER,
1209 PM2F_RENDER_RECTANGLE |
1210 PM2F_INCREASE_X | PM2F_INCREASE_Y);
1211 /* BitMapPackEachScanline */
1212 pm2_WR(par, PM2R_RASTERIZER_MODE, raster_mode | (1 << 9));
1213 pm2_WR(par, PM2R_CONSTANT_COLOR, fgx);
1214 pm2_WR(par, PM2R_RENDER,
1215 PM2F_RENDER_RECTANGLE |
1216 PM2F_INCREASE_X | PM2F_INCREASE_Y |
1217 PM2F_RENDER_SYNC_ON_BIT_MASK);
1218 } else {
1219 pm2_WR(par, PM2R_COLOR_DDA_MODE, 0);
1220 /* clear area */
1221 pm2_WR(par, PM2R_FB_BLOCK_COLOR, bgx);
1222 pm2_WR(par, PM2R_RENDER,
1223 PM2F_RENDER_RECTANGLE |
1224 PM2F_RENDER_FASTFILL |
1225 PM2F_INCREASE_X | PM2F_INCREASE_Y);
1226 pm2_WR(par, PM2R_RASTERIZER_MODE, raster_mode);
1227 pm2_WR(par, PM2R_FB_BLOCK_COLOR, fgx);
1228 pm2_WR(par, PM2R_RENDER,
1229 PM2F_RENDER_RECTANGLE |
1230 PM2F_INCREASE_X | PM2F_INCREASE_Y |
1231 PM2F_RENDER_FASTFILL |
1232 PM2F_RENDER_SYNC_ON_BIT_MASK);
1233 }
1234
1235 while (height--) {
1236 int width = ((image->width + 7) >> 3)
1237 + info->pixmap.scan_align - 1;
1238 width >>= 2;
1239 WAIT_FIFO(par, width);
1240 while (width--) {
1241 pm2_WR(par, PM2R_BIT_MASK_PATTERN, *src);
1242 src++;
1243 }
1244 }
1245 WAIT_FIFO(par, 3);
1246 pm2_WR(par, PM2R_RASTERIZER_MODE, 0);
1247 pm2_WR(par, PM2R_COLOR_DDA_MODE, 0);
1248 pm2_WR(par, PM2R_SCISSOR_MODE, 0);
1249}
1250
1251/*
1252 * Hardware cursor support.
1253 */
1254static const u8 cursor_bits_lookup[16] = {
1255 0x00, 0x40, 0x10, 0x50, 0x04, 0x44, 0x14, 0x54,
1256 0x01, 0x41, 0x11, 0x51, 0x05, 0x45, 0x15, 0x55
1257};
1258
1259static int pm2vfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1260{
1261 struct pm2fb_par *par = info->par;
1262 u8 mode = PM2F_CURSORMODE_TYPE_X;
1263 int x = cursor->image.dx - info->var.xoffset;
1264 int y = cursor->image.dy - info->var.yoffset;
1265
1266 if (cursor->enable)
1267 mode |= PM2F_CURSORMODE_CURSOR_ENABLE;
1268
1269 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_MODE, mode);
1270
1271 if (!cursor->enable)
1272 x = 2047; /* push it outside display */
1273 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_X_LOW, x & 0xff);
1274 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_X_HIGH, (x >> 8) & 0xf);
1275 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_Y_LOW, y & 0xff);
1276 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_Y_HIGH, (y >> 8) & 0xf);
1277
1278 /*
1279 * If the cursor is not be changed this means either we want the
1280 * current cursor state (if enable is set) or we want to query what
1281 * we can do with the cursor (if enable is not set)
1282 */
1283 if (!cursor->set)
1284 return 0;
1285
1286 if (cursor->set & FB_CUR_SETHOT) {
1287 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_X_HOT,
1288 cursor->hot.x & 0x3f);
1289 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_Y_HOT,
1290 cursor->hot.y & 0x3f);
1291 }
1292
1293 if (cursor->set & FB_CUR_SETCMAP) {
1294 u32 fg_idx = cursor->image.fg_color;
1295 u32 bg_idx = cursor->image.bg_color;
1296 struct fb_cmap cmap = info->cmap;
1297
1298 /* the X11 driver says one should use these color registers */
1299 pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_CURSOR_PALETTE >> 8);
1300 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 0,
1301 cmap.red[bg_idx] >> 8 );
1302 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 1,
1303 cmap.green[bg_idx] >> 8 );
1304 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 2,
1305 cmap.blue[bg_idx] >> 8 );
1306
1307 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 3,
1308 cmap.red[fg_idx] >> 8 );
1309 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 4,
1310 cmap.green[fg_idx] >> 8 );
1311 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 5,
1312 cmap.blue[fg_idx] >> 8 );
1313 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
1314 }
1315
1316 if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) {
1317 u8 *bitmap = (u8 *)cursor->image.data;
1318 u8 *mask = (u8 *)cursor->mask;
1319 int i;
1320 int pos = PM2VI_RD_CURSOR_PATTERN;
1321
1322 for (i = 0; i < cursor->image.height; i++) {
1323 int j = (cursor->image.width + 7) >> 3;
1324 int k = 8 - j;
1325
1326 pm2_WR(par, PM2VR_RD_INDEX_HIGH, pos >> 8);
1327
1328 for (; j > 0; j--) {
1329 u8 data = *bitmap ^ *mask;
1330
1331 if (cursor->rop == ROP_COPY)
1332 data = *mask & *bitmap;
1333 /* Upper 4 bits of bitmap data */
1334 pm2v_RDAC_WR(par, pos++,
1335 cursor_bits_lookup[data >> 4] |
1336 (cursor_bits_lookup[*mask >> 4] << 1));
1337 /* Lower 4 bits of bitmap */
1338 pm2v_RDAC_WR(par, pos++,
1339 cursor_bits_lookup[data & 0xf] |
1340 (cursor_bits_lookup[*mask & 0xf] << 1));
1341 bitmap++;
1342 mask++;
1343 }
1344 for (; k > 0; k--) {
1345 pm2v_RDAC_WR(par, pos++, 0);
1346 pm2v_RDAC_WR(par, pos++, 0);
1347 }
1348 }
1349
1350 while (pos < (1024 + PM2VI_RD_CURSOR_PATTERN)) {
1351 pm2_WR(par, PM2VR_RD_INDEX_HIGH, pos >> 8);
1352 pm2v_RDAC_WR(par, pos++, 0);
1353 }
1354
1355 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
1356 }
1357 return 0;
1358}
1359
1360static int pm2fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1361{
1362 struct pm2fb_par *par = info->par;
1363 u8 mode;
1364
1365 if (!hwcursor)
1366 return -EINVAL; /* just to force soft_cursor() call */
1367
1368 /* Too large of a cursor or wrong bpp :-( */
1369 if (cursor->image.width > 64 ||
1370 cursor->image.height > 64 ||
1371 cursor->image.depth > 1)
1372 return -EINVAL;
1373
1374 if (par->type == PM2_TYPE_PERMEDIA2V)
1375 return pm2vfb_cursor(info, cursor);
1376
1377 mode = 0x40;
1378 if (cursor->enable)
1379 mode = 0x43;
1380
1381 pm2_RDAC_WR(par, PM2I_RD_CURSOR_CONTROL, mode);
1382
1383 /*
1384 * If the cursor is not be changed this means either we want the
1385 * current cursor state (if enable is set) or we want to query what
1386 * we can do with the cursor (if enable is not set)
1387 */
1388 if (!cursor->set)
1389 return 0;
1390
1391 if (cursor->set & FB_CUR_SETPOS) {
1392 int x = cursor->image.dx - info->var.xoffset + 63;
1393 int y = cursor->image.dy - info->var.yoffset + 63;
1394
1395 WAIT_FIFO(par, 4);
1396 pm2_WR(par, PM2R_RD_CURSOR_X_LSB, x & 0xff);
1397 pm2_WR(par, PM2R_RD_CURSOR_X_MSB, (x >> 8) & 0x7);
1398 pm2_WR(par, PM2R_RD_CURSOR_Y_LSB, y & 0xff);
1399 pm2_WR(par, PM2R_RD_CURSOR_Y_MSB, (y >> 8) & 0x7);
1400 }
1401
1402 if (cursor->set & FB_CUR_SETCMAP) {
1403 u32 fg_idx = cursor->image.fg_color;
1404 u32 bg_idx = cursor->image.bg_color;
1405
1406 WAIT_FIFO(par, 7);
1407 pm2_WR(par, PM2R_RD_CURSOR_COLOR_ADDRESS, 1);
1408 pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA,
1409 info->cmap.red[bg_idx] >> 8);
1410 pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA,
1411 info->cmap.green[bg_idx] >> 8);
1412 pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA,
1413 info->cmap.blue[bg_idx] >> 8);
1414
1415 pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA,
1416 info->cmap.red[fg_idx] >> 8);
1417 pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA,
1418 info->cmap.green[fg_idx] >> 8);
1419 pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA,
1420 info->cmap.blue[fg_idx] >> 8);
1421 }
1422
1423 if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) {
1424 u8 *bitmap = (u8 *)cursor->image.data;
1425 u8 *mask = (u8 *)cursor->mask;
1426 int i;
1427
1428 WAIT_FIFO(par, 1);
1429 pm2_WR(par, PM2R_RD_PALETTE_WRITE_ADDRESS, 0);
1430
1431 for (i = 0; i < cursor->image.height; i++) {
1432 int j = (cursor->image.width + 7) >> 3;
1433 int k = 8 - j;
1434
1435 WAIT_FIFO(par, 8);
1436 for (; j > 0; j--) {
1437 u8 data = *bitmap ^ *mask;
1438
1439 if (cursor->rop == ROP_COPY)
1440 data = *mask & *bitmap;
1441 /* bitmap data */
1442 pm2_WR(par, PM2R_RD_CURSOR_DATA, data);
1443 bitmap++;
1444 mask++;
1445 }
1446 for (; k > 0; k--)
1447 pm2_WR(par, PM2R_RD_CURSOR_DATA, 0);
1448 }
1449 for (; i < 64; i++) {
1450 int j = 8;
1451 WAIT_FIFO(par, 8);
1452 while (j-- > 0)
1453 pm2_WR(par, PM2R_RD_CURSOR_DATA, 0);
1454 }
1455
1456 mask = (u8 *)cursor->mask;
1457 for (i = 0; i < cursor->image.height; i++) {
1458 int j = (cursor->image.width + 7) >> 3;
1459 int k = 8 - j;
1460
1461 WAIT_FIFO(par, 8);
1462 for (; j > 0; j--) {
1463 /* mask */
1464 pm2_WR(par, PM2R_RD_CURSOR_DATA, *mask);
1465 mask++;
1466 }
1467 for (; k > 0; k--)
1468 pm2_WR(par, PM2R_RD_CURSOR_DATA, 0);
1469 }
1470 for (; i < 64; i++) {
1471 int j = 8;
1472 WAIT_FIFO(par, 8);
1473 while (j-- > 0)
1474 pm2_WR(par, PM2R_RD_CURSOR_DATA, 0);
1475 }
1476 }
1477 return 0;
1478}
1479
1480/* ------------ Hardware Independent Functions ------------ */
1481
1482/*
1483 * Frame buffer operations
1484 */
1485
1486static struct fb_ops pm2fb_ops = {
1487 .owner = THIS_MODULE,
1488 .fb_check_var = pm2fb_check_var,
1489 .fb_set_par = pm2fb_set_par,
1490 .fb_setcolreg = pm2fb_setcolreg,
1491 .fb_blank = pm2fb_blank,
1492 .fb_pan_display = pm2fb_pan_display,
1493 .fb_fillrect = pm2fb_fillrect,
1494 .fb_copyarea = pm2fb_copyarea,
1495 .fb_imageblit = pm2fb_imageblit,
1496 .fb_sync = pm2fb_sync,
1497 .fb_cursor = pm2fb_cursor,
1498};
1499
1500/*
1501 * PCI stuff
1502 */
1503
1504
1505/**
1506 * Device initialisation
1507 *
1508 * Initialise and allocate resource for PCI device.
1509 *
1510 * @param pdev PCI device.
1511 * @param id PCI device ID.
1512 */
1513static int pm2fb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1514{
1515 struct pm2fb_par *default_par;
1516 struct fb_info *info;
1517 int err;
1518 int retval = -ENXIO;
1519
1520 err = pci_enable_device(pdev);
1521 if (err) {
1522 printk(KERN_WARNING "pm2fb: Can't enable pdev: %d\n", err);
1523 return err;
1524 }
1525
1526 info = framebuffer_alloc(sizeof(struct pm2fb_par), &pdev->dev);
1527 if (!info)
1528 return -ENOMEM;
1529 default_par = info->par;
1530
1531 switch (pdev->device) {
1532 case PCI_DEVICE_ID_TI_TVP4020:
1533 strcpy(pm2fb_fix.id, "TVP4020");
1534 default_par->type = PM2_TYPE_PERMEDIA2;
1535 break;
1536 case PCI_DEVICE_ID_3DLABS_PERMEDIA2:
1537 strcpy(pm2fb_fix.id, "Permedia2");
1538 default_par->type = PM2_TYPE_PERMEDIA2;
1539 break;
1540 case PCI_DEVICE_ID_3DLABS_PERMEDIA2V:
1541 strcpy(pm2fb_fix.id, "Permedia2v");
1542 default_par->type = PM2_TYPE_PERMEDIA2V;
1543 break;
1544 }
1545
1546 pm2fb_fix.mmio_start = pci_resource_start(pdev, 0);
1547 pm2fb_fix.mmio_len = PM2_REGS_SIZE;
1548
1549#if defined(__BIG_ENDIAN)
1550 /*
1551 * PM2 has a 64k register file, mapped twice in 128k. Lower
1552 * map is little-endian, upper map is big-endian.
1553 */
1554 pm2fb_fix.mmio_start += PM2_REGS_SIZE;
1555 DPRINTK("Adjusting register base for big-endian.\n");
1556#endif
1557 DPRINTK("Register base at 0x%lx\n", pm2fb_fix.mmio_start);
1558
1559 /* Registers - request region and map it. */
1560 if (!request_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len,
1561 "pm2fb regbase")) {
1562 printk(KERN_WARNING "pm2fb: Can't reserve regbase.\n");
1563 goto err_exit_neither;
1564 }
1565 default_par->v_regs =
1566 ioremap_nocache(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1567 if (!default_par->v_regs) {
1568 printk(KERN_WARNING "pm2fb: Can't remap %s register area.\n",
1569 pm2fb_fix.id);
1570 release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1571 goto err_exit_neither;
1572 }
1573
1574 /* Stash away memory register info for use when we reset the board */
1575 default_par->mem_control = pm2_RD(default_par, PM2R_MEM_CONTROL);
1576 default_par->boot_address = pm2_RD(default_par, PM2R_BOOT_ADDRESS);
1577 default_par->mem_config = pm2_RD(default_par, PM2R_MEM_CONFIG);
1578 DPRINTK("MemControl 0x%x BootAddress 0x%x MemConfig 0x%x\n",
1579 default_par->mem_control, default_par->boot_address,
1580 default_par->mem_config);
1581
1582 if (default_par->mem_control == 0 &&
1583 default_par->boot_address == 0x31 &&
1584 default_par->mem_config == 0x259fffff) {
1585 default_par->memclock = CVPPC_MEMCLOCK;
1586 default_par->mem_control = 0;
1587 default_par->boot_address = 0x20;
1588 default_par->mem_config = 0xe6002021;
1589 if (pdev->subsystem_vendor == 0x1048 &&
1590 pdev->subsystem_device == 0x0a31) {
1591 DPRINTK("subsystem_vendor: %04x, "
1592 "subsystem_device: %04x\n",
1593 pdev->subsystem_vendor, pdev->subsystem_device);
1594 DPRINTK("We have not been initialized by VGA BIOS and "
1595 "are running on an Elsa Winner 2000 Office\n");
1596 DPRINTK("Initializing card timings manually...\n");
1597 default_par->memclock = 100000;
1598 }
1599 if (pdev->subsystem_vendor == 0x3d3d &&
1600 pdev->subsystem_device == 0x0100) {
1601 DPRINTK("subsystem_vendor: %04x, "
1602 "subsystem_device: %04x\n",
1603 pdev->subsystem_vendor, pdev->subsystem_device);
1604 DPRINTK("We have not been initialized by VGA BIOS and "
1605 "are running on an 3dlabs reference board\n");
1606 DPRINTK("Initializing card timings manually...\n");
1607 default_par->memclock = 74894;
1608 }
1609 }
1610
1611 /* Now work out how big lfb is going to be. */
1612 switch (default_par->mem_config & PM2F_MEM_CONFIG_RAM_MASK) {
1613 case PM2F_MEM_BANKS_1:
1614 pm2fb_fix.smem_len = 0x200000;
1615 break;
1616 case PM2F_MEM_BANKS_2:
1617 pm2fb_fix.smem_len = 0x400000;
1618 break;
1619 case PM2F_MEM_BANKS_3:
1620 pm2fb_fix.smem_len = 0x600000;
1621 break;
1622 case PM2F_MEM_BANKS_4:
1623 pm2fb_fix.smem_len = 0x800000;
1624 break;
1625 }
1626 pm2fb_fix.smem_start = pci_resource_start(pdev, 1);
1627
1628 /* Linear frame buffer - request region and map it. */
1629 if (!request_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len,
1630 "pm2fb smem")) {
1631 printk(KERN_WARNING "pm2fb: Can't reserve smem.\n");
1632 goto err_exit_mmio;
1633 }
1634 info->screen_base =
1635 ioremap_wc(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1636 if (!info->screen_base) {
1637 printk(KERN_WARNING "pm2fb: Can't ioremap smem area.\n");
1638 release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1639 goto err_exit_mmio;
1640 }
1641
1642 if (!nomtrr)
1643 default_par->wc_cookie = arch_phys_wc_add(pm2fb_fix.smem_start,
1644 pm2fb_fix.smem_len);
1645
1646 info->fbops = &pm2fb_ops;
1647 info->fix = pm2fb_fix;
1648 info->pseudo_palette = default_par->palette;
1649 info->flags = FBINFO_DEFAULT |
1650 FBINFO_HWACCEL_YPAN |
1651 FBINFO_HWACCEL_COPYAREA |
1652 FBINFO_HWACCEL_IMAGEBLIT |
1653 FBINFO_HWACCEL_FILLRECT;
1654
1655 info->pixmap.addr = kmalloc(PM2_PIXMAP_SIZE, GFP_KERNEL);
1656 if (!info->pixmap.addr) {
1657 retval = -ENOMEM;
1658 goto err_exit_pixmap;
1659 }
1660 info->pixmap.size = PM2_PIXMAP_SIZE;
1661 info->pixmap.buf_align = 4;
1662 info->pixmap.scan_align = 4;
1663 info->pixmap.access_align = 32;
1664 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1665
1666 if (noaccel) {
1667 printk(KERN_DEBUG "disabling acceleration\n");
1668 info->flags |= FBINFO_HWACCEL_DISABLED;
1669 info->pixmap.scan_align = 1;
1670 }
1671
1672 if (!mode_option)
1673 mode_option = "640x480@60";
1674
1675 err = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
1676 if (!err || err == 4)
1677 info->var = pm2fb_var;
1678
1679 retval = fb_alloc_cmap(&info->cmap, 256, 0);
1680 if (retval < 0)
1681 goto err_exit_both;
1682
1683 retval = register_framebuffer(info);
1684 if (retval < 0)
1685 goto err_exit_all;
1686
1687 fb_info(info, "%s frame buffer device, memory = %dK\n",
1688 info->fix.id, pm2fb_fix.smem_len / 1024);
1689
1690 /*
1691 * Our driver data
1692 */
1693 pci_set_drvdata(pdev, info);
1694
1695 return 0;
1696
1697 err_exit_all:
1698 fb_dealloc_cmap(&info->cmap);
1699 err_exit_both:
1700 kfree(info->pixmap.addr);
1701 err_exit_pixmap:
1702 iounmap(info->screen_base);
1703 release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1704 err_exit_mmio:
1705 iounmap(default_par->v_regs);
1706 release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1707 err_exit_neither:
1708 framebuffer_release(info);
1709 return retval;
1710}
1711
1712/**
1713 * Device removal.
1714 *
1715 * Release all device resources.
1716 *
1717 * @param pdev PCI device to clean up.
1718 */
1719static void pm2fb_remove(struct pci_dev *pdev)
1720{
1721 struct fb_info *info = pci_get_drvdata(pdev);
1722 struct fb_fix_screeninfo *fix = &info->fix;
1723 struct pm2fb_par *par = info->par;
1724
1725 unregister_framebuffer(info);
1726 arch_phys_wc_del(par->wc_cookie);
1727 iounmap(info->screen_base);
1728 release_mem_region(fix->smem_start, fix->smem_len);
1729 iounmap(par->v_regs);
1730 release_mem_region(fix->mmio_start, fix->mmio_len);
1731
1732 fb_dealloc_cmap(&info->cmap);
1733 kfree(info->pixmap.addr);
1734 framebuffer_release(info);
1735}
1736
1737static const struct pci_device_id pm2fb_id_table[] = {
1738 { PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TVP4020,
1739 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1740 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2,
1741 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1742 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V,
1743 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1744 { 0, }
1745};
1746
1747static struct pci_driver pm2fb_driver = {
1748 .name = "pm2fb",
1749 .id_table = pm2fb_id_table,
1750 .probe = pm2fb_probe,
1751 .remove = pm2fb_remove,
1752};
1753
1754MODULE_DEVICE_TABLE(pci, pm2fb_id_table);
1755
1756
1757#ifndef MODULE
1758/**
1759 * Parse user specified options.
1760 *
1761 * This is, comma-separated options following `video=pm2fb:'.
1762 */
1763static int __init pm2fb_setup(char *options)
1764{
1765 char *this_opt;
1766
1767 if (!options || !*options)
1768 return 0;
1769
1770 while ((this_opt = strsep(&options, ",")) != NULL) {
1771 if (!*this_opt)
1772 continue;
1773 if (!strcmp(this_opt, "lowhsync"))
1774 lowhsync = 1;
1775 else if (!strcmp(this_opt, "lowvsync"))
1776 lowvsync = 1;
1777 else if (!strncmp(this_opt, "hwcursor=", 9))
1778 hwcursor = simple_strtoul(this_opt + 9, NULL, 0);
1779 else if (!strncmp(this_opt, "nomtrr", 6))
1780 nomtrr = 1;
1781 else if (!strncmp(this_opt, "noaccel", 7))
1782 noaccel = 1;
1783 else
1784 mode_option = this_opt;
1785 }
1786 return 0;
1787}
1788#endif
1789
1790
1791static int __init pm2fb_init(void)
1792{
1793#ifndef MODULE
1794 char *option = NULL;
1795
1796 if (fb_get_options("pm2fb", &option))
1797 return -ENODEV;
1798 pm2fb_setup(option);
1799#endif
1800
1801 return pci_register_driver(&pm2fb_driver);
1802}
1803
1804module_init(pm2fb_init);
1805
1806#ifdef MODULE
1807/*
1808 * Cleanup
1809 */
1810
1811static void __exit pm2fb_exit(void)
1812{
1813 pci_unregister_driver(&pm2fb_driver);
1814}
1815#endif
1816
1817#ifdef MODULE
1818module_exit(pm2fb_exit);
1819
1820module_param(mode_option, charp, 0);
1821MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
1822module_param_named(mode, mode_option, charp, 0);
1823MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)");
1824module_param(lowhsync, bool, 0);
1825MODULE_PARM_DESC(lowhsync, "Force horizontal sync low regardless of mode");
1826module_param(lowvsync, bool, 0);
1827MODULE_PARM_DESC(lowvsync, "Force vertical sync low regardless of mode");
1828module_param(noaccel, bool, 0);
1829MODULE_PARM_DESC(noaccel, "Disable acceleration");
1830module_param(hwcursor, int, 0644);
1831MODULE_PARM_DESC(hwcursor, "Enable hardware cursor "
1832 "(1=enable, 0=disable, default=1)");
1833module_param(nomtrr, bool, 0);
1834MODULE_PARM_DESC(nomtrr, "Disable MTRR support (0 or 1=disabled) (default=0)");
1835
1836MODULE_AUTHOR("Jim Hague <jim.hague@acm.org>");
1837MODULE_DESCRIPTION("Permedia2 framebuffer device driver");
1838MODULE_LICENSE("GPL");
1839#endif
1840