1/*
2 * Copyright (c) 2004 Evgeniy Polyakov <zbr@ioremap.net>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <asm/io.h>
16
17#include <linux/delay.h>
18#include <linux/moduleparam.h>
19#include <linux/module.h>
20
21#include "w1_internal.h"
22
23static int w1_delay_parm = 1;
24module_param_named(delay_coef, w1_delay_parm, int, 0);
25
26static int w1_disable_irqs = 0;
27module_param_named(disable_irqs, w1_disable_irqs, int, 0);
28
29static u8 w1_crc8_table[] = {
30 0, 94, 188, 226, 97, 63, 221, 131, 194, 156, 126, 32, 163, 253, 31, 65,
31 157, 195, 33, 127, 252, 162, 64, 30, 95, 1, 227, 189, 62, 96, 130, 220,
32 35, 125, 159, 193, 66, 28, 254, 160, 225, 191, 93, 3, 128, 222, 60, 98,
33 190, 224, 2, 92, 223, 129, 99, 61, 124, 34, 192, 158, 29, 67, 161, 255,
34 70, 24, 250, 164, 39, 121, 155, 197, 132, 218, 56, 102, 229, 187, 89, 7,
35 219, 133, 103, 57, 186, 228, 6, 88, 25, 71, 165, 251, 120, 38, 196, 154,
36 101, 59, 217, 135, 4, 90, 184, 230, 167, 249, 27, 69, 198, 152, 122, 36,
37 248, 166, 68, 26, 153, 199, 37, 123, 58, 100, 134, 216, 91, 5, 231, 185,
38 140, 210, 48, 110, 237, 179, 81, 15, 78, 16, 242, 172, 47, 113, 147, 205,
39 17, 79, 173, 243, 112, 46, 204, 146, 211, 141, 111, 49, 178, 236, 14, 80,
40 175, 241, 19, 77, 206, 144, 114, 44, 109, 51, 209, 143, 12, 82, 176, 238,
41 50, 108, 142, 208, 83, 13, 239, 177, 240, 174, 76, 18, 145, 207, 45, 115,
42 202, 148, 118, 40, 171, 245, 23, 73, 8, 86, 180, 234, 105, 55, 213, 139,
43 87, 9, 235, 181, 54, 104, 138, 212, 149, 203, 41, 119, 244, 170, 72, 22,
44 233, 183, 85, 11, 136, 214, 52, 106, 43, 117, 151, 201, 74, 20, 246, 168,
45 116, 42, 200, 150, 21, 75, 169, 247, 182, 232, 10, 84, 215, 137, 107, 53
46};
47
48static void w1_delay(unsigned long tm)
49{
50 udelay(tm * w1_delay_parm);
51}
52
53static void w1_write_bit(struct w1_master *dev, int bit);
54static u8 w1_read_bit(struct w1_master *dev);
55
56/**
57 * w1_touch_bit() - Generates a write-0 or write-1 cycle and samples the level.
58 * @dev: the master device
59 * @bit: 0 - write a 0, 1 - write a 0 read the level
60 */
61u8 w1_touch_bit(struct w1_master *dev, int bit)
62{
63 if (dev->bus_master->touch_bit)
64 return dev->bus_master->touch_bit(dev->bus_master->data, bit);
65 else if (bit)
66 return w1_read_bit(dev);
67 else {
68 w1_write_bit(dev, 0);
69 return 0;
70 }
71}
72EXPORT_SYMBOL_GPL(w1_touch_bit);
73
74/**
75 * w1_write_bit() - Generates a write-0 or write-1 cycle.
76 * @dev: the master device
77 * @bit: bit to write
78 *
79 * Only call if dev->bus_master->touch_bit is NULL
80 */
81static void w1_write_bit(struct w1_master *dev, int bit)
82{
83 unsigned long flags = 0;
84
85 if(w1_disable_irqs) local_irq_save(flags);
86
87 if (bit) {
88 dev->bus_master->write_bit(dev->bus_master->data, 0);
89 w1_delay(6);
90 dev->bus_master->write_bit(dev->bus_master->data, 1);
91 w1_delay(64);
92 } else {
93 dev->bus_master->write_bit(dev->bus_master->data, 0);
94 w1_delay(60);
95 dev->bus_master->write_bit(dev->bus_master->data, 1);
96 w1_delay(10);
97 }
98
99 if(w1_disable_irqs) local_irq_restore(flags);
100}
101
102/**
103 * w1_pre_write() - pre-write operations
104 * @dev: the master device
105 *
106 * Pre-write operation, currently only supporting strong pullups.
107 * Program the hardware for a strong pullup, if one has been requested and
108 * the hardware supports it.
109 */
110static void w1_pre_write(struct w1_master *dev)
111{
112 if (dev->pullup_duration &&
113 dev->enable_pullup && dev->bus_master->set_pullup) {
114 dev->bus_master->set_pullup(dev->bus_master->data,
115 dev->pullup_duration);
116 }
117}
118
119/**
120 * w1_post_write() - post-write options
121 * @dev: the master device
122 *
123 * Post-write operation, currently only supporting strong pullups.
124 * If a strong pullup was requested, clear it if the hardware supports
125 * them, or execute the delay otherwise, in either case clear the request.
126 */
127static void w1_post_write(struct w1_master *dev)
128{
129 if (dev->pullup_duration) {
130 if (dev->enable_pullup && dev->bus_master->set_pullup)
131 dev->bus_master->set_pullup(dev->bus_master->data, 0);
132 else
133 msleep(dev->pullup_duration);
134 dev->pullup_duration = 0;
135 }
136}
137
138/**
139 * w1_write_8() - Writes 8 bits.
140 * @dev: the master device
141 * @byte: the byte to write
142 */
143void w1_write_8(struct w1_master *dev, u8 byte)
144{
145 int i;
146
147 if (dev->bus_master->write_byte) {
148 w1_pre_write(dev);
149 dev->bus_master->write_byte(dev->bus_master->data, byte);
150 }
151 else
152 for (i = 0; i < 8; ++i) {
153 if (i == 7)
154 w1_pre_write(dev);
155 w1_touch_bit(dev, (byte >> i) & 0x1);
156 }
157 w1_post_write(dev);
158}
159EXPORT_SYMBOL_GPL(w1_write_8);
160
161
162/**
163 * w1_read_bit() - Generates a write-1 cycle and samples the level.
164 * @dev: the master device
165 *
166 * Only call if dev->bus_master->touch_bit is NULL
167 */
168static u8 w1_read_bit(struct w1_master *dev)
169{
170 int result;
171 unsigned long flags = 0;
172
173 /* sample timing is critical here */
174 local_irq_save(flags);
175 dev->bus_master->write_bit(dev->bus_master->data, 0);
176 w1_delay(6);
177 dev->bus_master->write_bit(dev->bus_master->data, 1);
178 w1_delay(9);
179
180 result = dev->bus_master->read_bit(dev->bus_master->data);
181 local_irq_restore(flags);
182
183 w1_delay(55);
184
185 return result & 0x1;
186}
187
188/**
189 * w1_triplet() - * Does a triplet - used for searching ROM addresses.
190 * @dev: the master device
191 * @bdir: the bit to write if both id_bit and comp_bit are 0
192 *
193 * Return bits:
194 * bit 0 = id_bit
195 * bit 1 = comp_bit
196 * bit 2 = dir_taken
197 *
198 * If both bits 0 & 1 are set, the search should be restarted.
199 *
200 * Return: bit fields - see above
201 */
202u8 w1_triplet(struct w1_master *dev, int bdir)
203{
204 if (dev->bus_master->triplet)
205 return dev->bus_master->triplet(dev->bus_master->data, bdir);
206 else {
207 u8 id_bit = w1_touch_bit(dev, 1);
208 u8 comp_bit = w1_touch_bit(dev, 1);
209 u8 retval;
210
211 if (id_bit && comp_bit)
212 return 0x03; /* error */
213
214 if (!id_bit && !comp_bit) {
215 /* Both bits are valid, take the direction given */
216 retval = bdir ? 0x04 : 0;
217 } else {
218 /* Only one bit is valid, take that direction */
219 bdir = id_bit;
220 retval = id_bit ? 0x05 : 0x02;
221 }
222
223 if (dev->bus_master->touch_bit)
224 w1_touch_bit(dev, bdir);
225 else
226 w1_write_bit(dev, bdir);
227 return retval;
228 }
229}
230EXPORT_SYMBOL_GPL(w1_triplet);
231
232/**
233 * w1_read_8() - Reads 8 bits.
234 * @dev: the master device
235 *
236 * Return: the byte read
237 */
238u8 w1_read_8(struct w1_master *dev)
239{
240 int i;
241 u8 res = 0;
242
243 if (dev->bus_master->read_byte)
244 res = dev->bus_master->read_byte(dev->bus_master->data);
245 else
246 for (i = 0; i < 8; ++i)
247 res |= (w1_touch_bit(dev,1) << i);
248
249 return res;
250}
251EXPORT_SYMBOL_GPL(w1_read_8);
252
253/**
254 * w1_write_block() - Writes a series of bytes.
255 * @dev: the master device
256 * @buf: pointer to the data to write
257 * @len: the number of bytes to write
258 */
259void w1_write_block(struct w1_master *dev, const u8 *buf, int len)
260{
261 int i;
262
263 if (dev->bus_master->write_block) {
264 w1_pre_write(dev);
265 dev->bus_master->write_block(dev->bus_master->data, buf, len);
266 }
267 else
268 for (i = 0; i < len; ++i)
269 w1_write_8(dev, buf[i]); /* calls w1_pre_write */
270 w1_post_write(dev);
271}
272EXPORT_SYMBOL_GPL(w1_write_block);
273
274/**
275 * w1_touch_block() - Touches a series of bytes.
276 * @dev: the master device
277 * @buf: pointer to the data to write
278 * @len: the number of bytes to write
279 */
280void w1_touch_block(struct w1_master *dev, u8 *buf, int len)
281{
282 int i, j;
283 u8 tmp;
284
285 for (i = 0; i < len; ++i) {
286 tmp = 0;
287 for (j = 0; j < 8; ++j) {
288 if (j == 7)
289 w1_pre_write(dev);
290 tmp |= w1_touch_bit(dev, (buf[i] >> j) & 0x1) << j;
291 }
292
293 buf[i] = tmp;
294 }
295}
296EXPORT_SYMBOL_GPL(w1_touch_block);
297
298/**
299 * w1_read_block() - Reads a series of bytes.
300 * @dev: the master device
301 * @buf: pointer to the buffer to fill
302 * @len: the number of bytes to read
303 * Return: the number of bytes read
304 */
305u8 w1_read_block(struct w1_master *dev, u8 *buf, int len)
306{
307 int i;
308 u8 ret;
309
310 if (dev->bus_master->read_block)
311 ret = dev->bus_master->read_block(dev->bus_master->data, buf, len);
312 else {
313 for (i = 0; i < len; ++i)
314 buf[i] = w1_read_8(dev);
315 ret = len;
316 }
317
318 return ret;
319}
320EXPORT_SYMBOL_GPL(w1_read_block);
321
322/**
323 * w1_reset_bus() - Issues a reset bus sequence.
324 * @dev: the master device
325 * Return: 0=Device present, 1=No device present or error
326 */
327int w1_reset_bus(struct w1_master *dev)
328{
329 int result;
330 unsigned long flags = 0;
331
332 if(w1_disable_irqs) local_irq_save(flags);
333
334 if (dev->bus_master->reset_bus)
335 result = dev->bus_master->reset_bus(dev->bus_master->data) & 0x1;
336 else {
337 dev->bus_master->write_bit(dev->bus_master->data, 0);
338 /* minimum 480, max ? us
339 * be nice and sleep, except 18b20 spec lists 960us maximum,
340 * so until we can sleep with microsecond accuracy, spin.
341 * Feel free to come up with some other way to give up the
342 * cpu for such a short amount of time AND get it back in
343 * the maximum amount of time.
344 */
345 w1_delay(500);
346 dev->bus_master->write_bit(dev->bus_master->data, 1);
347 w1_delay(70);
348
349 result = dev->bus_master->read_bit(dev->bus_master->data) & 0x1;
350 /* minimum 70 (above) + 430 = 500 us
351 * There aren't any timing requirements between a reset and
352 * the following transactions. Sleeping is safe here.
353 */
354 /* w1_delay(430); min required time */
355 msleep(1);
356 }
357
358 if(w1_disable_irqs) local_irq_restore(flags);
359
360 return result;
361}
362EXPORT_SYMBOL_GPL(w1_reset_bus);
363
364u8 w1_calc_crc8(u8 * data, int len)
365{
366 u8 crc = 0;
367
368 while (len--)
369 crc = w1_crc8_table[crc ^ *data++];
370
371 return crc;
372}
373EXPORT_SYMBOL_GPL(w1_calc_crc8);
374
375void w1_search_devices(struct w1_master *dev, u8 search_type, w1_slave_found_callback cb)
376{
377 dev->attempts++;
378 if (dev->bus_master->search)
379 dev->bus_master->search(dev->bus_master->data, dev,
380 search_type, cb);
381 else
382 w1_search(dev, search_type, cb);
383}
384
385/**
386 * w1_reset_select_slave() - reset and select a slave
387 * @sl: the slave to select
388 *
389 * Resets the bus and then selects the slave by sending either a skip rom
390 * or a rom match. A skip rom is issued if there is only one device
391 * registered on the bus.
392 * The w1 master lock must be held.
393 *
394 * Return: 0=success, anything else=error
395 */
396int w1_reset_select_slave(struct w1_slave *sl)
397{
398 if (w1_reset_bus(sl->master))
399 return -1;
400
401 if (sl->master->slave_count == 1)
402 w1_write_8(sl->master, W1_SKIP_ROM);
403 else {
404 u8 match[9] = {W1_MATCH_ROM, };
405 u64 rn = le64_to_cpu(*((u64*)&sl->reg_num));
406
407 memcpy(&match[1], &rn, 8);
408 w1_write_block(sl->master, match, 9);
409 }
410 return 0;
411}
412EXPORT_SYMBOL_GPL(w1_reset_select_slave);
413
414/**
415 * w1_reset_resume_command() - resume instead of another match ROM
416 * @dev: the master device
417 *
418 * When the workflow with a slave amongst many requires several
419 * successive commands a reset between each, this function is similar
420 * to doing a reset then a match ROM for the last matched ROM. The
421 * advantage being that the matched ROM step is skipped in favor of the
422 * resume command. The slave must support the command of course.
423 *
424 * If the bus has only one slave, traditionnaly the match ROM is skipped
425 * and a "SKIP ROM" is done for efficiency. On multi-slave busses, this
426 * doesn't work of course, but the resume command is the next best thing.
427 *
428 * The w1 master lock must be held.
429 */
430int w1_reset_resume_command(struct w1_master *dev)
431{
432 if (w1_reset_bus(dev))
433 return -1;
434
435 /* This will make only the last matched slave perform a skip ROM. */
436 w1_write_8(dev, W1_RESUME_CMD);
437 return 0;
438}
439EXPORT_SYMBOL_GPL(w1_reset_resume_command);
440
441/**
442 * w1_next_pullup() - register for a strong pullup
443 * @dev: the master device
444 * @delay: time in milliseconds
445 *
446 * Put out a strong pull-up of the specified duration after the next write
447 * operation. Not all hardware supports strong pullups. Hardware that
448 * doesn't support strong pullups will sleep for the given time after the
449 * write operation without a strong pullup. This is a one shot request for
450 * the next write, specifying zero will clear a previous request.
451 * The w1 master lock must be held.
452 *
453 * Return: 0=success, anything else=error
454 */
455void w1_next_pullup(struct w1_master *dev, int delay)
456{
457 dev->pullup_duration = delay;
458}
459EXPORT_SYMBOL_GPL(w1_next_pullup);
460