1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * drivers/char/watchdog/ixp4xx_wdt.c |
4 | * |
5 | * Watchdog driver for Intel IXP4xx network processors |
6 | * |
7 | * Author: Deepak Saxena <dsaxena@plexity.net> |
8 | * Author: Linus Walleij <linus.walleij@linaro.org> |
9 | * |
10 | * Copyright 2004 (c) MontaVista, Software, Inc. |
11 | * Based on sa1100 driver, Copyright (C) 2000 Oleg Drokin <green@crimea.edu> |
12 | */ |
13 | |
14 | #include <linux/module.h> |
15 | #include <linux/types.h> |
16 | #include <linux/kernel.h> |
17 | #include <linux/watchdog.h> |
18 | #include <linux/bits.h> |
19 | #include <linux/platform_device.h> |
20 | #include <linux/clk.h> |
21 | #include <linux/soc/ixp4xx/cpu.h> |
22 | |
23 | struct ixp4xx_wdt { |
24 | struct watchdog_device wdd; |
25 | void __iomem *base; |
26 | unsigned long rate; |
27 | }; |
28 | |
29 | /* Fallback if we do not have a clock for this */ |
30 | #define IXP4XX_TIMER_FREQ 66666000 |
31 | |
32 | /* Registers after the timer registers */ |
33 | #define IXP4XX_OSWT_OFFSET 0x14 /* Watchdog Timer */ |
34 | #define IXP4XX_OSWE_OFFSET 0x18 /* Watchdog Enable */ |
35 | #define IXP4XX_OSWK_OFFSET 0x1C /* Watchdog Key */ |
36 | #define IXP4XX_OSST_OFFSET 0x20 /* Timer Status */ |
37 | |
38 | #define IXP4XX_OSST_TIMER_WDOG_PEND 0x00000008 |
39 | #define IXP4XX_OSST_TIMER_WARM_RESET 0x00000010 |
40 | #define IXP4XX_WDT_KEY 0x0000482E |
41 | #define IXP4XX_WDT_RESET_ENABLE 0x00000001 |
42 | #define IXP4XX_WDT_IRQ_ENABLE 0x00000002 |
43 | #define IXP4XX_WDT_COUNT_ENABLE 0x00000004 |
44 | |
45 | static inline |
46 | struct ixp4xx_wdt *to_ixp4xx_wdt(struct watchdog_device *wdd) |
47 | { |
48 | return container_of(wdd, struct ixp4xx_wdt, wdd); |
49 | } |
50 | |
51 | static int ixp4xx_wdt_start(struct watchdog_device *wdd) |
52 | { |
53 | struct ixp4xx_wdt *iwdt = to_ixp4xx_wdt(wdd); |
54 | |
55 | __raw_writel(IXP4XX_WDT_KEY, addr: iwdt->base + IXP4XX_OSWK_OFFSET); |
56 | __raw_writel(val: 0, addr: iwdt->base + IXP4XX_OSWE_OFFSET); |
57 | __raw_writel(val: wdd->timeout * iwdt->rate, |
58 | addr: iwdt->base + IXP4XX_OSWT_OFFSET); |
59 | __raw_writel(IXP4XX_WDT_COUNT_ENABLE | IXP4XX_WDT_RESET_ENABLE, |
60 | addr: iwdt->base + IXP4XX_OSWE_OFFSET); |
61 | __raw_writel(val: 0, addr: iwdt->base + IXP4XX_OSWK_OFFSET); |
62 | |
63 | return 0; |
64 | } |
65 | |
66 | static int ixp4xx_wdt_stop(struct watchdog_device *wdd) |
67 | { |
68 | struct ixp4xx_wdt *iwdt = to_ixp4xx_wdt(wdd); |
69 | |
70 | __raw_writel(IXP4XX_WDT_KEY, addr: iwdt->base + IXP4XX_OSWK_OFFSET); |
71 | __raw_writel(val: 0, addr: iwdt->base + IXP4XX_OSWE_OFFSET); |
72 | __raw_writel(val: 0, addr: iwdt->base + IXP4XX_OSWK_OFFSET); |
73 | |
74 | return 0; |
75 | } |
76 | |
77 | static int ixp4xx_wdt_set_timeout(struct watchdog_device *wdd, |
78 | unsigned int timeout) |
79 | { |
80 | wdd->timeout = timeout; |
81 | if (watchdog_active(wdd)) |
82 | ixp4xx_wdt_start(wdd); |
83 | |
84 | return 0; |
85 | } |
86 | |
87 | static int ixp4xx_wdt_restart(struct watchdog_device *wdd, |
88 | unsigned long action, void *data) |
89 | { |
90 | struct ixp4xx_wdt *iwdt = to_ixp4xx_wdt(wdd); |
91 | |
92 | __raw_writel(IXP4XX_WDT_KEY, addr: iwdt->base + IXP4XX_OSWK_OFFSET); |
93 | __raw_writel(val: 0, addr: iwdt->base + IXP4XX_OSWT_OFFSET); |
94 | __raw_writel(IXP4XX_WDT_COUNT_ENABLE | IXP4XX_WDT_RESET_ENABLE, |
95 | addr: iwdt->base + IXP4XX_OSWE_OFFSET); |
96 | |
97 | return 0; |
98 | } |
99 | |
100 | static const struct watchdog_ops ixp4xx_wdt_ops = { |
101 | .start = ixp4xx_wdt_start, |
102 | .stop = ixp4xx_wdt_stop, |
103 | .set_timeout = ixp4xx_wdt_set_timeout, |
104 | .restart = ixp4xx_wdt_restart, |
105 | .owner = THIS_MODULE, |
106 | }; |
107 | |
108 | static const struct watchdog_info ixp4xx_wdt_info = { |
109 | .options = WDIOF_KEEPALIVEPING |
110 | | WDIOF_MAGICCLOSE |
111 | | WDIOF_SETTIMEOUT, |
112 | .identity = KBUILD_MODNAME, |
113 | }; |
114 | |
115 | static int ixp4xx_wdt_probe(struct platform_device *pdev) |
116 | { |
117 | struct device *dev = &pdev->dev; |
118 | struct ixp4xx_wdt *iwdt; |
119 | struct clk *clk; |
120 | int ret; |
121 | |
122 | if (!(read_cpuid_id() & 0xf) && !cpu_is_ixp46x()) { |
123 | dev_err(dev, "Rev. A0 IXP42x CPU detected - watchdog disabled\n" ); |
124 | return -ENODEV; |
125 | } |
126 | |
127 | iwdt = devm_kzalloc(dev, size: sizeof(*iwdt), GFP_KERNEL); |
128 | if (!iwdt) |
129 | return -ENOMEM; |
130 | iwdt->base = (void __iomem *)dev->platform_data; |
131 | |
132 | /* |
133 | * Retrieve rate from a fixed clock from the device tree if |
134 | * the parent has that, else use the default clock rate. |
135 | */ |
136 | clk = devm_clk_get_enabled(dev: dev->parent, NULL); |
137 | if (!IS_ERR(ptr: clk)) |
138 | iwdt->rate = clk_get_rate(clk); |
139 | |
140 | if (!iwdt->rate) |
141 | iwdt->rate = IXP4XX_TIMER_FREQ; |
142 | |
143 | iwdt->wdd.info = &ixp4xx_wdt_info; |
144 | iwdt->wdd.ops = &ixp4xx_wdt_ops; |
145 | iwdt->wdd.min_timeout = 1; |
146 | iwdt->wdd.max_timeout = U32_MAX / iwdt->rate; |
147 | iwdt->wdd.parent = dev; |
148 | /* Default to 60 seconds */ |
149 | iwdt->wdd.timeout = 60U; |
150 | watchdog_init_timeout(wdd: &iwdt->wdd, timeout_parm: 0, dev); |
151 | |
152 | if (__raw_readl(addr: iwdt->base + IXP4XX_OSST_OFFSET) & |
153 | IXP4XX_OSST_TIMER_WARM_RESET) |
154 | iwdt->wdd.bootstatus = WDIOF_CARDRESET; |
155 | |
156 | ret = devm_watchdog_register_device(dev, &iwdt->wdd); |
157 | if (ret) |
158 | return ret; |
159 | |
160 | dev_info(dev, "IXP4xx watchdog available\n" ); |
161 | |
162 | return 0; |
163 | } |
164 | |
165 | static struct platform_driver ixp4xx_wdt_driver = { |
166 | .probe = ixp4xx_wdt_probe, |
167 | .driver = { |
168 | .name = "ixp4xx-watchdog" , |
169 | }, |
170 | }; |
171 | module_platform_driver(ixp4xx_wdt_driver); |
172 | |
173 | MODULE_AUTHOR("Deepak Saxena <dsaxena@plexity.net>" ); |
174 | MODULE_DESCRIPTION("IXP4xx Network Processor Watchdog" ); |
175 | MODULE_LICENSE("GPL" ); |
176 | |