1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Mediatek Watchdog Driver
4 *
5 * Copyright (C) 2014 Matthias Brugger
6 *
7 * Matthias Brugger <matthias.bgg@gmail.com>
8 *
9 * Based on sunxi_wdt.c
10 */
11
12#include <dt-bindings/reset/mt2712-resets.h>
13#include <dt-bindings/reset/mediatek,mt6795-resets.h>
14#include <dt-bindings/reset/mt7986-resets.h>
15#include <dt-bindings/reset/mt8183-resets.h>
16#include <dt-bindings/reset/mt8186-resets.h>
17#include <dt-bindings/reset/mt8188-resets.h>
18#include <dt-bindings/reset/mt8192-resets.h>
19#include <dt-bindings/reset/mt8195-resets.h>
20#include <linux/delay.h>
21#include <linux/err.h>
22#include <linux/init.h>
23#include <linux/io.h>
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/moduleparam.h>
27#include <linux/of.h>
28#include <linux/platform_device.h>
29#include <linux/reset-controller.h>
30#include <linux/types.h>
31#include <linux/watchdog.h>
32#include <linux/interrupt.h>
33
34#define WDT_MAX_TIMEOUT 31
35#define WDT_MIN_TIMEOUT 2
36#define WDT_LENGTH_TIMEOUT(n) ((n) << 5)
37
38#define WDT_LENGTH 0x04
39#define WDT_LENGTH_KEY 0x8
40
41#define WDT_RST 0x08
42#define WDT_RST_RELOAD 0x1971
43
44#define WDT_MODE 0x00
45#define WDT_MODE_EN (1 << 0)
46#define WDT_MODE_EXT_POL_LOW (0 << 1)
47#define WDT_MODE_EXT_POL_HIGH (1 << 1)
48#define WDT_MODE_EXRST_EN (1 << 2)
49#define WDT_MODE_IRQ_EN (1 << 3)
50#define WDT_MODE_AUTO_START (1 << 4)
51#define WDT_MODE_DUAL_EN (1 << 6)
52#define WDT_MODE_CNT_SEL (1 << 8)
53#define WDT_MODE_KEY 0x22000000
54
55#define WDT_SWRST 0x14
56#define WDT_SWRST_KEY 0x1209
57
58#define WDT_SWSYSRST 0x18U
59#define WDT_SWSYS_RST_KEY 0x88000000
60
61#define DRV_NAME "mtk-wdt"
62#define DRV_VERSION "1.0"
63
64static bool nowayout = WATCHDOG_NOWAYOUT;
65static unsigned int timeout;
66
67struct mtk_wdt_dev {
68 struct watchdog_device wdt_dev;
69 void __iomem *wdt_base;
70 spinlock_t lock; /* protects WDT_SWSYSRST reg */
71 struct reset_controller_dev rcdev;
72 bool disable_wdt_extrst;
73 bool reset_by_toprgu;
74};
75
76struct mtk_wdt_data {
77 int toprgu_sw_rst_num;
78};
79
80static const struct mtk_wdt_data mt2712_data = {
81 .toprgu_sw_rst_num = MT2712_TOPRGU_SW_RST_NUM,
82};
83
84static const struct mtk_wdt_data mt6795_data = {
85 .toprgu_sw_rst_num = MT6795_TOPRGU_SW_RST_NUM,
86};
87
88static const struct mtk_wdt_data mt7986_data = {
89 .toprgu_sw_rst_num = MT7986_TOPRGU_SW_RST_NUM,
90};
91
92static const struct mtk_wdt_data mt8183_data = {
93 .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
94};
95
96static const struct mtk_wdt_data mt8186_data = {
97 .toprgu_sw_rst_num = MT8186_TOPRGU_SW_RST_NUM,
98};
99
100static const struct mtk_wdt_data mt8188_data = {
101 .toprgu_sw_rst_num = MT8188_TOPRGU_SW_RST_NUM,
102};
103
104static const struct mtk_wdt_data mt8192_data = {
105 .toprgu_sw_rst_num = MT8192_TOPRGU_SW_RST_NUM,
106};
107
108static const struct mtk_wdt_data mt8195_data = {
109 .toprgu_sw_rst_num = MT8195_TOPRGU_SW_RST_NUM,
110};
111
112static int toprgu_reset_update(struct reset_controller_dev *rcdev,
113 unsigned long id, bool assert)
114{
115 unsigned int tmp;
116 unsigned long flags;
117 struct mtk_wdt_dev *data =
118 container_of(rcdev, struct mtk_wdt_dev, rcdev);
119
120 spin_lock_irqsave(&data->lock, flags);
121
122 tmp = readl(addr: data->wdt_base + WDT_SWSYSRST);
123 if (assert)
124 tmp |= BIT(id);
125 else
126 tmp &= ~BIT(id);
127 tmp |= WDT_SWSYS_RST_KEY;
128 writel(val: tmp, addr: data->wdt_base + WDT_SWSYSRST);
129
130 spin_unlock_irqrestore(lock: &data->lock, flags);
131
132 return 0;
133}
134
135static int toprgu_reset_assert(struct reset_controller_dev *rcdev,
136 unsigned long id)
137{
138 return toprgu_reset_update(rcdev, id, assert: true);
139}
140
141static int toprgu_reset_deassert(struct reset_controller_dev *rcdev,
142 unsigned long id)
143{
144 return toprgu_reset_update(rcdev, id, assert: false);
145}
146
147static int toprgu_reset(struct reset_controller_dev *rcdev,
148 unsigned long id)
149{
150 int ret;
151
152 ret = toprgu_reset_assert(rcdev, id);
153 if (ret)
154 return ret;
155
156 return toprgu_reset_deassert(rcdev, id);
157}
158
159static const struct reset_control_ops toprgu_reset_ops = {
160 .assert = toprgu_reset_assert,
161 .deassert = toprgu_reset_deassert,
162 .reset = toprgu_reset,
163};
164
165static int toprgu_register_reset_controller(struct platform_device *pdev,
166 int rst_num)
167{
168 int ret;
169 struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev);
170
171 spin_lock_init(&mtk_wdt->lock);
172
173 mtk_wdt->rcdev.owner = THIS_MODULE;
174 mtk_wdt->rcdev.nr_resets = rst_num;
175 mtk_wdt->rcdev.ops = &toprgu_reset_ops;
176 mtk_wdt->rcdev.of_node = pdev->dev.of_node;
177 ret = devm_reset_controller_register(dev: &pdev->dev, rcdev: &mtk_wdt->rcdev);
178 if (ret != 0)
179 dev_err(&pdev->dev,
180 "couldn't register wdt reset controller: %d\n", ret);
181 return ret;
182}
183
184static int mtk_wdt_restart(struct watchdog_device *wdt_dev,
185 unsigned long action, void *data)
186{
187 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdd: wdt_dev);
188 void __iomem *wdt_base;
189
190 wdt_base = mtk_wdt->wdt_base;
191
192 while (1) {
193 writel(WDT_SWRST_KEY, addr: wdt_base + WDT_SWRST);
194 mdelay(5);
195 }
196
197 return 0;
198}
199
200static int mtk_wdt_ping(struct watchdog_device *wdt_dev)
201{
202 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdd: wdt_dev);
203 void __iomem *wdt_base = mtk_wdt->wdt_base;
204
205 iowrite32(WDT_RST_RELOAD, wdt_base + WDT_RST);
206
207 return 0;
208}
209
210static int mtk_wdt_set_timeout(struct watchdog_device *wdt_dev,
211 unsigned int timeout)
212{
213 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdd: wdt_dev);
214 void __iomem *wdt_base = mtk_wdt->wdt_base;
215 u32 reg;
216
217 wdt_dev->timeout = timeout;
218 /*
219 * In dual mode, irq will be triggered at timeout / 2
220 * the real timeout occurs at timeout
221 */
222 if (wdt_dev->pretimeout)
223 wdt_dev->pretimeout = timeout / 2;
224
225 /*
226 * One bit is the value of 512 ticks
227 * The clock has 32 KHz
228 */
229 reg = WDT_LENGTH_TIMEOUT((timeout - wdt_dev->pretimeout) << 6)
230 | WDT_LENGTH_KEY;
231 iowrite32(reg, wdt_base + WDT_LENGTH);
232
233 mtk_wdt_ping(wdt_dev);
234
235 return 0;
236}
237
238static void mtk_wdt_init(struct watchdog_device *wdt_dev)
239{
240 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdd: wdt_dev);
241 void __iomem *wdt_base;
242
243 wdt_base = mtk_wdt->wdt_base;
244
245 if (readl(addr: wdt_base + WDT_MODE) & WDT_MODE_EN) {
246 set_bit(WDOG_HW_RUNNING, addr: &wdt_dev->status);
247 mtk_wdt_set_timeout(wdt_dev, timeout: wdt_dev->timeout);
248 }
249}
250
251static int mtk_wdt_stop(struct watchdog_device *wdt_dev)
252{
253 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdd: wdt_dev);
254 void __iomem *wdt_base = mtk_wdt->wdt_base;
255 u32 reg;
256
257 reg = readl(addr: wdt_base + WDT_MODE);
258 reg &= ~WDT_MODE_EN;
259 reg |= WDT_MODE_KEY;
260 iowrite32(reg, wdt_base + WDT_MODE);
261
262 return 0;
263}
264
265static int mtk_wdt_start(struct watchdog_device *wdt_dev)
266{
267 u32 reg;
268 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdd: wdt_dev);
269 void __iomem *wdt_base = mtk_wdt->wdt_base;
270 int ret;
271
272 ret = mtk_wdt_set_timeout(wdt_dev, timeout: wdt_dev->timeout);
273 if (ret < 0)
274 return ret;
275
276 reg = ioread32(wdt_base + WDT_MODE);
277 if (wdt_dev->pretimeout)
278 reg |= (WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
279 else
280 reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
281 if (mtk_wdt->disable_wdt_extrst)
282 reg &= ~WDT_MODE_EXRST_EN;
283 if (mtk_wdt->reset_by_toprgu)
284 reg |= WDT_MODE_CNT_SEL;
285 reg |= (WDT_MODE_EN | WDT_MODE_KEY);
286 iowrite32(reg, wdt_base + WDT_MODE);
287
288 return 0;
289}
290
291static int mtk_wdt_set_pretimeout(struct watchdog_device *wdd,
292 unsigned int timeout)
293{
294 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdd);
295 void __iomem *wdt_base = mtk_wdt->wdt_base;
296 u32 reg = ioread32(wdt_base + WDT_MODE);
297
298 if (timeout && !wdd->pretimeout) {
299 wdd->pretimeout = wdd->timeout / 2;
300 reg |= (WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
301 } else if (!timeout && wdd->pretimeout) {
302 wdd->pretimeout = 0;
303 reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
304 } else {
305 return 0;
306 }
307
308 reg |= WDT_MODE_KEY;
309 iowrite32(reg, wdt_base + WDT_MODE);
310
311 return mtk_wdt_set_timeout(wdt_dev: wdd, timeout: wdd->timeout);
312}
313
314static irqreturn_t mtk_wdt_isr(int irq, void *arg)
315{
316 struct watchdog_device *wdd = arg;
317
318 watchdog_notify_pretimeout(wdd);
319
320 return IRQ_HANDLED;
321}
322
323static const struct watchdog_info mtk_wdt_info = {
324 .identity = DRV_NAME,
325 .options = WDIOF_SETTIMEOUT |
326 WDIOF_KEEPALIVEPING |
327 WDIOF_MAGICCLOSE,
328};
329
330static const struct watchdog_info mtk_wdt_pt_info = {
331 .identity = DRV_NAME,
332 .options = WDIOF_SETTIMEOUT |
333 WDIOF_PRETIMEOUT |
334 WDIOF_KEEPALIVEPING |
335 WDIOF_MAGICCLOSE,
336};
337
338static const struct watchdog_ops mtk_wdt_ops = {
339 .owner = THIS_MODULE,
340 .start = mtk_wdt_start,
341 .stop = mtk_wdt_stop,
342 .ping = mtk_wdt_ping,
343 .set_timeout = mtk_wdt_set_timeout,
344 .set_pretimeout = mtk_wdt_set_pretimeout,
345 .restart = mtk_wdt_restart,
346};
347
348static int mtk_wdt_probe(struct platform_device *pdev)
349{
350 struct device *dev = &pdev->dev;
351 struct mtk_wdt_dev *mtk_wdt;
352 const struct mtk_wdt_data *wdt_data;
353 int err, irq;
354
355 mtk_wdt = devm_kzalloc(dev, size: sizeof(*mtk_wdt), GFP_KERNEL);
356 if (!mtk_wdt)
357 return -ENOMEM;
358
359 platform_set_drvdata(pdev, data: mtk_wdt);
360
361 mtk_wdt->wdt_base = devm_platform_ioremap_resource(pdev, index: 0);
362 if (IS_ERR(ptr: mtk_wdt->wdt_base))
363 return PTR_ERR(ptr: mtk_wdt->wdt_base);
364
365 irq = platform_get_irq_optional(pdev, 0);
366 if (irq > 0) {
367 err = devm_request_irq(dev: &pdev->dev, irq, handler: mtk_wdt_isr, irqflags: 0, devname: "wdt_bark",
368 dev_id: &mtk_wdt->wdt_dev);
369 if (err)
370 return err;
371
372 mtk_wdt->wdt_dev.info = &mtk_wdt_pt_info;
373 mtk_wdt->wdt_dev.pretimeout = WDT_MAX_TIMEOUT / 2;
374 } else {
375 if (irq == -EPROBE_DEFER)
376 return -EPROBE_DEFER;
377
378 mtk_wdt->wdt_dev.info = &mtk_wdt_info;
379 }
380
381 mtk_wdt->wdt_dev.ops = &mtk_wdt_ops;
382 mtk_wdt->wdt_dev.timeout = WDT_MAX_TIMEOUT;
383 mtk_wdt->wdt_dev.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT * 1000;
384 mtk_wdt->wdt_dev.min_timeout = WDT_MIN_TIMEOUT;
385 mtk_wdt->wdt_dev.parent = dev;
386
387 watchdog_init_timeout(wdd: &mtk_wdt->wdt_dev, timeout_parm: timeout, dev);
388 watchdog_set_nowayout(wdd: &mtk_wdt->wdt_dev, nowayout);
389 watchdog_set_restart_priority(wdd: &mtk_wdt->wdt_dev, priority: 128);
390
391 watchdog_set_drvdata(wdd: &mtk_wdt->wdt_dev, data: mtk_wdt);
392
393 mtk_wdt_init(wdt_dev: &mtk_wdt->wdt_dev);
394
395 watchdog_stop_on_reboot(wdd: &mtk_wdt->wdt_dev);
396 err = devm_watchdog_register_device(dev, &mtk_wdt->wdt_dev);
397 if (unlikely(err))
398 return err;
399
400 dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n",
401 mtk_wdt->wdt_dev.timeout, nowayout);
402
403 wdt_data = of_device_get_match_data(dev);
404 if (wdt_data) {
405 err = toprgu_register_reset_controller(pdev,
406 rst_num: wdt_data->toprgu_sw_rst_num);
407 if (err)
408 return err;
409 }
410
411 mtk_wdt->disable_wdt_extrst =
412 of_property_read_bool(np: dev->of_node, propname: "mediatek,disable-extrst");
413
414 mtk_wdt->reset_by_toprgu =
415 of_property_read_bool(np: dev->of_node, propname: "mediatek,reset-by-toprgu");
416
417 return 0;
418}
419
420static int mtk_wdt_suspend(struct device *dev)
421{
422 struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev);
423
424 if (watchdog_active(wdd: &mtk_wdt->wdt_dev))
425 mtk_wdt_stop(wdt_dev: &mtk_wdt->wdt_dev);
426
427 return 0;
428}
429
430static int mtk_wdt_resume(struct device *dev)
431{
432 struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev);
433
434 if (watchdog_active(wdd: &mtk_wdt->wdt_dev)) {
435 mtk_wdt_start(wdt_dev: &mtk_wdt->wdt_dev);
436 mtk_wdt_ping(wdt_dev: &mtk_wdt->wdt_dev);
437 }
438
439 return 0;
440}
441
442static const struct of_device_id mtk_wdt_dt_ids[] = {
443 { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data },
444 { .compatible = "mediatek,mt6589-wdt" },
445 { .compatible = "mediatek,mt6795-wdt", .data = &mt6795_data },
446 { .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data },
447 { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
448 { .compatible = "mediatek,mt8186-wdt", .data = &mt8186_data },
449 { .compatible = "mediatek,mt8188-wdt", .data = &mt8188_data },
450 { .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data },
451 { .compatible = "mediatek,mt8195-wdt", .data = &mt8195_data },
452 { /* sentinel */ }
453};
454MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);
455
456static DEFINE_SIMPLE_DEV_PM_OPS(mtk_wdt_pm_ops,
457 mtk_wdt_suspend, mtk_wdt_resume);
458
459static struct platform_driver mtk_wdt_driver = {
460 .probe = mtk_wdt_probe,
461 .driver = {
462 .name = DRV_NAME,
463 .pm = pm_sleep_ptr(&mtk_wdt_pm_ops),
464 .of_match_table = mtk_wdt_dt_ids,
465 },
466};
467
468module_platform_driver(mtk_wdt_driver);
469
470module_param(timeout, uint, 0);
471MODULE_PARM_DESC(timeout, "Watchdog heartbeat in seconds");
472
473module_param(nowayout, bool, 0);
474MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
475 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
476
477MODULE_LICENSE("GPL");
478MODULE_AUTHOR("Matthias Brugger <matthias.bgg@gmail.com>");
479MODULE_DESCRIPTION("Mediatek WatchDog Timer Driver");
480MODULE_VERSION(DRV_VERSION);
481

source code of linux/drivers/watchdog/mtk_wdt.c