| 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
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| 2 | /* |
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| 3 | * nv_tco: TCO timer driver for nVidia chipsets. |
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| 4 | * |
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| 5 | * (c) Copyright 2005 Google Inc., All Rights Reserved. |
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| 6 | * |
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| 7 | * Supported Chipsets: |
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| 8 | * - MCP51/MCP55 |
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| 9 | * |
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| 10 | * (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights |
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| 11 | * Reserved. |
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| 12 | * https://www.kernelconcepts.de |
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| 13 | * |
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| 14 | * Neither kernel concepts nor Nils Faerber admit liability nor provide |
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| 15 | * warranty for any of this software. This material is provided |
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| 16 | * "AS-IS" and at no charge. |
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| 17 | * |
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| 18 | * (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de> |
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| 19 | * developed for |
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| 20 | * Jentro AG, Haar/Munich (Germany) |
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| 21 | * |
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| 22 | * TCO timer driver for NV chipsets |
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| 23 | * based on softdog.c by Alan Cox <alan@redhat.com> |
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| 24 | */ |
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| 25 | |
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| 26 | /* |
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| 27 | * Some address definitions for the TCO |
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| 28 | */ |
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| 29 | |
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| 30 | #define TCO_RLD(base) ((base) + 0x00) /* TCO Timer Reload and Current Value */ |
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| 31 | #define TCO_TMR(base) ((base) + 0x01) /* TCO Timer Initial Value */ |
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| 32 | |
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| 33 | #define TCO_STS(base) ((base) + 0x04) /* TCO Status Register */ |
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| 34 | /* |
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| 35 | * TCO Boot Status bit: set on TCO reset, reset by software or standby |
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| 36 | * power-good (survives reboots), unfortunately this bit is never |
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| 37 | * set. |
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| 38 | */ |
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| 39 | # define TCO_STS_BOOT_STS (1 << 9) |
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| 40 | /* |
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| 41 | * first and 2nd timeout status bits, these also survive a warm boot, |
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| 42 | * and they work, so we use them. |
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| 43 | */ |
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| 44 | # define TCO_STS_TCO_INT_STS (1 << 1) |
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| 45 | # define TCO_STS_TCO2TO_STS (1 << 10) |
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| 46 | # define TCO_STS_RESET (TCO_STS_BOOT_STS | TCO_STS_TCO2TO_STS | \ |
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| 47 | TCO_STS_TCO_INT_STS) |
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| 48 | |
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| 49 | #define TCO_CNT(base) ((base) + 0x08) /* TCO Control Register */ |
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| 50 | # define TCO_CNT_TCOHALT (1 << 12) |
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| 51 | |
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| 52 | #define MCP51_SMBUS_SETUP_B 0xe8 |
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| 53 | # define MCP51_SMBUS_SETUP_B_TCO_REBOOT (1 << 25) |
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| 54 | |
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| 55 | /* |
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| 56 | * The SMI_EN register is at the base io address + 0x04, |
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| 57 | * while TCOBASE is + 0x40. |
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| 58 | */ |
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| 59 | #define MCP51_SMI_EN(base) ((base) - 0x40 + 0x04) |
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| 60 | # define MCP51_SMI_EN_TCO ((1 << 4) | (1 << 5)) |
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| 61 | |
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