1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* Copyright (c) 2014, The Linux Foundation. All rights reserved. |
3 | */ |
4 | #include <linux/bits.h> |
5 | #include <linux/clk.h> |
6 | #include <linux/delay.h> |
7 | #include <linux/interrupt.h> |
8 | #include <linux/io.h> |
9 | #include <linux/kernel.h> |
10 | #include <linux/module.h> |
11 | #include <linux/of.h> |
12 | #include <linux/platform_device.h> |
13 | #include <linux/watchdog.h> |
14 | |
15 | enum wdt_reg { |
16 | WDT_RST, |
17 | WDT_EN, |
18 | WDT_STS, |
19 | WDT_BARK_TIME, |
20 | WDT_BITE_TIME, |
21 | }; |
22 | |
23 | #define QCOM_WDT_ENABLE BIT(0) |
24 | |
25 | static const u32 reg_offset_data_apcs_tmr[] = { |
26 | [WDT_RST] = 0x38, |
27 | [WDT_EN] = 0x40, |
28 | [WDT_STS] = 0x44, |
29 | [WDT_BARK_TIME] = 0x4C, |
30 | [WDT_BITE_TIME] = 0x5C, |
31 | }; |
32 | |
33 | static const u32 reg_offset_data_kpss[] = { |
34 | [WDT_RST] = 0x4, |
35 | [WDT_EN] = 0x8, |
36 | [WDT_STS] = 0xC, |
37 | [WDT_BARK_TIME] = 0x10, |
38 | [WDT_BITE_TIME] = 0x14, |
39 | }; |
40 | |
41 | struct qcom_wdt_match_data { |
42 | const u32 *offset; |
43 | bool pretimeout; |
44 | }; |
45 | |
46 | struct qcom_wdt { |
47 | struct watchdog_device wdd; |
48 | unsigned long rate; |
49 | void __iomem *base; |
50 | const u32 *layout; |
51 | }; |
52 | |
53 | static void __iomem *wdt_addr(struct qcom_wdt *wdt, enum wdt_reg reg) |
54 | { |
55 | return wdt->base + wdt->layout[reg]; |
56 | } |
57 | |
58 | static inline |
59 | struct qcom_wdt *to_qcom_wdt(struct watchdog_device *wdd) |
60 | { |
61 | return container_of(wdd, struct qcom_wdt, wdd); |
62 | } |
63 | |
64 | static irqreturn_t qcom_wdt_isr(int irq, void *arg) |
65 | { |
66 | struct watchdog_device *wdd = arg; |
67 | |
68 | watchdog_notify_pretimeout(wdd); |
69 | |
70 | return IRQ_HANDLED; |
71 | } |
72 | |
73 | static int qcom_wdt_start(struct watchdog_device *wdd) |
74 | { |
75 | struct qcom_wdt *wdt = to_qcom_wdt(wdd); |
76 | unsigned int bark = wdd->timeout - wdd->pretimeout; |
77 | |
78 | writel(val: 0, addr: wdt_addr(wdt, reg: WDT_EN)); |
79 | writel(val: 1, addr: wdt_addr(wdt, reg: WDT_RST)); |
80 | writel(val: bark * wdt->rate, addr: wdt_addr(wdt, reg: WDT_BARK_TIME)); |
81 | writel(val: wdd->timeout * wdt->rate, addr: wdt_addr(wdt, reg: WDT_BITE_TIME)); |
82 | writel(QCOM_WDT_ENABLE, addr: wdt_addr(wdt, reg: WDT_EN)); |
83 | return 0; |
84 | } |
85 | |
86 | static int qcom_wdt_stop(struct watchdog_device *wdd) |
87 | { |
88 | struct qcom_wdt *wdt = to_qcom_wdt(wdd); |
89 | |
90 | writel(val: 0, addr: wdt_addr(wdt, reg: WDT_EN)); |
91 | return 0; |
92 | } |
93 | |
94 | static int qcom_wdt_ping(struct watchdog_device *wdd) |
95 | { |
96 | struct qcom_wdt *wdt = to_qcom_wdt(wdd); |
97 | |
98 | writel(val: 1, addr: wdt_addr(wdt, reg: WDT_RST)); |
99 | return 0; |
100 | } |
101 | |
102 | static int qcom_wdt_set_timeout(struct watchdog_device *wdd, |
103 | unsigned int timeout) |
104 | { |
105 | wdd->timeout = timeout; |
106 | return qcom_wdt_start(wdd); |
107 | } |
108 | |
109 | static int qcom_wdt_set_pretimeout(struct watchdog_device *wdd, |
110 | unsigned int timeout) |
111 | { |
112 | wdd->pretimeout = timeout; |
113 | return qcom_wdt_start(wdd); |
114 | } |
115 | |
116 | static int qcom_wdt_restart(struct watchdog_device *wdd, unsigned long action, |
117 | void *data) |
118 | { |
119 | struct qcom_wdt *wdt = to_qcom_wdt(wdd); |
120 | u32 timeout; |
121 | |
122 | /* |
123 | * Trigger watchdog bite: |
124 | * Setup BITE_TIME to be 128ms, and enable WDT. |
125 | */ |
126 | timeout = 128 * wdt->rate / 1000; |
127 | |
128 | writel(val: 0, addr: wdt_addr(wdt, reg: WDT_EN)); |
129 | writel(val: 1, addr: wdt_addr(wdt, reg: WDT_RST)); |
130 | writel(val: timeout, addr: wdt_addr(wdt, reg: WDT_BARK_TIME)); |
131 | writel(val: timeout, addr: wdt_addr(wdt, reg: WDT_BITE_TIME)); |
132 | writel(QCOM_WDT_ENABLE, addr: wdt_addr(wdt, reg: WDT_EN)); |
133 | |
134 | /* |
135 | * Actually make sure the above sequence hits hardware before sleeping. |
136 | */ |
137 | wmb(); |
138 | |
139 | mdelay(150); |
140 | return 0; |
141 | } |
142 | |
143 | static int qcom_wdt_is_running(struct watchdog_device *wdd) |
144 | { |
145 | struct qcom_wdt *wdt = to_qcom_wdt(wdd); |
146 | |
147 | return (readl(addr: wdt_addr(wdt, reg: WDT_EN)) & QCOM_WDT_ENABLE); |
148 | } |
149 | |
150 | static const struct watchdog_ops qcom_wdt_ops = { |
151 | .start = qcom_wdt_start, |
152 | .stop = qcom_wdt_stop, |
153 | .ping = qcom_wdt_ping, |
154 | .set_timeout = qcom_wdt_set_timeout, |
155 | .set_pretimeout = qcom_wdt_set_pretimeout, |
156 | .restart = qcom_wdt_restart, |
157 | .owner = THIS_MODULE, |
158 | }; |
159 | |
160 | static const struct watchdog_info qcom_wdt_info = { |
161 | .options = WDIOF_KEEPALIVEPING |
162 | | WDIOF_MAGICCLOSE |
163 | | WDIOF_SETTIMEOUT |
164 | | WDIOF_CARDRESET, |
165 | .identity = KBUILD_MODNAME, |
166 | }; |
167 | |
168 | static const struct watchdog_info qcom_wdt_pt_info = { |
169 | .options = WDIOF_KEEPALIVEPING |
170 | | WDIOF_MAGICCLOSE |
171 | | WDIOF_SETTIMEOUT |
172 | | WDIOF_PRETIMEOUT |
173 | | WDIOF_CARDRESET, |
174 | .identity = KBUILD_MODNAME, |
175 | }; |
176 | |
177 | static const struct qcom_wdt_match_data match_data_apcs_tmr = { |
178 | .offset = reg_offset_data_apcs_tmr, |
179 | .pretimeout = false, |
180 | }; |
181 | |
182 | static const struct qcom_wdt_match_data match_data_kpss = { |
183 | .offset = reg_offset_data_kpss, |
184 | .pretimeout = true, |
185 | }; |
186 | |
187 | static int qcom_wdt_probe(struct platform_device *pdev) |
188 | { |
189 | struct device *dev = &pdev->dev; |
190 | struct qcom_wdt *wdt; |
191 | struct resource *res; |
192 | struct device_node *np = dev->of_node; |
193 | const struct qcom_wdt_match_data *data; |
194 | u32 percpu_offset; |
195 | int irq, ret; |
196 | struct clk *clk; |
197 | |
198 | data = of_device_get_match_data(dev); |
199 | if (!data) { |
200 | dev_err(dev, "Unsupported QCOM WDT module\n" ); |
201 | return -ENODEV; |
202 | } |
203 | |
204 | wdt = devm_kzalloc(dev, size: sizeof(*wdt), GFP_KERNEL); |
205 | if (!wdt) |
206 | return -ENOMEM; |
207 | |
208 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
209 | if (!res) |
210 | return -ENOMEM; |
211 | |
212 | /* We use CPU0's DGT for the watchdog */ |
213 | if (of_property_read_u32(np, propname: "cpu-offset" , out_value: &percpu_offset)) |
214 | percpu_offset = 0; |
215 | |
216 | res->start += percpu_offset; |
217 | res->end += percpu_offset; |
218 | |
219 | wdt->base = devm_ioremap_resource(dev, res); |
220 | if (IS_ERR(ptr: wdt->base)) |
221 | return PTR_ERR(ptr: wdt->base); |
222 | |
223 | clk = devm_clk_get_enabled(dev, NULL); |
224 | if (IS_ERR(ptr: clk)) { |
225 | dev_err(dev, "failed to get input clock\n" ); |
226 | return PTR_ERR(ptr: clk); |
227 | } |
228 | |
229 | /* |
230 | * We use the clock rate to calculate the max timeout, so ensure it's |
231 | * not zero to avoid a divide-by-zero exception. |
232 | * |
233 | * WATCHDOG_CORE assumes units of seconds, if the WDT is clocked such |
234 | * that it would bite before a second elapses it's usefulness is |
235 | * limited. Bail if this is the case. |
236 | */ |
237 | wdt->rate = clk_get_rate(clk); |
238 | if (wdt->rate == 0 || |
239 | wdt->rate > 0x10000000U) { |
240 | dev_err(dev, "invalid clock rate\n" ); |
241 | return -EINVAL; |
242 | } |
243 | |
244 | /* check if there is pretimeout support */ |
245 | irq = platform_get_irq_optional(pdev, 0); |
246 | if (data->pretimeout && irq > 0) { |
247 | ret = devm_request_irq(dev, irq, handler: qcom_wdt_isr, irqflags: 0, |
248 | devname: "wdt_bark" , dev_id: &wdt->wdd); |
249 | if (ret) |
250 | return ret; |
251 | |
252 | wdt->wdd.info = &qcom_wdt_pt_info; |
253 | wdt->wdd.pretimeout = 1; |
254 | } else { |
255 | if (irq == -EPROBE_DEFER) |
256 | return -EPROBE_DEFER; |
257 | |
258 | wdt->wdd.info = &qcom_wdt_info; |
259 | } |
260 | |
261 | wdt->wdd.ops = &qcom_wdt_ops; |
262 | wdt->wdd.min_timeout = 1; |
263 | wdt->wdd.max_timeout = 0x10000000U / wdt->rate; |
264 | wdt->wdd.parent = dev; |
265 | wdt->layout = data->offset; |
266 | |
267 | if (readl(addr: wdt_addr(wdt, reg: WDT_STS)) & 1) |
268 | wdt->wdd.bootstatus = WDIOF_CARDRESET; |
269 | |
270 | /* |
271 | * If 'timeout-sec' unspecified in devicetree, assume a 30 second |
272 | * default, unless the max timeout is less than 30 seconds, then use |
273 | * the max instead. |
274 | */ |
275 | wdt->wdd.timeout = min(wdt->wdd.max_timeout, 30U); |
276 | watchdog_init_timeout(wdd: &wdt->wdd, timeout_parm: 0, dev); |
277 | |
278 | /* |
279 | * If WDT is already running, call WDT start which |
280 | * will stop the WDT, set timeouts as bootloader |
281 | * might use different ones and set running bit |
282 | * to inform the WDT subsystem to ping the WDT |
283 | */ |
284 | if (qcom_wdt_is_running(wdd: &wdt->wdd)) { |
285 | qcom_wdt_start(wdd: &wdt->wdd); |
286 | set_bit(WDOG_HW_RUNNING, addr: &wdt->wdd.status); |
287 | } |
288 | |
289 | ret = devm_watchdog_register_device(dev, &wdt->wdd); |
290 | if (ret) |
291 | return ret; |
292 | |
293 | platform_set_drvdata(pdev, data: wdt); |
294 | return 0; |
295 | } |
296 | |
297 | static int __maybe_unused qcom_wdt_suspend(struct device *dev) |
298 | { |
299 | struct qcom_wdt *wdt = dev_get_drvdata(dev); |
300 | |
301 | if (watchdog_active(wdd: &wdt->wdd)) |
302 | qcom_wdt_stop(wdd: &wdt->wdd); |
303 | |
304 | return 0; |
305 | } |
306 | |
307 | static int __maybe_unused qcom_wdt_resume(struct device *dev) |
308 | { |
309 | struct qcom_wdt *wdt = dev_get_drvdata(dev); |
310 | |
311 | if (watchdog_active(wdd: &wdt->wdd)) |
312 | qcom_wdt_start(wdd: &wdt->wdd); |
313 | |
314 | return 0; |
315 | } |
316 | |
317 | static const struct dev_pm_ops qcom_wdt_pm_ops = { |
318 | SET_LATE_SYSTEM_SLEEP_PM_OPS(qcom_wdt_suspend, qcom_wdt_resume) |
319 | }; |
320 | |
321 | static const struct of_device_id qcom_wdt_of_table[] = { |
322 | { .compatible = "qcom,kpss-timer" , .data = &match_data_apcs_tmr }, |
323 | { .compatible = "qcom,scss-timer" , .data = &match_data_apcs_tmr }, |
324 | { .compatible = "qcom,kpss-wdt" , .data = &match_data_kpss }, |
325 | { }, |
326 | }; |
327 | MODULE_DEVICE_TABLE(of, qcom_wdt_of_table); |
328 | |
329 | static struct platform_driver qcom_watchdog_driver = { |
330 | .probe = qcom_wdt_probe, |
331 | .driver = { |
332 | .name = KBUILD_MODNAME, |
333 | .of_match_table = qcom_wdt_of_table, |
334 | .pm = &qcom_wdt_pm_ops, |
335 | }, |
336 | }; |
337 | module_platform_driver(qcom_watchdog_driver); |
338 | |
339 | MODULE_DESCRIPTION("QCOM KPSS Watchdog Driver" ); |
340 | MODULE_LICENSE("GPL v2" ); |
341 | |