| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * sp5100_tco: TCO timer driver for sp5100 chipsets. |
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| 4 | * |
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| 5 | * (c) Copyright 2009 Google Inc., All Rights Reserved. |
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| 6 | * |
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| 7 | * TCO timer driver for sp5100 chipsets |
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| 8 | */ |
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| 9 | |
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| 10 | #include <linux/bitops.h> |
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| 11 | |
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| 12 | /* |
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| 13 | * Some address definitions for the Watchdog |
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| 14 | */ |
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| 15 | #define SP5100_WDT_MEM_MAP_SIZE 0x08 |
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| 16 | #define SP5100_WDT_CONTROL(base) ((base) + 0x00) /* Watchdog Control */ |
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| 17 | #define SP5100_WDT_COUNT(base) ((base) + 0x04) /* Watchdog Count */ |
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| 18 | |
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| 19 | #define SP5100_WDT_START_STOP_BIT BIT(0) |
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| 20 | #define SP5100_WDT_FIRED BIT(1) |
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| 21 | #define SP5100_WDT_ACTION_RESET BIT(2) |
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| 22 | #define SP5100_WDT_DISABLED BIT(3) |
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| 23 | #define SP5100_WDT_TRIGGER_BIT BIT(7) |
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| 24 | |
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| 25 | #define SP5100_PM_IOPORTS_SIZE 0x02 |
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| 26 | |
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| 27 | /* |
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| 28 | * These two IO registers are hardcoded and there doesn't seem to be a way to |
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| 29 | * read them from a register. |
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| 30 | */ |
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| 31 | |
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| 32 | /* For SP5100/SB7x0/SB8x0 chipset */ |
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| 33 | #define SP5100_IO_PM_INDEX_REG 0xCD6 |
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| 34 | #define SP5100_IO_PM_DATA_REG 0xCD7 |
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| 35 | |
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| 36 | /* For SP5100/SB7x0 chipset */ |
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| 37 | #define SP5100_SB_RESOURCE_MMIO_BASE 0x9C |
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| 38 | |
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| 39 | #define SP5100_PM_WATCHDOG_CONTROL 0x69 |
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| 40 | #define SP5100_PM_WATCHDOG_BASE 0x6C |
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| 41 | |
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| 42 | #define SP5100_PCI_WATCHDOG_MISC_REG 0x41 |
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| 43 | #define SP5100_PCI_WATCHDOG_DECODE_EN BIT(3) |
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| 44 | |
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| 45 | #define SP5100_PM_WATCHDOG_DISABLE ((u8)BIT(0)) |
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| 46 | #define SP5100_PM_WATCHDOG_SECOND_RES GENMASK(2, 1) |
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| 47 | |
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| 48 | #define SP5100_DEVNAME "SP5100 TCO" |
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| 49 | |
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| 50 | /* For SB8x0(or later) chipset */ |
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| 51 | #define SB800_PM_ACPI_MMIO_EN 0x24 |
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| 52 | #define SB800_PM_WATCHDOG_CONTROL 0x48 |
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| 53 | #define SB800_PM_WATCHDOG_BASE 0x48 |
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| 54 | #define SB800_PM_WATCHDOG_CONFIG 0x4C |
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| 55 | |
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| 56 | #define SB800_PCI_WATCHDOG_DECODE_EN BIT(0) |
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| 57 | #define SB800_PM_WATCHDOG_DISABLE ((u8)BIT(1)) |
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| 58 | #define SB800_PM_WATCHDOG_SECOND_RES GENMASK(1, 0) |
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| 59 | #define SB800_ACPI_MMIO_DECODE_EN BIT(0) |
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| 60 | #define SB800_ACPI_MMIO_SEL BIT(1) |
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| 61 | #define SB800_ACPI_MMIO_MASK GENMASK(1, 0) |
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| 62 | |
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| 63 | #define SB800_PM_WDT_MMIO_OFFSET 0xB00 |
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| 64 | |
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| 65 | #define SB800_DEVNAME "SB800 TCO" |
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| 66 | |
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| 67 | /* For recent chips with embedded FCH (rev 40+) */ |
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| 68 | |
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| 69 | #define EFCH_PM_DECODEEN 0x00 |
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| 70 | |
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| 71 | #define EFCH_PM_DECODEEN_WDT_TMREN BIT(7) |
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| 72 | |
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| 73 | |
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| 74 | #define EFCH_PM_DECODEEN3 0x03 |
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| 75 | #define EFCH_PM_DECODEEN_SECOND_RES GENMASK(1, 0) |
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| 76 | #define EFCH_PM_WATCHDOG_DISABLE ((u8)GENMASK(3, 2)) |
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| 77 | |
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| 78 | /* WDT MMIO if enabled with PM00_DECODEEN_WDT_TMREN */ |
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| 79 | #define EFCH_PM_WDT_ADDR 0xfeb00000 |
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| 80 | |
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| 81 | #define EFCH_PM_ISACONTROL 0x04 |
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| 82 | |
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| 83 | #define EFCH_PM_ISACONTROL_MMIOEN BIT(1) |
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| 84 | |
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| 85 | #define EFCH_PM_ACPI_MMIO_ADDR 0xfed80000 |
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| 86 | #define EFCH_PM_ACPI_MMIO_PM_OFFSET 0x00000300 |
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| 87 | #define EFCH_PM_ACPI_MMIO_WDT_OFFSET 0x00000b00 |
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| 88 | |
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| 89 | #define EFCH_PM_ACPI_MMIO_PM_ADDR (EFCH_PM_ACPI_MMIO_ADDR + \ |
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| 90 | EFCH_PM_ACPI_MMIO_PM_OFFSET) |
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| 91 | #define EFCH_PM_ACPI_MMIO_PM_SIZE 8 |
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| 92 | #define AMD_ZEN_SMBUS_PCI_REV 0x51 |
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| 93 | |
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