1/*
2 * Copyright © 2008 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23#ifndef _DRM_DP_HELPER_H_
24#define _DRM_DP_HELPER_H_
25
26#include <linux/types.h>
27#include <linux/i2c.h>
28#include <linux/delay.h>
29
30/*
31 * Unless otherwise noted, all values are from the DP 1.1a spec. Note that
32 * DP and DPCD versions are independent. Differences from 1.0 are not noted,
33 * 1.0 devices basically don't exist in the wild.
34 *
35 * Abbreviations, in chronological order:
36 *
37 * eDP: Embedded DisplayPort version 1
38 * DPI: DisplayPort Interoperability Guideline v1.1a
39 * 1.2: DisplayPort 1.2
40 * MST: Multistream Transport - part of DP 1.2a
41 *
42 * 1.2 formally includes both eDP and DPI definitions.
43 */
44
45#define DP_AUX_MAX_PAYLOAD_BYTES 16
46
47#define DP_AUX_I2C_WRITE 0x0
48#define DP_AUX_I2C_READ 0x1
49#define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2
50#define DP_AUX_I2C_MOT 0x4
51#define DP_AUX_NATIVE_WRITE 0x8
52#define DP_AUX_NATIVE_READ 0x9
53
54#define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0)
55#define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0)
56#define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0)
57#define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0)
58
59#define DP_AUX_I2C_REPLY_ACK (0x0 << 2)
60#define DP_AUX_I2C_REPLY_NACK (0x1 << 2)
61#define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)
62#define DP_AUX_I2C_REPLY_MASK (0x3 << 2)
63
64/* AUX CH addresses */
65/* DPCD */
66#define DP_DPCD_REV 0x000
67# define DP_DPCD_REV_10 0x10
68# define DP_DPCD_REV_11 0x11
69# define DP_DPCD_REV_12 0x12
70# define DP_DPCD_REV_13 0x13
71# define DP_DPCD_REV_14 0x14
72
73#define DP_MAX_LINK_RATE 0x001
74
75#define DP_MAX_LANE_COUNT 0x002
76# define DP_MAX_LANE_COUNT_MASK 0x1f
77# define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */
78# define DP_ENHANCED_FRAME_CAP (1 << 7)
79
80#define DP_MAX_DOWNSPREAD 0x003
81# define DP_MAX_DOWNSPREAD_0_5 (1 << 0)
82# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
83# define DP_TPS4_SUPPORTED (1 << 7)
84
85#define DP_NORP 0x004
86
87#define DP_DOWNSTREAMPORT_PRESENT 0x005
88# define DP_DWN_STRM_PORT_PRESENT (1 << 0)
89# define DP_DWN_STRM_PORT_TYPE_MASK 0x06
90# define DP_DWN_STRM_PORT_TYPE_DP (0 << 1)
91# define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1)
92# define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1)
93# define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1)
94# define DP_FORMAT_CONVERSION (1 << 3)
95# define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */
96
97#define DP_MAIN_LINK_CHANNEL_CODING 0x006
98
99#define DP_DOWN_STREAM_PORT_COUNT 0x007
100# define DP_PORT_COUNT_MASK 0x0f
101# define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */
102# define DP_OUI_SUPPORT (1 << 7)
103
104#define DP_RECEIVE_PORT_0_CAP_0 0x008
105# define DP_LOCAL_EDID_PRESENT (1 << 1)
106# define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2)
107
108#define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009
109
110#define DP_RECEIVE_PORT_1_CAP_0 0x00a
111#define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b
112
113#define DP_I2C_SPEED_CAP 0x00c /* DPI */
114# define DP_I2C_SPEED_1K 0x01
115# define DP_I2C_SPEED_5K 0x02
116# define DP_I2C_SPEED_10K 0x04
117# define DP_I2C_SPEED_100K 0x08
118# define DP_I2C_SPEED_400K 0x10
119# define DP_I2C_SPEED_1M 0x20
120
121#define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
122# define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0)
123# define DP_FRAMING_CHANGE_CAP (1 << 1)
124# define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
125
126#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
127# define DP_TRAINING_AUX_RD_MASK 0x7F /* DP 1.3 */
128# define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7) /* DP 1.3 */
129
130#define DP_ADAPTER_CAP 0x00f /* 1.2 */
131# define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
132# define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1)
133
134#define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */
135# define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
136
137/* Multiple stream transport */
138#define DP_FAUX_CAP 0x020 /* 1.2 */
139# define DP_FAUX_CAP_1 (1 << 0)
140
141#define DP_MSTM_CAP 0x021 /* 1.2 */
142# define DP_MST_CAP (1 << 0)
143
144#define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */
145
146/* AV_SYNC_DATA_BLOCK 1.2 */
147#define DP_AV_GRANULARITY 0x023
148# define DP_AG_FACTOR_MASK (0xf << 0)
149# define DP_AG_FACTOR_3MS (0 << 0)
150# define DP_AG_FACTOR_2MS (1 << 0)
151# define DP_AG_FACTOR_1MS (2 << 0)
152# define DP_AG_FACTOR_500US (3 << 0)
153# define DP_AG_FACTOR_200US (4 << 0)
154# define DP_AG_FACTOR_100US (5 << 0)
155# define DP_AG_FACTOR_10US (6 << 0)
156# define DP_AG_FACTOR_1US (7 << 0)
157# define DP_VG_FACTOR_MASK (0xf << 4)
158# define DP_VG_FACTOR_3MS (0 << 4)
159# define DP_VG_FACTOR_2MS (1 << 4)
160# define DP_VG_FACTOR_1MS (2 << 4)
161# define DP_VG_FACTOR_500US (3 << 4)
162# define DP_VG_FACTOR_200US (4 << 4)
163# define DP_VG_FACTOR_100US (5 << 4)
164
165#define DP_AUD_DEC_LAT0 0x024
166#define DP_AUD_DEC_LAT1 0x025
167
168#define DP_AUD_PP_LAT0 0x026
169#define DP_AUD_PP_LAT1 0x027
170
171#define DP_VID_INTER_LAT 0x028
172
173#define DP_VID_PROG_LAT 0x029
174
175#define DP_REP_LAT 0x02a
176
177#define DP_AUD_DEL_INS0 0x02b
178#define DP_AUD_DEL_INS1 0x02c
179#define DP_AUD_DEL_INS2 0x02d
180/* End of AV_SYNC_DATA_BLOCK */
181
182#define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */
183# define DP_ALPM_CAP (1 << 0)
184
185#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */
186# define DP_AUX_FRAME_SYNC_CAP (1 << 0)
187
188#define DP_GUID 0x030 /* 1.2 */
189
190#define DP_DSC_SUPPORT 0x060 /* DP 1.4 */
191# define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0)
192
193#define DP_DSC_REV 0x061
194# define DP_DSC_MAJOR_MASK (0xf << 0)
195# define DP_DSC_MINOR_MASK (0xf << 4)
196# define DP_DSC_MAJOR_SHIFT 0
197# define DP_DSC_MINOR_SHIFT 4
198
199#define DP_DSC_RC_BUF_BLK_SIZE 0x062
200# define DP_DSC_RC_BUF_BLK_SIZE_1 0x0
201# define DP_DSC_RC_BUF_BLK_SIZE_4 0x1
202# define DP_DSC_RC_BUF_BLK_SIZE_16 0x2
203# define DP_DSC_RC_BUF_BLK_SIZE_64 0x3
204
205#define DP_DSC_RC_BUF_SIZE 0x063
206
207#define DP_DSC_SLICE_CAP_1 0x064
208# define DP_DSC_1_PER_DP_DSC_SINK (1 << 0)
209# define DP_DSC_2_PER_DP_DSC_SINK (1 << 1)
210# define DP_DSC_4_PER_DP_DSC_SINK (1 << 3)
211# define DP_DSC_6_PER_DP_DSC_SINK (1 << 4)
212# define DP_DSC_8_PER_DP_DSC_SINK (1 << 5)
213# define DP_DSC_10_PER_DP_DSC_SINK (1 << 6)
214# define DP_DSC_12_PER_DP_DSC_SINK (1 << 7)
215
216#define DP_DSC_LINE_BUF_BIT_DEPTH 0x065
217# define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0)
218# define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0
219# define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1
220# define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2
221# define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3
222# define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4
223# define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5
224# define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6
225# define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7
226# define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8
227
228#define DP_DSC_BLK_PREDICTION_SUPPORT 0x066
229# define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0)
230
231#define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */
232
233#define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */
234# define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0)
235# define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8
236
237#define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069
238# define DP_DSC_RGB (1 << 0)
239# define DP_DSC_YCbCr444 (1 << 1)
240# define DP_DSC_YCbCr422_Simple (1 << 2)
241# define DP_DSC_YCbCr422_Native (1 << 3)
242# define DP_DSC_YCbCr420_Native (1 << 4)
243
244#define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A
245# define DP_DSC_8_BPC (1 << 1)
246# define DP_DSC_10_BPC (1 << 2)
247# define DP_DSC_12_BPC (1 << 3)
248
249#define DP_DSC_PEAK_THROUGHPUT 0x06B
250# define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0)
251# define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0
252# define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0)
253# define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0)
254# define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0)
255# define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0)
256# define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0)
257# define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0)
258# define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0)
259# define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0)
260# define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0)
261# define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0)
262# define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0)
263# define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0)
264# define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0)
265# define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0)
266# define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4)
267# define DP_DSC_THROUGHPUT_MODE_1_SHIFT 4
268# define DP_DSC_THROUGHPUT_MODE_1_340 (1 << 4)
269# define DP_DSC_THROUGHPUT_MODE_1_400 (2 << 4)
270# define DP_DSC_THROUGHPUT_MODE_1_450 (3 << 4)
271# define DP_DSC_THROUGHPUT_MODE_1_500 (4 << 4)
272# define DP_DSC_THROUGHPUT_MODE_1_550 (5 << 4)
273# define DP_DSC_THROUGHPUT_MODE_1_600 (6 << 4)
274# define DP_DSC_THROUGHPUT_MODE_1_650 (7 << 4)
275# define DP_DSC_THROUGHPUT_MODE_1_700 (8 << 4)
276# define DP_DSC_THROUGHPUT_MODE_1_750 (9 << 4)
277# define DP_DSC_THROUGHPUT_MODE_1_800 (10 << 4)
278# define DP_DSC_THROUGHPUT_MODE_1_850 (11 << 4)
279# define DP_DSC_THROUGHPUT_MODE_1_900 (12 << 4)
280# define DP_DSC_THROUGHPUT_MODE_1_950 (13 << 4)
281# define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4)
282
283#define DP_DSC_MAX_SLICE_WIDTH 0x06C
284#define DP_DSC_MIN_SLICE_WIDTH_VALUE 2560
285#define DP_DSC_SLICE_WIDTH_MULTIPLIER 320
286
287#define DP_DSC_SLICE_CAP_2 0x06D
288# define DP_DSC_16_PER_DP_DSC_SINK (1 << 0)
289# define DP_DSC_20_PER_DP_DSC_SINK (1 << 1)
290# define DP_DSC_24_PER_DP_DSC_SINK (1 << 2)
291
292#define DP_DSC_BITS_PER_PIXEL_INC 0x06F
293# define DP_DSC_BITS_PER_PIXEL_1_16 0x0
294# define DP_DSC_BITS_PER_PIXEL_1_8 0x1
295# define DP_DSC_BITS_PER_PIXEL_1_4 0x2
296# define DP_DSC_BITS_PER_PIXEL_1_2 0x3
297# define DP_DSC_BITS_PER_PIXEL_1 0x4
298
299#define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
300# define DP_PSR_IS_SUPPORTED 1
301# define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */
302# define DP_PSR2_WITH_Y_COORD_IS_SUPPORTED 3 /* eDP 1.4a */
303
304#define DP_PSR_CAPS 0x071 /* XXX 1.2? */
305# define DP_PSR_NO_TRAIN_ON_EXIT 1
306# define DP_PSR_SETUP_TIME_330 (0 << 1)
307# define DP_PSR_SETUP_TIME_275 (1 << 1)
308# define DP_PSR_SETUP_TIME_220 (2 << 1)
309# define DP_PSR_SETUP_TIME_165 (3 << 1)
310# define DP_PSR_SETUP_TIME_110 (4 << 1)
311# define DP_PSR_SETUP_TIME_55 (5 << 1)
312# define DP_PSR_SETUP_TIME_0 (6 << 1)
313# define DP_PSR_SETUP_TIME_MASK (7 << 1)
314# define DP_PSR_SETUP_TIME_SHIFT 1
315# define DP_PSR2_SU_Y_COORDINATE_REQUIRED (1 << 4) /* eDP 1.4a */
316# define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */
317
318#define DP_PSR2_SU_X_GRANULARITY 0x072 /* eDP 1.4b */
319#define DP_PSR2_SU_Y_GRANULARITY 0x074 /* eDP 1.4b */
320
321/*
322 * 0x80-0x8f describe downstream port capabilities, but there are two layouts
323 * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not,
324 * each port's descriptor is one byte wide. If it was set, each port's is
325 * four bytes wide, starting with the one byte from the base info. As of
326 * DP interop v1.1a only VGA defines additional detail.
327 */
328
329/* offset 0 */
330#define DP_DOWNSTREAM_PORT_0 0x80
331# define DP_DS_PORT_TYPE_MASK (7 << 0)
332# define DP_DS_PORT_TYPE_DP 0
333# define DP_DS_PORT_TYPE_VGA 1
334# define DP_DS_PORT_TYPE_DVI 2
335# define DP_DS_PORT_TYPE_HDMI 3
336# define DP_DS_PORT_TYPE_NON_EDID 4
337# define DP_DS_PORT_TYPE_DP_DUALMODE 5
338# define DP_DS_PORT_TYPE_WIRELESS 6
339# define DP_DS_PORT_HPD (1 << 3)
340/* offset 1 for VGA is maximum megapixels per second / 8 */
341/* offset 2 */
342# define DP_DS_MAX_BPC_MASK (3 << 0)
343# define DP_DS_8BPC 0
344# define DP_DS_10BPC 1
345# define DP_DS_12BPC 2
346# define DP_DS_16BPC 3
347
348/* DP Forward error Correction Registers */
349#define DP_FEC_CAPABILITY 0x090 /* 1.4 */
350# define DP_FEC_CAPABLE (1 << 0)
351# define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1)
352# define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2)
353# define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3)
354
355/* link configuration */
356#define DP_LINK_BW_SET 0x100
357# define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
358# define DP_LINK_BW_1_62 0x06
359# define DP_LINK_BW_2_7 0x0a
360# define DP_LINK_BW_5_4 0x14 /* 1.2 */
361# define DP_LINK_BW_8_1 0x1e /* 1.4 */
362
363#define DP_LANE_COUNT_SET 0x101
364# define DP_LANE_COUNT_MASK 0x0f
365# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
366
367#define DP_TRAINING_PATTERN_SET 0x102
368# define DP_TRAINING_PATTERN_DISABLE 0
369# define DP_TRAINING_PATTERN_1 1
370# define DP_TRAINING_PATTERN_2 2
371# define DP_TRAINING_PATTERN_3 3 /* 1.2 */
372# define DP_TRAINING_PATTERN_4 7 /* 1.4 */
373# define DP_TRAINING_PATTERN_MASK 0x3
374# define DP_TRAINING_PATTERN_MASK_1_4 0xf
375
376/* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */
377# define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2)
378# define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2)
379# define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2)
380# define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2)
381# define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2)
382
383# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
384# define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
385
386# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
387# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
388# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
389# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
390
391#define DP_TRAINING_LANE0_SET 0x103
392#define DP_TRAINING_LANE1_SET 0x104
393#define DP_TRAINING_LANE2_SET 0x105
394#define DP_TRAINING_LANE3_SET 0x106
395
396# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
397# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
398# define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
399# define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
400# define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
401# define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
402# define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
403
404# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
405# define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3)
406# define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3)
407# define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3)
408# define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3)
409
410# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
411# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
412
413#define DP_DOWNSPREAD_CTRL 0x107
414# define DP_SPREAD_AMP_0_5 (1 << 4)
415# define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */
416
417#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
418# define DP_SET_ANSI_8B10B (1 << 0)
419
420#define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */
421/* bitmask as for DP_I2C_SPEED_CAP */
422
423#define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
424# define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0)
425# define DP_FRAMING_CHANGE_ENABLE (1 << 1)
426# define DP_PANEL_SELF_TEST_ENABLE (1 << 7)
427
428#define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */
429#define DP_LINK_QUAL_LANE1_SET 0x10c
430#define DP_LINK_QUAL_LANE2_SET 0x10d
431#define DP_LINK_QUAL_LANE3_SET 0x10e
432# define DP_LINK_QUAL_PATTERN_DISABLE 0
433# define DP_LINK_QUAL_PATTERN_D10_2 1
434# define DP_LINK_QUAL_PATTERN_ERROR_RATE 2
435# define DP_LINK_QUAL_PATTERN_PRBS7 3
436# define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4
437# define DP_LINK_QUAL_PATTERN_HBR2_EYE 5
438# define DP_LINK_QUAL_PATTERN_MASK 7
439
440#define DP_TRAINING_LANE0_1_SET2 0x10f
441#define DP_TRAINING_LANE2_3_SET2 0x110
442# define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0)
443# define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2)
444# define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4)
445# define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6)
446
447#define DP_MSTM_CTRL 0x111 /* 1.2 */
448# define DP_MST_EN (1 << 0)
449# define DP_UP_REQ_EN (1 << 1)
450# define DP_UPSTREAM_IS_SRC (1 << 2)
451
452#define DP_AUDIO_DELAY0 0x112 /* 1.2 */
453#define DP_AUDIO_DELAY1 0x113
454#define DP_AUDIO_DELAY2 0x114
455
456#define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */
457# define DP_LINK_RATE_SET_SHIFT 0
458# define DP_LINK_RATE_SET_MASK (7 << 0)
459
460#define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */
461# define DP_ALPM_ENABLE (1 << 0)
462# define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1)
463
464#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */
465# define DP_AUX_FRAME_SYNC_ENABLE (1 << 0)
466# define DP_IRQ_HPD_ENABLE (1 << 1)
467
468#define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */
469# define DP_PWR_NOT_NEEDED (1 << 0)
470
471#define DP_FEC_CONFIGURATION 0x120 /* 1.4 */
472# define DP_FEC_READY (1 << 0)
473# define DP_FEC_ERR_COUNT_SEL_MASK (7 << 1)
474# define DP_FEC_ERR_COUNT_DIS (0 << 1)
475# define DP_FEC_UNCORR_BLK_ERROR_COUNT (1 << 1)
476# define DP_FEC_CORR_BLK_ERROR_COUNT (2 << 1)
477# define DP_FEC_BIT_ERROR_COUNT (3 << 1)
478# define DP_FEC_LANE_SELECT_MASK (3 << 4)
479# define DP_FEC_LANE_0_SELECT (0 << 4)
480# define DP_FEC_LANE_1_SELECT (1 << 4)
481# define DP_FEC_LANE_2_SELECT (2 << 4)
482# define DP_FEC_LANE_3_SELECT (3 << 4)
483
484#define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
485# define DP_AUX_FRAME_SYNC_VALID (1 << 0)
486
487#define DP_DSC_ENABLE 0x160 /* DP 1.4 */
488# define DP_DECOMPRESSION_EN (1 << 0)
489
490#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
491# define DP_PSR_ENABLE (1 << 0)
492# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
493# define DP_PSR_CRC_VERIFICATION (1 << 2)
494# define DP_PSR_FRAME_CAPTURE (1 << 3)
495# define DP_PSR_SELECTIVE_UPDATE (1 << 4)
496# define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5)
497# define DP_PSR_ENABLE_PSR2 (1 << 6) /* eDP 1.4a */
498
499#define DP_ADAPTER_CTRL 0x1a0
500# define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
501
502#define DP_BRANCH_DEVICE_CTRL 0x1a1
503# define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
504
505#define DP_PAYLOAD_ALLOCATE_SET 0x1c0
506#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
507#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
508
509#define DP_SINK_COUNT 0x200
510/* prior to 1.2 bit 7 was reserved mbz */
511# define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
512# define DP_SINK_CP_READY (1 << 6)
513
514#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
515# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
516# define DP_AUTOMATED_TEST_REQUEST (1 << 1)
517# define DP_CP_IRQ (1 << 2)
518# define DP_MCCS_IRQ (1 << 3)
519# define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */
520# define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */
521# define DP_SINK_SPECIFIC_IRQ (1 << 6)
522
523#define DP_LANE0_1_STATUS 0x202
524#define DP_LANE2_3_STATUS 0x203
525# define DP_LANE_CR_DONE (1 << 0)
526# define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
527# define DP_LANE_SYMBOL_LOCKED (1 << 2)
528
529#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
530 DP_LANE_CHANNEL_EQ_DONE | \
531 DP_LANE_SYMBOL_LOCKED)
532
533#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
534
535#define DP_INTERLANE_ALIGN_DONE (1 << 0)
536#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
537#define DP_LINK_STATUS_UPDATED (1 << 7)
538
539#define DP_SINK_STATUS 0x205
540
541#define DP_RECEIVE_PORT_0_STATUS (1 << 0)
542#define DP_RECEIVE_PORT_1_STATUS (1 << 1)
543
544#define DP_ADJUST_REQUEST_LANE0_1 0x206
545#define DP_ADJUST_REQUEST_LANE2_3 0x207
546# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
547# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
548# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
549# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
550# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
551# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
552# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
553# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
554
555#define DP_ADJUST_REQUEST_POST_CURSOR2 0x20c
556
557#define DP_TEST_REQUEST 0x218
558# define DP_TEST_LINK_TRAINING (1 << 0)
559# define DP_TEST_LINK_VIDEO_PATTERN (1 << 1)
560# define DP_TEST_LINK_EDID_READ (1 << 2)
561# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */
562# define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */
563# define DP_TEST_LINK_AUDIO_PATTERN (1 << 5) /* DPCD >= 1.2 */
564# define DP_TEST_LINK_AUDIO_DISABLED_VIDEO (1 << 6) /* DPCD >= 1.2 */
565
566#define DP_TEST_LINK_RATE 0x219
567# define DP_LINK_RATE_162 (0x6)
568# define DP_LINK_RATE_27 (0xa)
569
570#define DP_TEST_LANE_COUNT 0x220
571
572#define DP_TEST_PATTERN 0x221
573# define DP_NO_TEST_PATTERN 0x0
574# define DP_COLOR_RAMP 0x1
575# define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2
576# define DP_COLOR_SQUARE 0x3
577
578#define DP_TEST_H_TOTAL_HI 0x222
579#define DP_TEST_H_TOTAL_LO 0x223
580
581#define DP_TEST_V_TOTAL_HI 0x224
582#define DP_TEST_V_TOTAL_LO 0x225
583
584#define DP_TEST_H_START_HI 0x226
585#define DP_TEST_H_START_LO 0x227
586
587#define DP_TEST_V_START_HI 0x228
588#define DP_TEST_V_START_LO 0x229
589
590#define DP_TEST_HSYNC_HI 0x22A
591# define DP_TEST_HSYNC_POLARITY (1 << 7)
592# define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0)
593#define DP_TEST_HSYNC_WIDTH_LO 0x22B
594
595#define DP_TEST_VSYNC_HI 0x22C
596# define DP_TEST_VSYNC_POLARITY (1 << 7)
597# define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0)
598#define DP_TEST_VSYNC_WIDTH_LO 0x22D
599
600#define DP_TEST_H_WIDTH_HI 0x22E
601#define DP_TEST_H_WIDTH_LO 0x22F
602
603#define DP_TEST_V_HEIGHT_HI 0x230
604#define DP_TEST_V_HEIGHT_LO 0x231
605
606#define DP_TEST_MISC0 0x232
607# define DP_TEST_SYNC_CLOCK (1 << 0)
608# define DP_TEST_COLOR_FORMAT_MASK (3 << 1)
609# define DP_TEST_COLOR_FORMAT_SHIFT 1
610# define DP_COLOR_FORMAT_RGB (0 << 1)
611# define DP_COLOR_FORMAT_YCbCr422 (1 << 1)
612# define DP_COLOR_FORMAT_YCbCr444 (2 << 1)
613# define DP_TEST_DYNAMIC_RANGE_VESA (0 << 3)
614# define DP_TEST_DYNAMIC_RANGE_CEA (1 << 3)
615# define DP_TEST_YCBCR_COEFFICIENTS (1 << 4)
616# define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4)
617# define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4)
618# define DP_TEST_BIT_DEPTH_MASK (7 << 5)
619# define DP_TEST_BIT_DEPTH_SHIFT 5
620# define DP_TEST_BIT_DEPTH_6 (0 << 5)
621# define DP_TEST_BIT_DEPTH_8 (1 << 5)
622# define DP_TEST_BIT_DEPTH_10 (2 << 5)
623# define DP_TEST_BIT_DEPTH_12 (3 << 5)
624# define DP_TEST_BIT_DEPTH_16 (4 << 5)
625
626#define DP_TEST_MISC1 0x233
627# define DP_TEST_REFRESH_DENOMINATOR (1 << 0)
628# define DP_TEST_INTERLACED (1 << 1)
629
630#define DP_TEST_REFRESH_RATE_NUMERATOR 0x234
631
632#define DP_TEST_MISC0 0x232
633
634#define DP_TEST_CRC_R_CR 0x240
635#define DP_TEST_CRC_G_Y 0x242
636#define DP_TEST_CRC_B_CB 0x244
637
638#define DP_TEST_SINK_MISC 0x246
639# define DP_TEST_CRC_SUPPORTED (1 << 5)
640# define DP_TEST_COUNT_MASK 0xf
641
642#define DP_TEST_PHY_PATTERN 0x248
643#define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
644#define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
645#define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252
646#define DP_TEST_80BIT_CUSTOM_PATTERN_31_24 0x253
647#define DP_TEST_80BIT_CUSTOM_PATTERN_39_32 0x254
648#define DP_TEST_80BIT_CUSTOM_PATTERN_47_40 0x255
649#define DP_TEST_80BIT_CUSTOM_PATTERN_55_48 0x256
650#define DP_TEST_80BIT_CUSTOM_PATTERN_63_56 0x257
651#define DP_TEST_80BIT_CUSTOM_PATTERN_71_64 0x258
652#define DP_TEST_80BIT_CUSTOM_PATTERN_79_72 0x259
653
654#define DP_TEST_RESPONSE 0x260
655# define DP_TEST_ACK (1 << 0)
656# define DP_TEST_NAK (1 << 1)
657# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
658
659#define DP_TEST_EDID_CHECKSUM 0x261
660
661#define DP_TEST_SINK 0x270
662# define DP_TEST_SINK_START (1 << 0)
663#define DP_TEST_AUDIO_MODE 0x271
664#define DP_TEST_AUDIO_PATTERN_TYPE 0x272
665#define DP_TEST_AUDIO_PERIOD_CH1 0x273
666#define DP_TEST_AUDIO_PERIOD_CH2 0x274
667#define DP_TEST_AUDIO_PERIOD_CH3 0x275
668#define DP_TEST_AUDIO_PERIOD_CH4 0x276
669#define DP_TEST_AUDIO_PERIOD_CH5 0x277
670#define DP_TEST_AUDIO_PERIOD_CH6 0x278
671#define DP_TEST_AUDIO_PERIOD_CH7 0x279
672#define DP_TEST_AUDIO_PERIOD_CH8 0x27A
673
674#define DP_FEC_STATUS 0x280 /* 1.4 */
675# define DP_FEC_DECODE_EN_DETECTED (1 << 0)
676# define DP_FEC_DECODE_DIS_DETECTED (1 << 1)
677
678#define DP_FEC_ERROR_COUNT_LSB 0x0281 /* 1.4 */
679
680#define DP_FEC_ERROR_COUNT_MSB 0x0282 /* 1.4 */
681# define DP_FEC_ERROR_COUNT_MASK 0x7F
682# define DP_FEC_ERR_COUNT_VALID (1 << 7)
683
684#define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */
685# define DP_PAYLOAD_TABLE_UPDATED (1 << 0)
686# define DP_PAYLOAD_ACT_HANDLED (1 << 1)
687
688#define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */
689/* up to ID_SLOT_63 at 0x2ff */
690
691#define DP_SOURCE_OUI 0x300
692#define DP_SINK_OUI 0x400
693#define DP_BRANCH_OUI 0x500
694#define DP_BRANCH_ID 0x503
695#define DP_BRANCH_REVISION_START 0x509
696#define DP_BRANCH_HW_REV 0x509
697#define DP_BRANCH_SW_REV 0x50A
698
699#define DP_SET_POWER 0x600
700# define DP_SET_POWER_D0 0x1
701# define DP_SET_POWER_D3 0x2
702# define DP_SET_POWER_MASK 0x3
703# define DP_SET_POWER_D3_AUX_ON 0x5
704
705#define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
706# define DP_EDP_11 0x00
707# define DP_EDP_12 0x01
708# define DP_EDP_13 0x02
709# define DP_EDP_14 0x03
710# define DP_EDP_14a 0x04 /* eDP 1.4a */
711# define DP_EDP_14b 0x05 /* eDP 1.4b */
712
713#define DP_EDP_GENERAL_CAP_1 0x701
714# define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0)
715# define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP (1 << 1)
716# define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP (1 << 2)
717# define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP (1 << 3)
718# define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP (1 << 4)
719# define DP_EDP_FRC_ENABLE_CAP (1 << 5)
720# define DP_EDP_COLOR_ENGINE_CAP (1 << 6)
721# define DP_EDP_SET_POWER_CAP (1 << 7)
722
723#define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702
724# define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0)
725# define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP (1 << 1)
726# define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT (1 << 2)
727# define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP (1 << 3)
728# define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP (1 << 4)
729# define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5)
730# define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6)
731# define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7)
732
733#define DP_EDP_GENERAL_CAP_2 0x703
734# define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0)
735
736#define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */
737# define DP_EDP_X_REGION_CAP_MASK (0xf << 0)
738# define DP_EDP_X_REGION_CAP_SHIFT 0
739# define DP_EDP_Y_REGION_CAP_MASK (0xf << 4)
740# define DP_EDP_Y_REGION_CAP_SHIFT 4
741
742#define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720
743# define DP_EDP_BACKLIGHT_ENABLE (1 << 0)
744# define DP_EDP_BLACK_VIDEO_ENABLE (1 << 1)
745# define DP_EDP_FRC_ENABLE (1 << 2)
746# define DP_EDP_COLOR_ENGINE_ENABLE (1 << 3)
747# define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE (1 << 7)
748
749#define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721
750# define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0)
751# define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0)
752# define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0)
753# define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0)
754# define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0)
755# define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE (1 << 2)
756# define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE (1 << 3)
757# define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE (1 << 4)
758# define DP_EDP_REGIONAL_BACKLIGHT_ENABLE (1 << 5)
759# define DP_EDP_UPDATE_REGION_BRIGHTNESS (1 << 6) /* eDP 1.4 */
760
761#define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722
762#define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723
763
764#define DP_EDP_PWMGEN_BIT_COUNT 0x724
765#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725
766#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726
767# define DP_EDP_PWMGEN_BIT_COUNT_MASK (0x1f << 0)
768
769#define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727
770
771#define DP_EDP_BACKLIGHT_FREQ_SET 0x728
772# define DP_EDP_BACKLIGHT_FREQ_BASE_KHZ 27000
773
774#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a
775#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b
776#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c
777
778#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d
779#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e
780#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f
781
782#define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732
783#define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733
784
785#define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */
786#define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */
787
788#define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
789#define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
790#define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
791#define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */
792
793#define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */
794/* 0-5 sink count */
795# define DP_SINK_COUNT_CP_READY (1 << 6)
796
797#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */
798
799#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */
800# define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE (1 << 0)
801# define DP_LOCK_ACQUISITION_REQUEST (1 << 1)
802# define DP_CEC_IRQ (1 << 2)
803
804#define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */
805
806#define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
807# define DP_PSR_LINK_CRC_ERROR (1 << 0)
808# define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
809# define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */
810
811#define DP_PSR_ESI 0x2007 /* XXX 1.2? */
812# define DP_PSR_CAPS_CHANGE (1 << 0)
813
814#define DP_PSR_STATUS 0x2008 /* XXX 1.2? */
815# define DP_PSR_SINK_INACTIVE 0
816# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
817# define DP_PSR_SINK_ACTIVE_RFB 2
818# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3
819# define DP_PSR_SINK_ACTIVE_RESYNC 4
820# define DP_PSR_SINK_INTERNAL_ERROR 7
821# define DP_PSR_SINK_STATE_MASK 0x07
822
823#define DP_SYNCHRONIZATION_LATENCY_IN_SINK 0x2009 /* edp 1.4 */
824# define DP_MAX_RESYNC_FRAME_COUNT_MASK (0xf << 0)
825# define DP_MAX_RESYNC_FRAME_COUNT_SHIFT 0
826# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK (0xf << 4)
827# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT 4
828
829#define DP_LAST_RECEIVED_PSR_SDP 0x200a /* eDP 1.2 */
830# define DP_PSR_STATE_BIT (1 << 0) /* eDP 1.2 */
831# define DP_UPDATE_RFB_BIT (1 << 1) /* eDP 1.2 */
832# define DP_CRC_VALID_BIT (1 << 2) /* eDP 1.2 */
833# define DP_SU_VALID (1 << 3) /* eDP 1.4 */
834# define DP_FIRST_SCAN_LINE_SU_REGION (1 << 4) /* eDP 1.4 */
835# define DP_LAST_SCAN_LINE_SU_REGION (1 << 5) /* eDP 1.4 */
836# define DP_Y_COORDINATE_VALID (1 << 6) /* eDP 1.4a */
837
838#define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
839# define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
840
841#define DP_LANE0_1_STATUS_ESI 0x200c /* status same as 0x202 */
842#define DP_LANE2_3_STATUS_ESI 0x200d /* status same as 0x203 */
843#define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */
844#define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */
845
846#define DP_DP13_DPCD_REV 0x2200
847#define DP_DP13_MAX_LINK_RATE 0x2201
848
849#define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */
850# define DP_GTC_CAP (1 << 0) /* DP 1.3 */
851# define DP_SST_SPLIT_SDP_CAP (1 << 1) /* DP 1.4 */
852# define DP_AV_SYNC_CAP (1 << 2) /* DP 1.3 */
853# define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED (1 << 3) /* DP 1.3 */
854# define DP_VSC_EXT_VESA_SDP_SUPPORTED (1 << 4) /* DP 1.4 */
855# define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED (1 << 5) /* DP 1.4 */
856# define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6) /* DP 1.4 */
857# define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7) /* DP 1.4 */
858
859/* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
860#define DP_CEC_TUNNELING_CAPABILITY 0x3000
861# define DP_CEC_TUNNELING_CAPABLE (1 << 0)
862# define DP_CEC_SNOOPING_CAPABLE (1 << 1)
863# define DP_CEC_MULTIPLE_LA_CAPABLE (1 << 2)
864
865#define DP_CEC_TUNNELING_CONTROL 0x3001
866# define DP_CEC_TUNNELING_ENABLE (1 << 0)
867# define DP_CEC_SNOOPING_ENABLE (1 << 1)
868
869#define DP_CEC_RX_MESSAGE_INFO 0x3002
870# define DP_CEC_RX_MESSAGE_LEN_MASK (0xf << 0)
871# define DP_CEC_RX_MESSAGE_LEN_SHIFT 0
872# define DP_CEC_RX_MESSAGE_HPD_STATE (1 << 4)
873# define DP_CEC_RX_MESSAGE_HPD_LOST (1 << 5)
874# define DP_CEC_RX_MESSAGE_ACKED (1 << 6)
875# define DP_CEC_RX_MESSAGE_ENDED (1 << 7)
876
877#define DP_CEC_TX_MESSAGE_INFO 0x3003
878# define DP_CEC_TX_MESSAGE_LEN_MASK (0xf << 0)
879# define DP_CEC_TX_MESSAGE_LEN_SHIFT 0
880# define DP_CEC_TX_RETRY_COUNT_MASK (0x7 << 4)
881# define DP_CEC_TX_RETRY_COUNT_SHIFT 4
882# define DP_CEC_TX_MESSAGE_SEND (1 << 7)
883
884#define DP_CEC_TUNNELING_IRQ_FLAGS 0x3004
885# define DP_CEC_RX_MESSAGE_INFO_VALID (1 << 0)
886# define DP_CEC_RX_MESSAGE_OVERFLOW (1 << 1)
887# define DP_CEC_TX_MESSAGE_SENT (1 << 4)
888# define DP_CEC_TX_LINE_ERROR (1 << 5)
889# define DP_CEC_TX_ADDRESS_NACK_ERROR (1 << 6)
890# define DP_CEC_TX_DATA_NACK_ERROR (1 << 7)
891
892#define DP_CEC_LOGICAL_ADDRESS_MASK 0x300E /* 0x300F word */
893# define DP_CEC_LOGICAL_ADDRESS_0 (1 << 0)
894# define DP_CEC_LOGICAL_ADDRESS_1 (1 << 1)
895# define DP_CEC_LOGICAL_ADDRESS_2 (1 << 2)
896# define DP_CEC_LOGICAL_ADDRESS_3 (1 << 3)
897# define DP_CEC_LOGICAL_ADDRESS_4 (1 << 4)
898# define DP_CEC_LOGICAL_ADDRESS_5 (1 << 5)
899# define DP_CEC_LOGICAL_ADDRESS_6 (1 << 6)
900# define DP_CEC_LOGICAL_ADDRESS_7 (1 << 7)
901#define DP_CEC_LOGICAL_ADDRESS_MASK_2 0x300F /* 0x300E word */
902# define DP_CEC_LOGICAL_ADDRESS_8 (1 << 0)
903# define DP_CEC_LOGICAL_ADDRESS_9 (1 << 1)
904# define DP_CEC_LOGICAL_ADDRESS_10 (1 << 2)
905# define DP_CEC_LOGICAL_ADDRESS_11 (1 << 3)
906# define DP_CEC_LOGICAL_ADDRESS_12 (1 << 4)
907# define DP_CEC_LOGICAL_ADDRESS_13 (1 << 5)
908# define DP_CEC_LOGICAL_ADDRESS_14 (1 << 6)
909# define DP_CEC_LOGICAL_ADDRESS_15 (1 << 7)
910
911#define DP_CEC_RX_MESSAGE_BUFFER 0x3010
912#define DP_CEC_TX_MESSAGE_BUFFER 0x3020
913#define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10
914
915#define DP_AUX_HDCP_BKSV 0x68000
916#define DP_AUX_HDCP_RI_PRIME 0x68005
917#define DP_AUX_HDCP_AKSV 0x68007
918#define DP_AUX_HDCP_AN 0x6800C
919#define DP_AUX_HDCP_V_PRIME(h) (0x68014 + h * 4)
920#define DP_AUX_HDCP_BCAPS 0x68028
921# define DP_BCAPS_REPEATER_PRESENT BIT(1)
922# define DP_BCAPS_HDCP_CAPABLE BIT(0)
923#define DP_AUX_HDCP_BSTATUS 0x68029
924# define DP_BSTATUS_REAUTH_REQ BIT(3)
925# define DP_BSTATUS_LINK_FAILURE BIT(2)
926# define DP_BSTATUS_R0_PRIME_READY BIT(1)
927# define DP_BSTATUS_READY BIT(0)
928#define DP_AUX_HDCP_BINFO 0x6802A
929#define DP_AUX_HDCP_KSV_FIFO 0x6802C
930#define DP_AUX_HDCP_AINFO 0x6803B
931
932/* DP HDCP2.2 parameter offsets in DPCD address space */
933#define DP_HDCP_2_2_REG_RTX_OFFSET 0x69000
934#define DP_HDCP_2_2_REG_TXCAPS_OFFSET 0x69008
935#define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B
936#define DP_HDCP_2_2_REG_RRX_OFFSET 0x69215
937#define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D
938#define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET 0x69220
939#define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET 0x692A0
940#define DP_HDCP_2_2_REG_M_OFFSET 0x692B0
941#define DP_HDCP_2_2_REG_HPRIME_OFFSET 0x692C0
942#define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 0x692E0
943#define DP_HDCP_2_2_REG_RN_OFFSET 0x692F0
944#define DP_HDCP_2_2_REG_LPRIME_OFFSET 0x692F8
945#define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET 0x69318
946#define DP_HDCP_2_2_REG_RIV_OFFSET 0x69328
947#define DP_HDCP_2_2_REG_RXINFO_OFFSET 0x69330
948#define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET 0x69332
949#define DP_HDCP_2_2_REG_VPRIME_OFFSET 0x69335
950#define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET 0x69345
951#define DP_HDCP_2_2_REG_V_OFFSET 0x693E0
952#define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 0x693F0
953#define DP_HDCP_2_2_REG_K_OFFSET 0x693F3
954#define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET 0x693F5
955#define DP_HDCP_2_2_REG_MPRIME_OFFSET 0x69473
956#define DP_HDCP_2_2_REG_RXSTATUS_OFFSET 0x69493
957#define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494
958#define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518
959
960/* DP HDCP message start offsets in DPCD address space */
961#define DP_HDCP_2_2_AKE_INIT_OFFSET DP_HDCP_2_2_REG_RTX_OFFSET
962#define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET
963#define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKPUB_KM_OFFSET
964#define DP_HDCP_2_2_AKE_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET
965#define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET DP_HDCP_2_2_REG_HPRIME_OFFSET
966#define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET \
967 DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET
968#define DP_HDCP_2_2_LC_INIT_OFFSET DP_HDCP_2_2_REG_RN_OFFSET
969#define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET DP_HDCP_2_2_REG_LPRIME_OFFSET
970#define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET DP_HDCP_2_2_REG_EDKEY_KS_OFFSET
971#define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET DP_HDCP_2_2_REG_RXINFO_OFFSET
972#define DP_HDCP_2_2_REP_SEND_ACK_OFFSET DP_HDCP_2_2_REG_V_OFFSET
973#define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET
974#define DP_HDCP_2_2_REP_STREAM_READY_OFFSET DP_HDCP_2_2_REG_MPRIME_OFFSET
975
976#define HDCP_2_2_DP_RXSTATUS_LEN 1
977#define HDCP_2_2_DP_RXSTATUS_READY(x) ((x) & BIT(0))
978#define HDCP_2_2_DP_RXSTATUS_H_PRIME(x) ((x) & BIT(1))
979#define HDCP_2_2_DP_RXSTATUS_PAIRING(x) ((x) & BIT(2))
980#define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3))
981#define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x) ((x) & BIT(4))
982
983/* DP 1.2 Sideband message defines */
984/* peer device type - DP 1.2a Table 2-92 */
985#define DP_PEER_DEVICE_NONE 0x0
986#define DP_PEER_DEVICE_SOURCE_OR_SST 0x1
987#define DP_PEER_DEVICE_MST_BRANCHING 0x2
988#define DP_PEER_DEVICE_SST_SINK 0x3
989#define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4
990
991/* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */
992#define DP_GET_MSG_TRANSACTION_VERSION 0x00 /* DP 1.3 */
993#define DP_LINK_ADDRESS 0x01
994#define DP_CONNECTION_STATUS_NOTIFY 0x02
995#define DP_ENUM_PATH_RESOURCES 0x10
996#define DP_ALLOCATE_PAYLOAD 0x11
997#define DP_QUERY_PAYLOAD 0x12
998#define DP_RESOURCE_STATUS_NOTIFY 0x13
999#define DP_CLEAR_PAYLOAD_ID_TABLE 0x14
1000#define DP_REMOTE_DPCD_READ 0x20
1001#define DP_REMOTE_DPCD_WRITE 0x21
1002#define DP_REMOTE_I2C_READ 0x22
1003#define DP_REMOTE_I2C_WRITE 0x23
1004#define DP_POWER_UP_PHY 0x24
1005#define DP_POWER_DOWN_PHY 0x25
1006#define DP_SINK_EVENT_NOTIFY 0x30
1007#define DP_QUERY_STREAM_ENC_STATUS 0x38
1008
1009/* DP 1.2 MST sideband reply types */
1010#define DP_SIDEBAND_REPLY_ACK 0x00
1011#define DP_SIDEBAND_REPLY_NAK 0x01
1012
1013/* DP 1.2 MST sideband nak reasons - table 2.84 */
1014#define DP_NAK_WRITE_FAILURE 0x01
1015#define DP_NAK_INVALID_READ 0x02
1016#define DP_NAK_CRC_FAILURE 0x03
1017#define DP_NAK_BAD_PARAM 0x04
1018#define DP_NAK_DEFER 0x05
1019#define DP_NAK_LINK_FAILURE 0x06
1020#define DP_NAK_NO_RESOURCES 0x07
1021#define DP_NAK_DPCD_FAIL 0x08
1022#define DP_NAK_I2C_NAK 0x09
1023#define DP_NAK_ALLOCATE_FAIL 0x0a
1024
1025#define MODE_I2C_START 1
1026#define MODE_I2C_WRITE 2
1027#define MODE_I2C_READ 4
1028#define MODE_I2C_STOP 8
1029
1030/* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */
1031#define DP_MST_PHYSICAL_PORT_0 0
1032#define DP_MST_LOGICAL_PORT_0 8
1033
1034#define DP_LINK_STATUS_SIZE 6
1035bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
1036 int lane_count);
1037bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
1038 int lane_count);
1039u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
1040 int lane);
1041u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
1042 int lane);
1043
1044#define DP_BRANCH_OUI_HEADER_SIZE 0xc
1045#define DP_RECEIVER_CAP_SIZE 0xf
1046#define DP_DSC_RECEIVER_CAP_SIZE 0xf
1047#define EDP_PSR_RECEIVER_CAP_SIZE 2
1048#define EDP_DISPLAY_CTL_CAP_SIZE 3
1049
1050void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
1051void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
1052
1053u8 drm_dp_link_rate_to_bw_code(int link_rate);
1054int drm_dp_bw_code_to_link_rate(u8 link_bw);
1055
1056#define DP_SDP_AUDIO_TIMESTAMP 0x01
1057#define DP_SDP_AUDIO_STREAM 0x02
1058#define DP_SDP_EXTENSION 0x04 /* DP 1.1 */
1059#define DP_SDP_AUDIO_COPYMANAGEMENT 0x05 /* DP 1.2 */
1060#define DP_SDP_ISRC 0x06 /* DP 1.2 */
1061#define DP_SDP_VSC 0x07 /* DP 1.2 */
1062#define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i)) /* 0-7, DP 1.3 */
1063#define DP_SDP_PPS 0x10 /* DP 1.4 */
1064#define DP_SDP_VSC_EXT_VESA 0x20 /* DP 1.4 */
1065#define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */
1066/* 0x80+ CEA-861 infoframe types */
1067
1068/**
1069 * struct dp_sdp_header - DP secondary data packet header
1070 * @HB0: Secondary Data Packet ID
1071 * @HB1: Secondary Data Packet Type
1072 * @HB2: Secondary Data Packet Specific header, Byte 0
1073 * @HB3: Secondary Data packet Specific header, Byte 1
1074 */
1075struct dp_sdp_header {
1076 u8 HB0;
1077 u8 HB1;
1078 u8 HB2;
1079 u8 HB3;
1080} __packed;
1081
1082#define EDP_SDP_HEADER_REVISION_MASK 0x1F
1083#define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
1084#define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F
1085
1086struct edp_vsc_psr {
1087 struct dp_sdp_header sdp_header;
1088 u8 DB0; /* Stereo Interface */
1089 u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */
1090 u8 DB2; /* CRC value bits 7:0 of the R or Cr component */
1091 u8 DB3; /* CRC value bits 15:8 of the R or Cr component */
1092 u8 DB4; /* CRC value bits 7:0 of the G or Y component */
1093 u8 DB5; /* CRC value bits 15:8 of the G or Y component */
1094 u8 DB6; /* CRC value bits 7:0 of the B or Cb component */
1095 u8 DB7; /* CRC value bits 15:8 of the B or Cb component */
1096 u8 DB8_31[24]; /* Reserved */
1097} __packed;
1098
1099#define EDP_VSC_PSR_STATE_ACTIVE (1<<0)
1100#define EDP_VSC_PSR_UPDATE_RFB (1<<1)
1101#define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
1102
1103int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
1104
1105static inline int
1106drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1107{
1108 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
1109}
1110
1111static inline u8
1112drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1113{
1114 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
1115}
1116
1117static inline bool
1118drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1119{
1120 return dpcd[DP_DPCD_REV] >= 0x11 &&
1121 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);
1122}
1123
1124static inline bool
1125drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1126{
1127 return dpcd[DP_DPCD_REV] >= 0x12 &&
1128 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED;
1129}
1130
1131static inline bool
1132drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1133{
1134 return dpcd[DP_DPCD_REV] >= 0x14 &&
1135 dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED;
1136}
1137
1138static inline u8
1139drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1140{
1141 return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 :
1142 DP_TRAINING_PATTERN_MASK;
1143}
1144
1145static inline bool
1146drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1147{
1148 return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT;
1149}
1150
1151/* DP/eDP DSC support */
1152u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
1153 bool is_edp);
1154u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
1155int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE],
1156 u8 dsc_bpc[3]);
1157
1158static inline bool
1159drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1160{
1161 return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] &
1162 DP_DSC_DECOMPRESSION_IS_SUPPORTED;
1163}
1164
1165static inline u16
1166drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1167{
1168 return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] |
1169 (dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] &
1170 DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK <<
1171 DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT);
1172}
1173
1174static inline u32
1175drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1176{
1177 /* Max Slicewidth = Number of Pixels * 320 */
1178 return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] *
1179 DP_DSC_SLICE_WIDTH_MULTIPLIER;
1180}
1181
1182/* Forward Error Correction Support on DP 1.4 */
1183static inline bool
1184drm_dp_sink_supports_fec(const u8 fec_capable)
1185{
1186 return fec_capable & DP_FEC_CAPABLE;
1187}
1188
1189/*
1190 * DisplayPort AUX channel
1191 */
1192
1193/**
1194 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction
1195 * @address: address of the (first) register to access
1196 * @request: contains the type of transaction (see DP_AUX_* macros)
1197 * @reply: upon completion, contains the reply type of the transaction
1198 * @buffer: pointer to a transmission or reception buffer
1199 * @size: size of @buffer
1200 */
1201struct drm_dp_aux_msg {
1202 unsigned int address;
1203 u8 request;
1204 u8 reply;
1205 void *buffer;
1206 size_t size;
1207};
1208
1209struct cec_adapter;
1210struct edid;
1211
1212/**
1213 * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX
1214 * @lock: mutex protecting this struct
1215 * @adap: the CEC adapter for CEC-Tunneling-over-AUX support.
1216 * @name: name of the CEC adapter
1217 * @parent: parent device of the CEC adapter
1218 * @unregister_work: unregister the CEC adapter
1219 */
1220struct drm_dp_aux_cec {
1221 struct mutex lock;
1222 struct cec_adapter *adap;
1223 const char *name;
1224 struct device *parent;
1225 struct delayed_work unregister_work;
1226};
1227
1228/**
1229 * struct drm_dp_aux - DisplayPort AUX channel
1230 * @name: user-visible name of this AUX channel and the I2C-over-AUX adapter
1231 * @ddc: I2C adapter that can be used for I2C-over-AUX communication
1232 * @dev: pointer to struct device that is the parent for this AUX channel
1233 * @crtc: backpointer to the crtc that is currently using this AUX channel
1234 * @hw_mutex: internal mutex used for locking transfers
1235 * @crc_work: worker that captures CRCs for each frame
1236 * @crc_count: counter of captured frame CRCs
1237 * @transfer: transfers a message representing a single AUX transaction
1238 *
1239 * The .dev field should be set to a pointer to the device that implements
1240 * the AUX channel.
1241 *
1242 * The .name field may be used to specify the name of the I2C adapter. If set to
1243 * NULL, dev_name() of .dev will be used.
1244 *
1245 * Drivers provide a hardware-specific implementation of how transactions
1246 * are executed via the .transfer() function. A pointer to a drm_dp_aux_msg
1247 * structure describing the transaction is passed into this function. Upon
1248 * success, the implementation should return the number of payload bytes
1249 * that were transferred, or a negative error-code on failure. Helpers
1250 * propagate errors from the .transfer() function, with the exception of
1251 * the -EBUSY error, which causes a transaction to be retried. On a short,
1252 * helpers will return -EPROTO to make it simpler to check for failure.
1253 *
1254 * An AUX channel can also be used to transport I2C messages to a sink. A
1255 * typical application of that is to access an EDID that's present in the
1256 * sink device. The .transfer() function can also be used to execute such
1257 * transactions. The drm_dp_aux_register() function registers an I2C
1258 * adapter that can be passed to drm_probe_ddc(). Upon removal, drivers
1259 * should call drm_dp_aux_unregister() to remove the I2C adapter.
1260 * The I2C adapter uses long transfers by default; if a partial response is
1261 * received, the adapter will drop down to the size given by the partial
1262 * response for this transaction only.
1263 *
1264 * Note that the aux helper code assumes that the .transfer() function
1265 * only modifies the reply field of the drm_dp_aux_msg structure. The
1266 * retry logic and i2c helpers assume this is the case.
1267 */
1268struct drm_dp_aux {
1269 const char *name;
1270 struct i2c_adapter ddc;
1271 struct device *dev;
1272 struct drm_crtc *crtc;
1273 struct mutex hw_mutex;
1274 struct work_struct crc_work;
1275 u8 crc_count;
1276 ssize_t (*transfer)(struct drm_dp_aux *aux,
1277 struct drm_dp_aux_msg *msg);
1278 /**
1279 * @i2c_nack_count: Counts I2C NACKs, used for DP validation.
1280 */
1281 unsigned i2c_nack_count;
1282 /**
1283 * @i2c_defer_count: Counts I2C DEFERs, used for DP validation.
1284 */
1285 unsigned i2c_defer_count;
1286 /**
1287 * @cec: struct containing fields used for CEC-Tunneling-over-AUX.
1288 */
1289 struct drm_dp_aux_cec cec;
1290};
1291
1292ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
1293 void *buffer, size_t size);
1294ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
1295 void *buffer, size_t size);
1296
1297/**
1298 * drm_dp_dpcd_readb() - read a single byte from the DPCD
1299 * @aux: DisplayPort AUX channel
1300 * @offset: address of the register to read
1301 * @valuep: location where the value of the register will be stored
1302 *
1303 * Returns the number of bytes transferred (1) on success, or a negative
1304 * error code on failure.
1305 */
1306static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux,
1307 unsigned int offset, u8 *valuep)
1308{
1309 return drm_dp_dpcd_read(aux, offset, valuep, 1);
1310}
1311
1312/**
1313 * drm_dp_dpcd_writeb() - write a single byte to the DPCD
1314 * @aux: DisplayPort AUX channel
1315 * @offset: address of the register to write
1316 * @value: value to write to the register
1317 *
1318 * Returns the number of bytes transferred (1) on success, or a negative
1319 * error code on failure.
1320 */
1321static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux,
1322 unsigned int offset, u8 value)
1323{
1324 return drm_dp_dpcd_write(aux, offset, &value, 1);
1325}
1326
1327int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
1328 u8 status[DP_LINK_STATUS_SIZE]);
1329
1330/*
1331 * DisplayPort link
1332 */
1333#define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0)
1334
1335struct drm_dp_link {
1336 unsigned char revision;
1337 unsigned int rate;
1338 unsigned int num_lanes;
1339 unsigned long capabilities;
1340};
1341
1342int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link);
1343int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link);
1344int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link);
1345int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
1346int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1347 const u8 port_cap[4]);
1348int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1349 const u8 port_cap[4]);
1350int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]);
1351void drm_dp_downstream_debug(struct seq_file *m, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1352 const u8 port_cap[4], struct drm_dp_aux *aux);
1353
1354void drm_dp_aux_init(struct drm_dp_aux *aux);
1355int drm_dp_aux_register(struct drm_dp_aux *aux);
1356void drm_dp_aux_unregister(struct drm_dp_aux *aux);
1357
1358int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc);
1359int drm_dp_stop_crc(struct drm_dp_aux *aux);
1360
1361struct drm_dp_dpcd_ident {
1362 u8 oui[3];
1363 u8 device_id[6];
1364 u8 hw_rev;
1365 u8 sw_major_rev;
1366 u8 sw_minor_rev;
1367} __packed;
1368
1369/**
1370 * struct drm_dp_desc - DP branch/sink device descriptor
1371 * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch).
1372 * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks.
1373 */
1374struct drm_dp_desc {
1375 struct drm_dp_dpcd_ident ident;
1376 u32 quirks;
1377};
1378
1379int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
1380 bool is_branch);
1381
1382/**
1383 * enum drm_dp_quirk - Display Port sink/branch device specific quirks
1384 *
1385 * Display Port sink and branch devices in the wild have a variety of bugs, try
1386 * to collect them here. The quirks are shared, but it's up to the drivers to
1387 * implement workarounds for them.
1388 */
1389enum drm_dp_quirk {
1390 /**
1391 * @DP_DPCD_QUIRK_CONSTANT_N:
1392 *
1393 * The device requires main link attributes Mvid and Nvid to be limited
1394 * to 16 bits. So will give a constant value (0x8000) for compatability.
1395 */
1396 DP_DPCD_QUIRK_CONSTANT_N,
1397 /**
1398 * @DP_DPCD_QUIRK_NO_PSR:
1399 *
1400 * The device does not support PSR even if reports that it supports or
1401 * driver still need to implement proper handling for such device.
1402 */
1403 DP_DPCD_QUIRK_NO_PSR,
1404};
1405
1406/**
1407 * drm_dp_has_quirk() - does the DP device have a specific quirk
1408 * @desc: Device decriptor filled by drm_dp_read_desc()
1409 * @quirk: Quirk to query for
1410 *
1411 * Return true if DP device identified by @desc has @quirk.
1412 */
1413static inline bool
1414drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk)
1415{
1416 return desc->quirks & BIT(quirk);
1417}
1418
1419#ifdef CONFIG_DRM_DP_CEC
1420void drm_dp_cec_irq(struct drm_dp_aux *aux);
1421void drm_dp_cec_register_connector(struct drm_dp_aux *aux, const char *name,
1422 struct device *parent);
1423void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux);
1424void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid);
1425void drm_dp_cec_unset_edid(struct drm_dp_aux *aux);
1426#else
1427static inline void drm_dp_cec_irq(struct drm_dp_aux *aux)
1428{
1429}
1430
1431static inline void drm_dp_cec_register_connector(struct drm_dp_aux *aux,
1432 const char *name,
1433 struct device *parent)
1434{
1435}
1436
1437static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux)
1438{
1439}
1440
1441static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux,
1442 const struct edid *edid)
1443{
1444}
1445
1446static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
1447{
1448}
1449
1450#endif
1451
1452#endif /* _DRM_DP_HELPER_H_ */
1453