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1/*
2 * Copyright (c) 2016-2017 Linaro Ltd.
3 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */
10
11#ifndef __DTS_HI3660_CLOCK_H
12#define __DTS_HI3660_CLOCK_H
13
14/* fixed rate clocks */
15#define HI3660_CLKIN_SYS 0
16#define HI3660_CLKIN_REF 1
17#define HI3660_CLK_FLL_SRC 2
18#define HI3660_CLK_PPLL0 3
19#define HI3660_CLK_PPLL1 4
20#define HI3660_CLK_PPLL2 5
21#define HI3660_CLK_PPLL3 6
22#define HI3660_CLK_SCPLL 7
23#define HI3660_PCLK 8
24#define HI3660_CLK_UART0_DBG 9
25#define HI3660_CLK_UART6 10
26#define HI3660_OSC32K 11
27#define HI3660_OSC19M 12
28#define HI3660_CLK_480M 13
29#define HI3660_CLK_INV 14
30
31/* clk in crgctrl */
32#define HI3660_FACTOR_UART3 15
33#define HI3660_CLK_FACTOR_MMC 16
34#define HI3660_CLK_GATE_I2C0 17
35#define HI3660_CLK_GATE_I2C1 18
36#define HI3660_CLK_GATE_I2C2 19
37#define HI3660_CLK_GATE_I2C6 20
38#define HI3660_CLK_DIV_SYSBUS 21
39#define HI3660_CLK_DIV_320M 22
40#define HI3660_CLK_DIV_A53 23
41#define HI3660_CLK_GATE_SPI0 24
42#define HI3660_CLK_GATE_SPI2 25
43#define HI3660_PCIEPHY_REF 26
44#define HI3660_CLK_ABB_USB 27
45#define HI3660_HCLK_GATE_SDIO0 28
46#define HI3660_HCLK_GATE_SD 29
47#define HI3660_CLK_GATE_AOMM 30
48#define HI3660_PCLK_GPIO0 31
49#define HI3660_PCLK_GPIO1 32
50#define HI3660_PCLK_GPIO2 33
51#define HI3660_PCLK_GPIO3 34
52#define HI3660_PCLK_GPIO4 35
53#define HI3660_PCLK_GPIO5 36
54#define HI3660_PCLK_GPIO6 37
55#define HI3660_PCLK_GPIO7 38
56#define HI3660_PCLK_GPIO8 39
57#define HI3660_PCLK_GPIO9 40
58#define HI3660_PCLK_GPIO10 41
59#define HI3660_PCLK_GPIO11 42
60#define HI3660_PCLK_GPIO12 43
61#define HI3660_PCLK_GPIO13 44
62#define HI3660_PCLK_GPIO14 45
63#define HI3660_PCLK_GPIO15 46
64#define HI3660_PCLK_GPIO16 47
65#define HI3660_PCLK_GPIO17 48
66#define HI3660_PCLK_GPIO18 49
67#define HI3660_PCLK_GPIO19 50
68#define HI3660_PCLK_GPIO20 51
69#define HI3660_PCLK_GPIO21 52
70#define HI3660_CLK_GATE_SPI3 53
71#define HI3660_CLK_GATE_I2C7 54
72#define HI3660_CLK_GATE_I2C3 55
73#define HI3660_CLK_GATE_SPI1 56
74#define HI3660_CLK_GATE_UART1 57
75#define HI3660_CLK_GATE_UART2 58
76#define HI3660_CLK_GATE_UART4 59
77#define HI3660_CLK_GATE_UART5 60
78#define HI3660_CLK_GATE_I2C4 61
79#define HI3660_CLK_GATE_DMAC 62
80#define HI3660_PCLK_GATE_DSS 63
81#define HI3660_ACLK_GATE_DSS 64
82#define HI3660_CLK_GATE_LDI1 65
83#define HI3660_CLK_GATE_LDI0 66
84#define HI3660_CLK_GATE_VIVOBUS 67
85#define HI3660_CLK_GATE_EDC0 68
86#define HI3660_CLK_GATE_TXDPHY0_CFG 69
87#define HI3660_CLK_GATE_TXDPHY0_REF 70
88#define HI3660_CLK_GATE_TXDPHY1_CFG 71
89#define HI3660_CLK_GATE_TXDPHY1_REF 72
90#define HI3660_ACLK_GATE_USB3OTG 73
91#define HI3660_CLK_GATE_SPI4 74
92#define HI3660_CLK_GATE_SD 75
93#define HI3660_CLK_GATE_SDIO0 76
94#define HI3660_CLK_GATE_UFS_SUBSYS 77
95#define HI3660_PCLK_GATE_DSI0 78
96#define HI3660_PCLK_GATE_DSI1 79
97#define HI3660_ACLK_GATE_PCIE 80
98#define HI3660_PCLK_GATE_PCIE_SYS 81
99#define HI3660_CLK_GATE_PCIEAUX 82
100#define HI3660_PCLK_GATE_PCIE_PHY 83
101#define HI3660_CLK_ANDGT_LDI0 84
102#define HI3660_CLK_ANDGT_LDI1 85
103#define HI3660_CLK_ANDGT_EDC0 86
104#define HI3660_CLK_GATE_UFSPHY_GT 87
105#define HI3660_CLK_ANDGT_MMC 88
106#define HI3660_CLK_ANDGT_SD 89
107#define HI3660_CLK_A53HPM_ANDGT 90
108#define HI3660_CLK_ANDGT_SDIO 91
109#define HI3660_CLK_ANDGT_UART0 92
110#define HI3660_CLK_ANDGT_UART1 93
111#define HI3660_CLK_ANDGT_UARTH 94
112#define HI3660_CLK_ANDGT_SPI 95
113#define HI3660_CLK_VIVOBUS_ANDGT 96
114#define HI3660_CLK_AOMM_ANDGT 97
115#define HI3660_CLK_320M_PLL_GT 98
116#define HI3660_AUTODIV_EMMC0BUS 99
117#define HI3660_AUTODIV_SYSBUS 100
118#define HI3660_CLK_GATE_UFSPHY_CFG 101
119#define HI3660_CLK_GATE_UFSIO_REF 102
120#define HI3660_CLK_MUX_SYSBUS 103
121#define HI3660_CLK_MUX_UART0 104
122#define HI3660_CLK_MUX_UART1 105
123#define HI3660_CLK_MUX_UARTH 106
124#define HI3660_CLK_MUX_SPI 107
125#define HI3660_CLK_MUX_I2C 108
126#define HI3660_CLK_MUX_MMC_PLL 109
127#define HI3660_CLK_MUX_LDI1 110
128#define HI3660_CLK_MUX_LDI0 111
129#define HI3660_CLK_MUX_SD_PLL 112
130#define HI3660_CLK_MUX_SD_SYS 113
131#define HI3660_CLK_MUX_EDC0 114
132#define HI3660_CLK_MUX_SDIO_SYS 115
133#define HI3660_CLK_MUX_SDIO_PLL 116
134#define HI3660_CLK_MUX_VIVOBUS 117
135#define HI3660_CLK_MUX_A53HPM 118
136#define HI3660_CLK_MUX_320M 119
137#define HI3660_CLK_MUX_IOPERI 120
138#define HI3660_CLK_DIV_UART0 121
139#define HI3660_CLK_DIV_UART1 122
140#define HI3660_CLK_DIV_UARTH 123
141#define HI3660_CLK_DIV_MMC 124
142#define HI3660_CLK_DIV_SD 125
143#define HI3660_CLK_DIV_EDC0 126
144#define HI3660_CLK_DIV_LDI0 127
145#define HI3660_CLK_DIV_SDIO 128
146#define HI3660_CLK_DIV_LDI1 129
147#define HI3660_CLK_DIV_SPI 130
148#define HI3660_CLK_DIV_VIVOBUS 131
149#define HI3660_CLK_DIV_I2C 132
150#define HI3660_CLK_DIV_UFSPHY 133
151#define HI3660_CLK_DIV_CFGBUS 134
152#define HI3660_CLK_DIV_MMC0BUS 135
153#define HI3660_CLK_DIV_MMC1BUS 136
154#define HI3660_CLK_DIV_UFSPERI 137
155#define HI3660_CLK_DIV_AOMM 138
156#define HI3660_CLK_DIV_IOPERI 139
157#define HI3660_VENC_VOLT_HOLD 140
158#define HI3660_PERI_VOLT_HOLD 141
159#define HI3660_CLK_GATE_VENC 142
160#define HI3660_CLK_GATE_VDEC 143
161#define HI3660_CLK_ANDGT_VENC 144
162#define HI3660_CLK_ANDGT_VDEC 145
163#define HI3660_CLK_MUX_VENC 146
164#define HI3660_CLK_MUX_VDEC 147
165#define HI3660_CLK_DIV_VENC 148
166#define HI3660_CLK_DIV_VDEC 149
167#define HI3660_CLK_FAC_ISP_SNCLK 150
168#define HI3660_CLK_GATE_ISP_SNCLK0 151
169#define HI3660_CLK_GATE_ISP_SNCLK1 152
170#define HI3660_CLK_GATE_ISP_SNCLK2 153
171#define HI3660_CLK_ANGT_ISP_SNCLK 154
172#define HI3660_CLK_MUX_ISP_SNCLK 155
173#define HI3660_CLK_DIV_ISP_SNCLK 156
174
175/* clk in pmuctrl */
176#define HI3660_GATE_ABB_192 0
177
178/* clk in pctrl */
179#define HI3660_GATE_UFS_TCXO_EN 0
180#define HI3660_GATE_USB_TCXO_EN 1
181
182/* clk in sctrl */
183#define HI3660_PCLK_AO_GPIO0 0
184#define HI3660_PCLK_AO_GPIO1 1
185#define HI3660_PCLK_AO_GPIO2 2
186#define HI3660_PCLK_AO_GPIO3 3
187#define HI3660_PCLK_AO_GPIO4 4
188#define HI3660_PCLK_AO_GPIO5 5
189#define HI3660_PCLK_AO_GPIO6 6
190#define HI3660_PCLK_GATE_MMBUF 7
191#define HI3660_CLK_GATE_DSS_AXI_MM 8
192#define HI3660_PCLK_MMBUF_ANDGT 9
193#define HI3660_CLK_MMBUF_PLL_ANDGT 10
194#define HI3660_CLK_FLL_MMBUF_ANDGT 11
195#define HI3660_CLK_SYS_MMBUF_ANDGT 12
196#define HI3660_CLK_GATE_PCIEPHY_GT 13
197#define HI3660_ACLK_MUX_MMBUF 14
198#define HI3660_CLK_SW_MMBUF 15
199#define HI3660_CLK_DIV_AOBUS 16
200#define HI3660_PCLK_DIV_MMBUF 17
201#define HI3660_ACLK_DIV_MMBUF 18
202#define HI3660_CLK_DIV_PCIEPHY 19
203
204/* clk in iomcu */
205#define HI3660_CLK_I2C0_IOMCU 0
206#define HI3660_CLK_I2C1_IOMCU 1
207#define HI3660_CLK_I2C2_IOMCU 2
208#define HI3660_CLK_I2C6_IOMCU 3
209#define HI3660_CLK_IOMCU_PERI0 4
210
211/* clk in stub clock */
212#define HI3660_CLK_STUB_CLUSTER0 0
213#define HI3660_CLK_STUB_CLUSTER1 1
214#define HI3660_CLK_STUB_GPU 2
215#define HI3660_CLK_STUB_DDR 3
216#define HI3660_CLK_STUB_NUM 4
217
218#endif /* __DTS_HI3660_CLOCK_H */
219

Warning: That file was not part of the compilation database. It may have many parsing errors.