| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Device Tree binding constants for HiSilicon Hi3670 SoC |
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| 4 | * |
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| 5 | * Copyright (c) 2001-2021, Huawei Tech. Co., Ltd. |
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| 6 | * Copyright (c) 2018 Linaro Ltd. |
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| 7 | */ |
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| 8 | |
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| 9 | #ifndef __DT_BINDINGS_CLOCK_HI3670_H |
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| 10 | #define __DT_BINDINGS_CLOCK_HI3670_H |
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| 11 | |
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| 12 | /* clk in stub clock */ |
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| 13 | #define HI3670_CLK_STUB_CLUSTER0 0 |
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| 14 | #define HI3670_CLK_STUB_CLUSTER1 1 |
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| 15 | #define HI3670_CLK_STUB_GPU 2 |
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| 16 | #define HI3670_CLK_STUB_DDR 3 |
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| 17 | #define HI3670_CLK_STUB_DDR_VOTE 4 |
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| 18 | #define HI3670_CLK_STUB_DDR_LIMIT 5 |
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| 19 | #define HI3670_CLK_STUB_NUM 6 |
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| 20 | |
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| 21 | /* clk in crg clock */ |
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| 22 | #define HI3670_CLKIN_SYS 0 |
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| 23 | #define HI3670_CLKIN_REF 1 |
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| 24 | #define HI3670_CLK_FLL_SRC 2 |
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| 25 | #define HI3670_CLK_PPLL0 3 |
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| 26 | #define HI3670_CLK_PPLL1 4 |
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| 27 | #define HI3670_CLK_PPLL2 5 |
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| 28 | #define HI3670_CLK_PPLL3 6 |
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| 29 | #define HI3670_CLK_PPLL4 7 |
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| 30 | #define HI3670_CLK_PPLL6 8 |
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| 31 | #define HI3670_CLK_PPLL7 9 |
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| 32 | #define HI3670_CLK_PPLL_PCIE 10 |
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| 33 | #define HI3670_CLK_PCIEPLL_REV 11 |
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| 34 | #define HI3670_CLK_SCPLL 12 |
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| 35 | #define HI3670_PCLK 13 |
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| 36 | #define HI3670_CLK_UART0_DBG 14 |
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| 37 | #define HI3670_CLK_UART6 15 |
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| 38 | #define HI3670_OSC32K 16 |
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| 39 | #define HI3670_OSC19M 17 |
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| 40 | #define HI3670_CLK_480M 18 |
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| 41 | #define HI3670_CLK_INVALID 19 |
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| 42 | #define HI3670_CLK_DIV_SYSBUS 20 |
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| 43 | #define HI3670_CLK_FACTOR_MMC 21 |
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| 44 | #define HI3670_CLK_SD_SYS 22 |
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| 45 | #define HI3670_CLK_SDIO_SYS 23 |
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| 46 | #define HI3670_CLK_DIV_A53HPM 24 |
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| 47 | #define HI3670_CLK_DIV_320M 25 |
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| 48 | #define HI3670_PCLK_GATE_UART0 26 |
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| 49 | #define HI3670_CLK_FACTOR_UART0 27 |
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| 50 | #define HI3670_CLK_FACTOR_USB3PHY_PLL 28 |
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| 51 | #define HI3670_CLK_GATE_ABB_USB 29 |
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| 52 | #define HI3670_CLK_GATE_UFSPHY_REF 30 |
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| 53 | #define HI3670_ICS_VOLT_HIGH 31 |
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| 54 | #define HI3670_ICS_VOLT_MIDDLE 32 |
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| 55 | #define HI3670_VENC_VOLT_HOLD 33 |
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| 56 | #define HI3670_VDEC_VOLT_HOLD 34 |
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| 57 | #define HI3670_EDC_VOLT_HOLD 35 |
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| 58 | #define HI3670_CLK_ISP_SNCLK_FAC 36 |
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| 59 | #define HI3670_CLK_FACTOR_RXDPHY 37 |
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| 60 | #define HI3670_AUTODIV_SYSBUS 38 |
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| 61 | #define HI3670_AUTODIV_EMMC0BUS 39 |
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| 62 | #define HI3670_PCLK_ANDGT_MMC1_PCIE 40 |
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| 63 | #define HI3670_CLK_GATE_VCODECBUS_GT 41 |
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| 64 | #define HI3670_CLK_ANDGT_SD 42 |
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| 65 | #define HI3670_CLK_SD_SYS_GT 43 |
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| 66 | #define HI3670_CLK_ANDGT_SDIO 44 |
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| 67 | #define HI3670_CLK_SDIO_SYS_GT 45 |
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| 68 | #define HI3670_CLK_A53HPM_ANDGT 46 |
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| 69 | #define HI3670_CLK_320M_PLL_GT 47 |
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| 70 | #define HI3670_CLK_ANDGT_UARTH 48 |
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| 71 | #define HI3670_CLK_ANDGT_UARTL 49 |
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| 72 | #define HI3670_CLK_ANDGT_UART0 50 |
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| 73 | #define HI3670_CLK_ANDGT_SPI 51 |
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| 74 | #define HI3670_CLK_ANDGT_PCIEAXI 52 |
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| 75 | #define HI3670_CLK_DIV_AO_ASP_GT 53 |
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| 76 | #define HI3670_CLK_GATE_CSI_TRANS 54 |
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| 77 | #define HI3670_CLK_GATE_DSI_TRANS 55 |
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| 78 | #define HI3670_CLK_ANDGT_PTP 56 |
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| 79 | #define HI3670_CLK_ANDGT_OUT0 57 |
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| 80 | #define HI3670_CLK_ANDGT_OUT1 58 |
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| 81 | #define HI3670_CLKGT_DP_AUDIO_PLL_AO 59 |
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| 82 | #define HI3670_CLK_ANDGT_VDEC 60 |
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| 83 | #define HI3670_CLK_ANDGT_VENC 61 |
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| 84 | #define HI3670_CLK_ISP_SNCLK_ANGT 62 |
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| 85 | #define HI3670_CLK_ANDGT_RXDPHY 63 |
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| 86 | #define HI3670_CLK_ANDGT_ICS 64 |
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| 87 | #define HI3670_AUTODIV_DMABUS 65 |
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| 88 | #define HI3670_CLK_MUX_SYSBUS 66 |
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| 89 | #define HI3670_CLK_MUX_VCODECBUS 67 |
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| 90 | #define HI3670_CLK_MUX_SD_SYS 68 |
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| 91 | #define HI3670_CLK_MUX_SD_PLL 69 |
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| 92 | #define HI3670_CLK_MUX_SDIO_SYS 70 |
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| 93 | #define HI3670_CLK_MUX_SDIO_PLL 71 |
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| 94 | #define HI3670_CLK_MUX_A53HPM 72 |
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| 95 | #define HI3670_CLK_MUX_320M 73 |
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| 96 | #define HI3670_CLK_MUX_UARTH 74 |
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| 97 | #define HI3670_CLK_MUX_UARTL 75 |
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| 98 | #define HI3670_CLK_MUX_UART0 76 |
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| 99 | #define HI3670_CLK_MUX_I2C 77 |
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| 100 | #define HI3670_CLK_MUX_SPI 78 |
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| 101 | #define HI3670_CLK_MUX_PCIEAXI 79 |
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| 102 | #define HI3670_CLK_MUX_AO_ASP 80 |
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| 103 | #define HI3670_CLK_MUX_VDEC 81 |
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| 104 | #define HI3670_CLK_MUX_VENC 82 |
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| 105 | #define HI3670_CLK_ISP_SNCLK_MUX0 83 |
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| 106 | #define HI3670_CLK_ISP_SNCLK_MUX1 84 |
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| 107 | #define HI3670_CLK_ISP_SNCLK_MUX2 85 |
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| 108 | #define HI3670_CLK_MUX_RXDPHY_CFG 86 |
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| 109 | #define HI3670_CLK_MUX_ICS 87 |
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| 110 | #define HI3670_CLK_DIV_CFGBUS 88 |
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| 111 | #define HI3670_CLK_DIV_MMC0BUS 89 |
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| 112 | #define HI3670_CLK_DIV_MMC1BUS 90 |
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| 113 | #define HI3670_PCLK_DIV_MMC1_PCIE 91 |
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| 114 | #define HI3670_CLK_DIV_VCODECBUS 92 |
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| 115 | #define HI3670_CLK_DIV_SD 93 |
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| 116 | #define HI3670_CLK_DIV_SDIO 94 |
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| 117 | #define HI3670_CLK_DIV_UARTH 95 |
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| 118 | #define HI3670_CLK_DIV_UARTL 96 |
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| 119 | #define HI3670_CLK_DIV_UART0 97 |
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| 120 | #define HI3670_CLK_DIV_I2C 98 |
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| 121 | #define HI3670_CLK_DIV_SPI 99 |
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| 122 | #define HI3670_CLK_DIV_PCIEAXI 100 |
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| 123 | #define HI3670_CLK_DIV_AO_ASP 101 |
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| 124 | #define HI3670_CLK_DIV_CSI_TRANS 102 |
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| 125 | #define HI3670_CLK_DIV_DSI_TRANS 103 |
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| 126 | #define HI3670_CLK_DIV_PTP 104 |
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| 127 | #define HI3670_CLK_DIV_CLKOUT0_PLL 105 |
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| 128 | #define HI3670_CLK_DIV_CLKOUT1_PLL 106 |
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| 129 | #define HI3670_CLKDIV_DP_AUDIO_PLL_AO 107 |
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| 130 | #define HI3670_CLK_DIV_VDEC 108 |
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| 131 | #define HI3670_CLK_DIV_VENC 109 |
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| 132 | #define HI3670_CLK_ISP_SNCLK_DIV0 110 |
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| 133 | #define HI3670_CLK_ISP_SNCLK_DIV1 111 |
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| 134 | #define HI3670_CLK_ISP_SNCLK_DIV2 112 |
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| 135 | #define HI3670_CLK_DIV_ICS 113 |
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| 136 | #define HI3670_PPLL1_EN_ACPU 114 |
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| 137 | #define HI3670_PPLL2_EN_ACPU 115 |
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| 138 | #define HI3670_PPLL3_EN_ACPU 116 |
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| 139 | #define HI3670_PPLL1_GT_CPU 117 |
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| 140 | #define HI3670_PPLL2_GT_CPU 118 |
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| 141 | #define HI3670_PPLL3_GT_CPU 119 |
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| 142 | #define HI3670_CLK_GATE_PPLL2_MEDIA 120 |
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| 143 | #define HI3670_CLK_GATE_PPLL3_MEDIA 121 |
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| 144 | #define HI3670_CLK_GATE_PPLL4_MEDIA 122 |
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| 145 | #define HI3670_CLK_GATE_PPLL6_MEDIA 123 |
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| 146 | #define HI3670_CLK_GATE_PPLL7_MEDIA 124 |
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| 147 | #define HI3670_PCLK_GPIO0 125 |
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| 148 | #define HI3670_PCLK_GPIO1 126 |
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| 149 | #define HI3670_PCLK_GPIO2 127 |
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| 150 | #define HI3670_PCLK_GPIO3 128 |
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| 151 | #define HI3670_PCLK_GPIO4 129 |
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| 152 | #define HI3670_PCLK_GPIO5 130 |
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| 153 | #define HI3670_PCLK_GPIO6 131 |
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| 154 | #define HI3670_PCLK_GPIO7 132 |
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| 155 | #define HI3670_PCLK_GPIO8 133 |
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| 156 | #define HI3670_PCLK_GPIO9 134 |
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| 157 | #define HI3670_PCLK_GPIO10 135 |
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| 158 | #define HI3670_PCLK_GPIO11 136 |
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| 159 | #define HI3670_PCLK_GPIO12 137 |
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| 160 | #define HI3670_PCLK_GPIO13 138 |
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| 161 | #define HI3670_PCLK_GPIO14 139 |
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| 162 | #define HI3670_PCLK_GPIO15 140 |
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| 163 | #define HI3670_PCLK_GPIO16 141 |
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| 164 | #define HI3670_PCLK_GPIO17 142 |
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| 165 | #define HI3670_PCLK_GPIO20 143 |
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| 166 | #define HI3670_PCLK_GPIO21 144 |
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| 167 | #define HI3670_PCLK_GATE_DSI0 145 |
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| 168 | #define HI3670_PCLK_GATE_DSI1 146 |
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| 169 | #define HI3670_HCLK_GATE_USB3OTG 147 |
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| 170 | #define HI3670_ACLK_GATE_USB3DVFS 148 |
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| 171 | #define HI3670_HCLK_GATE_SDIO 149 |
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| 172 | #define HI3670_PCLK_GATE_PCIE_SYS 150 |
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| 173 | #define HI3670_PCLK_GATE_PCIE_PHY 151 |
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| 174 | #define HI3670_PCLK_GATE_MMC1_PCIE 152 |
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| 175 | #define HI3670_PCLK_GATE_MMC0_IOC 153 |
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| 176 | #define HI3670_PCLK_GATE_MMC1_IOC 154 |
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| 177 | #define HI3670_CLK_GATE_DMAC 155 |
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| 178 | #define HI3670_CLK_GATE_VCODECBUS2DDR 156 |
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| 179 | #define HI3670_CLK_CCI400_BYPASS 157 |
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| 180 | #define HI3670_CLK_GATE_CCI400 158 |
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| 181 | #define HI3670_CLK_GATE_SD 159 |
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| 182 | #define HI3670_HCLK_GATE_SD 160 |
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| 183 | #define HI3670_CLK_GATE_SDIO 161 |
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| 184 | #define HI3670_CLK_GATE_A57HPM 162 |
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| 185 | #define HI3670_CLK_GATE_A53HPM 163 |
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| 186 | #define HI3670_CLK_GATE_PA_A53 164 |
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| 187 | #define HI3670_CLK_GATE_PA_A57 165 |
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| 188 | #define HI3670_CLK_GATE_PA_G3D 166 |
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| 189 | #define HI3670_CLK_GATE_GPUHPM 167 |
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| 190 | #define HI3670_CLK_GATE_PERIHPM 168 |
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| 191 | #define HI3670_CLK_GATE_AOHPM 169 |
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| 192 | #define HI3670_CLK_GATE_UART1 170 |
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| 193 | #define HI3670_CLK_GATE_UART4 171 |
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| 194 | #define HI3670_PCLK_GATE_UART1 172 |
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| 195 | #define HI3670_PCLK_GATE_UART4 173 |
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| 196 | #define HI3670_CLK_GATE_UART2 174 |
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| 197 | #define HI3670_CLK_GATE_UART5 175 |
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| 198 | #define HI3670_PCLK_GATE_UART2 176 |
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| 199 | #define HI3670_PCLK_GATE_UART5 177 |
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| 200 | #define HI3670_CLK_GATE_UART0 178 |
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| 201 | #define HI3670_CLK_GATE_I2C3 179 |
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| 202 | #define HI3670_CLK_GATE_I2C4 180 |
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| 203 | #define HI3670_CLK_GATE_I2C7 181 |
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| 204 | #define HI3670_PCLK_GATE_I2C3 182 |
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| 205 | #define HI3670_PCLK_GATE_I2C4 183 |
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| 206 | #define HI3670_PCLK_GATE_I2C7 184 |
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| 207 | #define HI3670_CLK_GATE_SPI1 185 |
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| 208 | #define HI3670_CLK_GATE_SPI4 186 |
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| 209 | #define HI3670_PCLK_GATE_SPI1 187 |
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| 210 | #define HI3670_PCLK_GATE_SPI4 188 |
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| 211 | #define HI3670_CLK_GATE_USB3OTG_REF 189 |
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| 212 | #define HI3670_CLK_GATE_USB2PHY_REF 190 |
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| 213 | #define HI3670_CLK_GATE_PCIEAUX 191 |
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| 214 | #define HI3670_ACLK_GATE_PCIE 192 |
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| 215 | #define HI3670_CLK_GATE_MMC1_PCIEAXI 193 |
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| 216 | #define HI3670_CLK_GATE_PCIEPHY_REF 194 |
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| 217 | #define HI3670_CLK_GATE_PCIE_DEBOUNCE 195 |
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| 218 | #define HI3670_CLK_GATE_PCIEIO 196 |
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| 219 | #define HI3670_CLK_GATE_PCIE_HP 197 |
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| 220 | #define HI3670_CLK_GATE_AO_ASP 198 |
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| 221 | #define HI3670_PCLK_GATE_PCTRL 199 |
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| 222 | #define HI3670_CLK_CSI_TRANS_GT 200 |
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| 223 | #define HI3670_CLK_DSI_TRANS_GT 201 |
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| 224 | #define HI3670_CLK_GATE_PWM 202 |
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| 225 | #define HI3670_ABB_AUDIO_EN0 203 |
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| 226 | #define HI3670_ABB_AUDIO_EN1 204 |
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| 227 | #define HI3670_ABB_AUDIO_GT_EN0 205 |
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| 228 | #define HI3670_ABB_AUDIO_GT_EN1 206 |
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| 229 | #define HI3670_CLK_GATE_DP_AUDIO_PLL_AO 207 |
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| 230 | #define HI3670_PERI_VOLT_HOLD 208 |
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| 231 | #define HI3670_PERI_VOLT_MIDDLE 209 |
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| 232 | #define HI3670_CLK_GATE_ISP_SNCLK0 210 |
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| 233 | #define HI3670_CLK_GATE_ISP_SNCLK1 211 |
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| 234 | #define HI3670_CLK_GATE_ISP_SNCLK2 212 |
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| 235 | #define HI3670_CLK_GATE_RXDPHY0_CFG 213 |
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| 236 | #define HI3670_CLK_GATE_RXDPHY1_CFG 214 |
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| 237 | #define HI3670_CLK_GATE_RXDPHY2_CFG 215 |
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| 238 | #define HI3670_CLK_GATE_TXDPHY0_CFG 216 |
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| 239 | #define HI3670_CLK_GATE_TXDPHY0_REF 217 |
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| 240 | #define HI3670_CLK_GATE_TXDPHY1_CFG 218 |
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| 241 | #define HI3670_CLK_GATE_TXDPHY1_REF 219 |
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| 242 | #define HI3670_CLK_GATE_MEDIA_TCXO 220 |
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| 243 | |
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| 244 | /* clk in sctrl */ |
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| 245 | #define HI3670_CLK_ANDGT_IOPERI 0 |
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| 246 | #define HI3670_CLKANDGT_ASP_SUBSYS_PERI 1 |
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| 247 | #define HI3670_CLK_ANGT_ASP_SUBSYS 2 |
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| 248 | #define HI3670_CLK_MUX_UFS_SUBSYS 3 |
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| 249 | #define HI3670_CLK_MUX_CLKOUT0 4 |
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| 250 | #define HI3670_CLK_MUX_CLKOUT1 5 |
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| 251 | #define HI3670_CLK_MUX_ASP_SUBSYS_PERI 6 |
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| 252 | #define HI3670_CLK_MUX_ASP_PLL 7 |
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| 253 | #define HI3670_CLK_DIV_AOBUS 8 |
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| 254 | #define HI3670_CLK_DIV_UFS_SUBSYS 9 |
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| 255 | #define HI3670_CLK_DIV_IOPERI 10 |
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| 256 | #define HI3670_CLK_DIV_CLKOUT0_TCXO 11 |
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| 257 | #define HI3670_CLK_DIV_CLKOUT1_TCXO 12 |
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| 258 | #define HI3670_CLK_ASP_SUBSYS_PERI_DIV 13 |
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| 259 | #define HI3670_CLK_DIV_ASP_SUBSYS 14 |
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| 260 | #define HI3670_PPLL0_EN_ACPU 15 |
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| 261 | #define HI3670_PPLL0_GT_CPU 16 |
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| 262 | #define HI3670_CLK_GATE_PPLL0_MEDIA 17 |
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| 263 | #define HI3670_PCLK_GPIO18 18 |
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| 264 | #define HI3670_PCLK_GPIO19 19 |
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| 265 | #define HI3670_CLK_GATE_SPI 20 |
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| 266 | #define HI3670_PCLK_GATE_SPI 21 |
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| 267 | #define HI3670_CLK_GATE_UFS_SUBSYS 22 |
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| 268 | #define HI3670_CLK_GATE_UFSIO_REF 23 |
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| 269 | #define HI3670_PCLK_AO_GPIO0 24 |
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| 270 | #define HI3670_PCLK_AO_GPIO1 25 |
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| 271 | #define HI3670_PCLK_AO_GPIO2 26 |
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| 272 | #define HI3670_PCLK_AO_GPIO3 27 |
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| 273 | #define HI3670_PCLK_AO_GPIO4 28 |
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| 274 | #define HI3670_PCLK_AO_GPIO5 29 |
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| 275 | #define HI3670_PCLK_AO_GPIO6 30 |
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| 276 | #define HI3670_CLK_GATE_OUT0 31 |
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| 277 | #define HI3670_CLK_GATE_OUT1 32 |
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| 278 | #define HI3670_PCLK_GATE_SYSCNT 33 |
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| 279 | #define HI3670_CLK_GATE_SYSCNT 34 |
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| 280 | #define HI3670_CLK_GATE_ASP_SUBSYS_PERI 35 |
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| 281 | #define HI3670_CLK_GATE_ASP_SUBSYS 36 |
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| 282 | #define HI3670_CLK_GATE_ASP_TCXO 37 |
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| 283 | #define HI3670_CLK_GATE_DP_AUDIO_PLL 38 |
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| 284 | |
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| 285 | /* clk in pmuctrl */ |
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| 286 | #define HI3670_GATE_ABB_192 0 |
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| 287 | |
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| 288 | /* clk in pctrl */ |
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| 289 | #define HI3670_GATE_UFS_TCXO_EN 0 |
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| 290 | #define HI3670_GATE_USB_TCXO_EN 1 |
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| 291 | |
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| 292 | /* clk in iomcu */ |
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| 293 | #define HI3670_CLK_GATE_I2C0 0 |
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| 294 | #define HI3670_CLK_GATE_I2C1 1 |
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| 295 | #define HI3670_CLK_GATE_I2C2 2 |
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| 296 | #define HI3670_CLK_GATE_SPI0 3 |
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| 297 | #define HI3670_CLK_GATE_SPI2 4 |
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| 298 | #define HI3670_CLK_GATE_UART3 5 |
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| 299 | #define HI3670_CLK_I2C0_GATE_IOMCU 6 |
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| 300 | #define HI3670_CLK_I2C1_GATE_IOMCU 7 |
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| 301 | #define HI3670_CLK_I2C2_GATE_IOMCU 8 |
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| 302 | #define HI3670_CLK_SPI0_GATE_IOMCU 9 |
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| 303 | #define HI3670_CLK_SPI2_GATE_IOMCU 10 |
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| 304 | #define HI3670_CLK_UART3_GATE_IOMCU 11 |
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| 305 | #define HI3670_CLK_GATE_PERI0_IOMCU 12 |
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| 306 | |
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| 307 | /* clk in media1 */ |
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| 308 | #define HI3670_CLK_GATE_VIVOBUS_ANDGT 0 |
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| 309 | #define HI3670_CLK_ANDGT_EDC0 1 |
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| 310 | #define HI3670_CLK_ANDGT_LDI0 2 |
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| 311 | #define HI3670_CLK_ANDGT_LDI1 3 |
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| 312 | #define HI3670_CLK_MMBUF_PLL_ANDGT 4 |
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| 313 | #define HI3670_PCLK_MMBUF_ANDGT 5 |
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| 314 | #define HI3670_CLK_MUX_VIVOBUS 6 |
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| 315 | #define HI3670_CLK_MUX_EDC0 7 |
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| 316 | #define HI3670_CLK_MUX_LDI0 8 |
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| 317 | #define HI3670_CLK_MUX_LDI1 9 |
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| 318 | #define HI3670_CLK_SW_MMBUF 10 |
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| 319 | #define HI3670_CLK_DIV_VIVOBUS 11 |
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| 320 | #define HI3670_CLK_DIV_EDC0 12 |
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| 321 | #define HI3670_CLK_DIV_LDI0 13 |
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| 322 | #define HI3670_CLK_DIV_LDI1 14 |
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| 323 | #define HI3670_ACLK_DIV_MMBUF 15 |
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| 324 | #define HI3670_PCLK_DIV_MMBUF 16 |
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| 325 | #define HI3670_ACLK_GATE_NOC_DSS 17 |
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| 326 | #define HI3670_PCLK_GATE_NOC_DSS_CFG 18 |
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| 327 | #define HI3670_PCLK_GATE_MMBUF_CFG 19 |
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| 328 | #define HI3670_PCLK_GATE_DISP_NOC_SUBSYS 20 |
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| 329 | #define HI3670_ACLK_GATE_DISP_NOC_SUBSYS 21 |
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| 330 | #define HI3670_PCLK_GATE_DSS 22 |
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| 331 | #define HI3670_ACLK_GATE_DSS 23 |
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| 332 | #define HI3670_CLK_GATE_VIVOBUSFREQ 24 |
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| 333 | #define HI3670_CLK_GATE_EDC0 25 |
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| 334 | #define HI3670_CLK_GATE_LDI0 26 |
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| 335 | #define HI3670_CLK_GATE_LDI1FREQ 27 |
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| 336 | #define HI3670_CLK_GATE_BRG 28 |
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| 337 | #define HI3670_ACLK_GATE_ASC 29 |
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| 338 | #define HI3670_CLK_GATE_DSS_AXI_MM 30 |
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| 339 | #define HI3670_CLK_GATE_MMBUF 31 |
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| 340 | #define HI3670_PCLK_GATE_MMBUF 32 |
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| 341 | #define HI3670_CLK_GATE_ATDIV_VIVO 33 |
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| 342 | |
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| 343 | /* clk in media2 */ |
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| 344 | #define HI3670_CLK_GATE_VDECFREQ 0 |
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| 345 | #define HI3670_CLK_GATE_VENCFREQ 1 |
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| 346 | #define HI3670_CLK_GATE_ICSFREQ 2 |
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| 347 | |
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| 348 | #endif /* __DT_BINDINGS_CLOCK_HI3670_H */ |
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| 349 | |
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