| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2014 Linaro Ltd. |
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| 4 | * Copyright (c) 2014 Hisilicon Limited. |
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| 5 | */ |
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| 6 | |
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| 7 | #ifndef __DTS_HIX5HD2_CLOCK_H |
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| 8 | #define __DTS_HIX5HD2_CLOCK_H |
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| 9 | |
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| 10 | /* fixed rate */ |
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| 11 | #define HIX5HD2_FIXED_1200M 1 |
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| 12 | #define HIX5HD2_FIXED_400M 2 |
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| 13 | #define HIX5HD2_FIXED_48M 3 |
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| 14 | #define HIX5HD2_FIXED_24M 4 |
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| 15 | #define HIX5HD2_FIXED_600M 5 |
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| 16 | #define HIX5HD2_FIXED_300M 6 |
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| 17 | #define HIX5HD2_FIXED_75M 7 |
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| 18 | #define HIX5HD2_FIXED_200M 8 |
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| 19 | #define HIX5HD2_FIXED_100M 9 |
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| 20 | #define HIX5HD2_FIXED_40M 10 |
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| 21 | #define HIX5HD2_FIXED_150M 11 |
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| 22 | #define HIX5HD2_FIXED_1728M 12 |
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| 23 | #define HIX5HD2_FIXED_28P8M 13 |
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| 24 | #define HIX5HD2_FIXED_432M 14 |
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| 25 | #define HIX5HD2_FIXED_345P6M 15 |
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| 26 | #define HIX5HD2_FIXED_288M 16 |
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| 27 | #define HIX5HD2_FIXED_60M 17 |
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| 28 | #define HIX5HD2_FIXED_750M 18 |
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| 29 | #define HIX5HD2_FIXED_500M 19 |
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| 30 | #define HIX5HD2_FIXED_54M 20 |
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| 31 | #define HIX5HD2_FIXED_27M 21 |
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| 32 | #define HIX5HD2_FIXED_1500M 22 |
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| 33 | #define HIX5HD2_FIXED_375M 23 |
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| 34 | #define HIX5HD2_FIXED_187M 24 |
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| 35 | #define HIX5HD2_FIXED_250M 25 |
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| 36 | #define HIX5HD2_FIXED_125M 26 |
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| 37 | #define HIX5HD2_FIXED_2P02M 27 |
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| 38 | #define HIX5HD2_FIXED_50M 28 |
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| 39 | #define HIX5HD2_FIXED_25M 29 |
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| 40 | #define HIX5HD2_FIXED_83M 30 |
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| 41 | |
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| 42 | /* mux clocks */ |
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| 43 | #define HIX5HD2_SFC_MUX 64 |
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| 44 | #define HIX5HD2_MMC_MUX 65 |
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| 45 | #define HIX5HD2_FEPHY_MUX 66 |
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| 46 | #define HIX5HD2_SD_MUX 67 |
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| 47 | |
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| 48 | /* gate clocks */ |
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| 49 | #define HIX5HD2_SFC_RST 128 |
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| 50 | #define HIX5HD2_SFC_CLK 129 |
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| 51 | #define HIX5HD2_MMC_CIU_CLK 130 |
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| 52 | #define HIX5HD2_MMC_BIU_CLK 131 |
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| 53 | #define HIX5HD2_MMC_CIU_RST 132 |
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| 54 | #define HIX5HD2_FWD_BUS_CLK 133 |
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| 55 | #define HIX5HD2_FWD_SYS_CLK 134 |
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| 56 | #define HIX5HD2_MAC0_PHY_CLK 135 |
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| 57 | #define HIX5HD2_SD_CIU_CLK 136 |
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| 58 | #define HIX5HD2_SD_BIU_CLK 137 |
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| 59 | #define HIX5HD2_SD_CIU_RST 138 |
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| 60 | #define HIX5HD2_WDG0_CLK 139 |
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| 61 | #define HIX5HD2_WDG0_RST 140 |
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| 62 | #define HIX5HD2_I2C0_CLK 141 |
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| 63 | #define HIX5HD2_I2C0_RST 142 |
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| 64 | #define HIX5HD2_I2C1_CLK 143 |
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| 65 | #define HIX5HD2_I2C1_RST 144 |
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| 66 | #define HIX5HD2_I2C2_CLK 145 |
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| 67 | #define HIX5HD2_I2C2_RST 146 |
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| 68 | #define HIX5HD2_I2C3_CLK 147 |
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| 69 | #define HIX5HD2_I2C3_RST 148 |
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| 70 | #define HIX5HD2_I2C4_CLK 149 |
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| 71 | #define HIX5HD2_I2C4_RST 150 |
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| 72 | #define HIX5HD2_I2C5_CLK 151 |
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| 73 | #define HIX5HD2_I2C5_RST 152 |
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| 74 | |
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| 75 | /* complex */ |
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| 76 | #define HIX5HD2_MAC0_CLK 192 |
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| 77 | #define HIX5HD2_MAC1_CLK 193 |
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| 78 | #define HIX5HD2_SATA_CLK 194 |
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| 79 | #define HIX5HD2_USB_CLK 195 |
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| 80 | |
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| 81 | #define HIX5HD2_NR_CLKS 256 |
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| 82 | #endif /* __DTS_HIX5HD2_CLOCK_H */ |
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| 83 | |
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