1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Copyright (c) 2014 LSI Corporation |
4 | */ |
5 | |
6 | #ifndef _DT_BINDINGS_CLK_AXM5516_H |
7 | #define _DT_BINDINGS_CLK_AXM5516_H |
8 | |
9 | #define AXXIA_CLK_FAB_PLL 0 |
10 | #define AXXIA_CLK_CPU_PLL 1 |
11 | #define AXXIA_CLK_SYS_PLL 2 |
12 | #define AXXIA_CLK_SM0_PLL 3 |
13 | #define AXXIA_CLK_SM1_PLL 4 |
14 | #define AXXIA_CLK_FAB_DIV 5 |
15 | #define AXXIA_CLK_SYS_DIV 6 |
16 | #define AXXIA_CLK_NRCP_DIV 7 |
17 | #define AXXIA_CLK_CPU0_DIV 8 |
18 | #define AXXIA_CLK_CPU1_DIV 9 |
19 | #define AXXIA_CLK_CPU2_DIV 10 |
20 | #define AXXIA_CLK_CPU3_DIV 11 |
21 | #define AXXIA_CLK_PER_DIV 12 |
22 | #define AXXIA_CLK_MMC_DIV 13 |
23 | #define AXXIA_CLK_FAB 14 |
24 | #define AXXIA_CLK_SYS 15 |
25 | #define AXXIA_CLK_NRCP 16 |
26 | #define AXXIA_CLK_CPU0 17 |
27 | #define AXXIA_CLK_CPU1 18 |
28 | #define AXXIA_CLK_CPU2 19 |
29 | #define AXXIA_CLK_CPU3 20 |
30 | #define AXXIA_CLK_PER 21 |
31 | #define AXXIA_CLK_MMC 22 |
32 | |
33 | #endif |
34 | |