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1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2/*
3 * Copyright (c) 2023 Collabora Ltd.
4 * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
5 */
6#ifndef _DT_BINDINGS_GCE_MT6795_H
7#define _DT_BINDINGS_GCE_MT6795_H
8
9/* GCE HW thread priority */
10#define CMDQ_THR_PRIO_LOWEST 0
11#define CMDQ_THR_PRIO_NORMAL 1
12#define CMDQ_THR_PRIO_NORMAL_2 2
13#define CMDQ_THR_PRIO_MEDIUM 3
14#define CMDQ_THR_PRIO_MEDIUM_2 4
15#define CMDQ_THR_PRIO_HIGH 5
16#define CMDQ_THR_PRIO_HIGHER 6
17#define CMDQ_THR_PRIO_HIGHEST 7
18
19/* GCE SUBSYS */
20#define SUBSYS_1300XXXX 0
21#define SUBSYS_1400XXXX 1
22#define SUBSYS_1401XXXX 2
23#define SUBSYS_1402XXXX 3
24#define SUBSYS_1500XXXX 4
25#define SUBSYS_1600XXXX 5
26#define SUBSYS_1700XXXX 6
27#define SUBSYS_1800XXXX 7
28#define SUBSYS_1000XXXX 8
29#define SUBSYS_1001XXXX 9
30#define SUBSYS_1002XXXX 10
31#define SUBSYS_1003XXXX 11
32#define SUBSYS_1004XXXX 12
33#define SUBSYS_1005XXXX 13
34#define SUBSYS_1020XXXX 14
35#define SUBSYS_1021XXXX 15
36#define SUBSYS_1120XXXX 16
37#define SUBSYS_1121XXXX 17
38#define SUBSYS_1122XXXX 18
39#define SUBSYS_1123XXXX 19
40#define SUBSYS_1124XXXX 20
41#define SUBSYS_1125XXXX 21
42#define SUBSYS_1126XXXX 22
43
44/* GCE HW EVENT */
45#define CMDQ_EVENT_MDP_RDMA0_SOF 0
46#define CMDQ_EVENT_MDP_RDMA1_SOF 1
47#define CMDQ_EVENT_MDP_DSI0_TE_SOF 2
48#define CMDQ_EVENT_MDP_DSI1_TE_SOF 3
49#define CMDQ_EVENT_MDP_MVW_SOF 4
50#define CMDQ_EVENT_MDP_TDSHP0_SOF 5
51#define CMDQ_EVENT_MDP_TDSHP1_SOF 6
52#define CMDQ_EVENT_MDP_WDMA_SOF 7
53#define CMDQ_EVENT_MDP_WROT0_SOF 8
54#define CMDQ_EVENT_MDP_WROT1_SOF 9
55#define CMDQ_EVENT_MDP_CROP_SOF 10
56#define CMDQ_EVENT_DISP_OVL0_SOF 11
57#define CMDQ_EVENT_DISP_OVL1_SOF 12
58#define CMDQ_EVENT_DISP_RDMA0_SOF 13
59#define CMDQ_EVENT_DISP_RDMA1_SOF 14
60#define CMDQ_EVENT_DISP_RDMA2_SOF 15
61#define CMDQ_EVENT_DISP_WDMA0_SOF 16
62#define CMDQ_EVENT_DISP_WDMA1_SOF 17
63#define CMDQ_EVENT_DISP_COLOR0_SOF 18
64#define CMDQ_EVENT_DISP_COLOR1_SOF 19
65#define CMDQ_EVENT_DISP_AAL_SOF 20
66#define CMDQ_EVENT_DISP_GAMMA_SOF 21
67#define CMDQ_EVENT_DISP_UFOE_SOF 22
68#define CMDQ_EVENT_DISP_PWM0_SOF 23
69#define CMDQ_EVENT_DISP_PWM1_SOF 24
70#define CMDQ_EVENT_DISP_OD_SOF 25
71#define CMDQ_EVENT_MDP_RDMA0_EOF 26
72#define CMDQ_EVENT_MDP_RDMA1_EOF 27
73#define CMDQ_EVENT_MDP_RSZ0_EOF 28
74#define CMDQ_EVENT_MDP_RSZ1_EOF 29
75#define CMDQ_EVENT_MDP_RSZ2_EOF 30
76#define CMDQ_EVENT_MDP_TDSHP0_EOF 31
77#define CMDQ_EVENT_MDP_TDSHP1_EOF 32
78#define CMDQ_EVENT_MDP_WDMA_EOF 33
79#define CMDQ_EVENT_MDP_WROT0_WRITE_EOF 34
80#define CMDQ_EVENT_MDP_WROT0_READ_EOF 35
81#define CMDQ_EVENT_MDP_WROT1_WRITE_EOF 36
82#define CMDQ_EVENT_MDP_WROT1_READ_EOF 37
83#define CMDQ_EVENT_MDP_CROP_EOF 38
84#define CMDQ_EVENT_DISP_OVL0_EOF 39
85#define CMDQ_EVENT_DISP_OVL1_EOF 40
86#define CMDQ_EVENT_DISP_RDMA0_EOF 41
87#define CMDQ_EVENT_DISP_RDMA1_EOF 42
88#define CMDQ_EVENT_DISP_RDMA2_EOF 43
89#define CMDQ_EVENT_DISP_WDMA0_EOF 44
90#define CMDQ_EVENT_DISP_WDMA1_EOF 45
91#define CMDQ_EVENT_DISP_COLOR0_EOF 46
92#define CMDQ_EVENT_DISP_COLOR1_EOF 47
93#define CMDQ_EVENT_DISP_AAL_EOF 48
94#define CMDQ_EVENT_DISP_GAMMA_EOF 49
95#define CMDQ_EVENT_DISP_UFOE_EOF 50
96#define CMDQ_EVENT_DISP_DPI0_EOF 51
97#define CMDQ_EVENT_MUTEX0_STREAM_EOF 52
98#define CMDQ_EVENT_MUTEX1_STREAM_EOF 53
99#define CMDQ_EVENT_MUTEX2_STREAM_EOF 54
100#define CMDQ_EVENT_MUTEX3_STREAM_EOF 55
101#define CMDQ_EVENT_MUTEX4_STREAM_EOF 56
102#define CMDQ_EVENT_MUTEX5_STREAM_EOF 57
103#define CMDQ_EVENT_MUTEX6_STREAM_EOF 58
104#define CMDQ_EVENT_MUTEX7_STREAM_EOF 59
105#define CMDQ_EVENT_MUTEX8_STREAM_EOF 60
106#define CMDQ_EVENT_MUTEX9_STREAM_EOF 61
107#define CMDQ_EVENT_DISP_RDMA0_UNDERRUN 62
108#define CMDQ_EVENT_DISP_RDMA1_UNDERRUN 63
109#define CMDQ_EVENT_DISP_RDMA2_UNDERRUN 64
110#define CMDQ_EVENT_ISP_PASS2_2_EOF 129
111#define CMDQ_EVENT_ISP_PASS2_1_EOF 130
112#define CMDQ_EVENT_ISP_PASS2_0_EOF 131
113#define CMDQ_EVENT_ISP_PASS1_1_EOF 132
114#define CMDQ_EVENT_ISP_PASS1_0_EOF 133
115#define CMDQ_EVENT_CAMSV_2_PASS1_EOF 134
116#define CMDQ_EVENT_CAMSV_1_PASS1_EOF 135
117#define CMDQ_EVENT_SENINF_CAM1_2_3_FIFO_FULL 136
118#define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL 137
119#define CMDQ_EVENT_JPGENC_PASS2_EOF 257
120#define CMDQ_EVENT_JPGENC_PASS1_EOF 258
121#define CMDQ_EVENT_JPGDEC_EOF 259
122
123#endif
124

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source code of linux/include/dt-bindings/gce/mediatek,mt6795-gce.h