1/* SPDX-License-Identifier: GPL-2.0-only */
2/* include/linux/amba/pl080.h
3 *
4 * Copyright 2008 Openmoko, Inc.
5 * Copyright 2008 Simtec Electronics
6 * http://armlinux.simtec.co.uk/
7 * Ben Dooks <ben@simtec.co.uk>
8 *
9 * ARM PrimeCell PL080 DMA controller
10*/
11
12/* Note, there are some Samsung updates to this controller block which
13 * make it not entierly compatible with the PL080 specification from
14 * ARM. When in doubt, check the Samsung documentation first.
15 *
16 * The Samsung defines are PL080S, and add an extra control register,
17 * the ability to move more than 2^11 counts of data and some extra
18 * OneNAND features.
19*/
20
21#ifndef ASM_PL080_H
22#define ASM_PL080_H
23
24#define PL080_INT_STATUS (0x00)
25#define PL080_TC_STATUS (0x04)
26#define PL080_TC_CLEAR (0x08)
27#define PL080_ERR_STATUS (0x0C)
28#define PL080_ERR_CLEAR (0x10)
29#define PL080_RAW_TC_STATUS (0x14)
30#define PL080_RAW_ERR_STATUS (0x18)
31#define PL080_EN_CHAN (0x1c)
32#define PL080_SOFT_BREQ (0x20)
33#define PL080_SOFT_SREQ (0x24)
34#define PL080_SOFT_LBREQ (0x28)
35#define PL080_SOFT_LSREQ (0x2C)
36
37#define PL080_CONFIG (0x30)
38#define PL080_CONFIG_M2_BE BIT(2)
39#define PL080_CONFIG_M1_BE BIT(1)
40#define PL080_CONFIG_ENABLE BIT(0)
41
42#define PL080_SYNC (0x34)
43
44/* The Faraday Technology FTDMAC020 variant registers */
45#define FTDMAC020_CH_BUSY (0x20)
46/* Identical to PL080_CONFIG */
47#define FTDMAC020_CSR (0x24)
48/* Identical to PL080_SYNC */
49#define FTDMAC020_SYNC (0x2C)
50#define FTDMAC020_REVISION (0x30)
51#define FTDMAC020_FEATURE (0x34)
52
53/* Per channel configuration registers */
54#define PL080_Cx_BASE(x) ((0x100 + (x * 0x20)))
55#define PL080_CH_SRC_ADDR (0x00)
56#define PL080_CH_DST_ADDR (0x04)
57#define PL080_CH_LLI (0x08)
58#define PL080_CH_CONTROL (0x0C)
59#define PL080_CH_CONFIG (0x10)
60#define PL080S_CH_CONTROL2 (0x10)
61#define PL080S_CH_CONFIG (0x14)
62/* The Faraday FTDMAC020 derivative shuffles the registers around */
63#define FTDMAC020_CH_CSR (0x00)
64#define FTDMAC020_CH_CFG (0x04)
65#define FTDMAC020_CH_SRC_ADDR (0x08)
66#define FTDMAC020_CH_DST_ADDR (0x0C)
67#define FTDMAC020_CH_LLP (0x10)
68#define FTDMAC020_CH_SIZE (0x14)
69
70#define PL080_LLI_ADDR_MASK GENMASK(31, 2)
71#define PL080_LLI_ADDR_SHIFT (2)
72#define PL080_LLI_LM_AHB2 BIT(0)
73
74#define PL080_CONTROL_TC_IRQ_EN BIT(31)
75#define PL080_CONTROL_PROT_MASK GENMASK(30, 28)
76#define PL080_CONTROL_PROT_SHIFT (28)
77#define PL080_CONTROL_PROT_CACHE BIT(30)
78#define PL080_CONTROL_PROT_BUFF BIT(29)
79#define PL080_CONTROL_PROT_SYS BIT(28)
80#define PL080_CONTROL_DST_INCR BIT(27)
81#define PL080_CONTROL_SRC_INCR BIT(26)
82#define PL080_CONTROL_DST_AHB2 BIT(25)
83#define PL080_CONTROL_SRC_AHB2 BIT(24)
84#define PL080_CONTROL_DWIDTH_MASK GENMASK(23, 21)
85#define PL080_CONTROL_DWIDTH_SHIFT (21)
86#define PL080_CONTROL_SWIDTH_MASK GENMASK(20, 18)
87#define PL080_CONTROL_SWIDTH_SHIFT (18)
88#define PL080_CONTROL_DB_SIZE_MASK GENMASK(17, 15)
89#define PL080_CONTROL_DB_SIZE_SHIFT (15)
90#define PL080_CONTROL_SB_SIZE_MASK GENMASK(14, 12)
91#define PL080_CONTROL_SB_SIZE_SHIFT (12)
92#define PL080_CONTROL_TRANSFER_SIZE_MASK GENMASK(11, 0)
93#define PL080S_CONTROL_TRANSFER_SIZE_MASK GENMASK(24, 0)
94#define PL080_CONTROL_TRANSFER_SIZE_SHIFT (0)
95
96#define PL080_BSIZE_1 (0x0)
97#define PL080_BSIZE_4 (0x1)
98#define PL080_BSIZE_8 (0x2)
99#define PL080_BSIZE_16 (0x3)
100#define PL080_BSIZE_32 (0x4)
101#define PL080_BSIZE_64 (0x5)
102#define PL080_BSIZE_128 (0x6)
103#define PL080_BSIZE_256 (0x7)
104
105#define PL080_WIDTH_8BIT (0x0)
106#define PL080_WIDTH_16BIT (0x1)
107#define PL080_WIDTH_32BIT (0x2)
108
109#define PL080N_CONFIG_ITPROT BIT(20)
110#define PL080N_CONFIG_SECPROT BIT(19)
111#define PL080_CONFIG_HALT BIT(18)
112#define PL080_CONFIG_ACTIVE BIT(17) /* RO */
113#define PL080_CONFIG_LOCK BIT(16)
114#define PL080_CONFIG_TC_IRQ_MASK BIT(15)
115#define PL080_CONFIG_ERR_IRQ_MASK BIT(14)
116#define PL080_CONFIG_FLOW_CONTROL_MASK GENMASK(13, 11)
117#define PL080_CONFIG_FLOW_CONTROL_SHIFT (11)
118#define PL080_CONFIG_DST_SEL_MASK GENMASK(9, 6)
119#define PL080_CONFIG_DST_SEL_SHIFT (6)
120#define PL080_CONFIG_SRC_SEL_MASK GENMASK(4, 1)
121#define PL080_CONFIG_SRC_SEL_SHIFT (1)
122#define PL080_CONFIG_ENABLE BIT(0)
123
124#define PL080_FLOW_MEM2MEM (0x0)
125#define PL080_FLOW_MEM2PER (0x1)
126#define PL080_FLOW_PER2MEM (0x2)
127#define PL080_FLOW_SRC2DST (0x3)
128#define PL080_FLOW_SRC2DST_DST (0x4)
129#define PL080_FLOW_MEM2PER_PER (0x5)
130#define PL080_FLOW_PER2MEM_PER (0x6)
131#define PL080_FLOW_SRC2DST_SRC (0x7)
132
133#define FTDMAC020_CH_CSR_TC_MSK BIT(31)
134/* Later versions have a threshold in bits 24..26, */
135#define FTDMAC020_CH_CSR_FIFOTH_MSK GENMASK(26, 24)
136#define FTDMAC020_CH_CSR_FIFOTH_SHIFT (24)
137#define FTDMAC020_CH_CSR_CHPR1_MSK GENMASK(23, 22)
138#define FTDMAC020_CH_CSR_PROT3 BIT(21)
139#define FTDMAC020_CH_CSR_PROT2 BIT(20)
140#define FTDMAC020_CH_CSR_PROT1 BIT(19)
141#define FTDMAC020_CH_CSR_SRC_SIZE_MSK GENMASK(18, 16)
142#define FTDMAC020_CH_CSR_SRC_SIZE_SHIFT (16)
143#define FTDMAC020_CH_CSR_ABT BIT(15)
144#define FTDMAC020_CH_CSR_SRC_WIDTH_MSK GENMASK(13, 11)
145#define FTDMAC020_CH_CSR_SRC_WIDTH_SHIFT (11)
146#define FTDMAC020_CH_CSR_DST_WIDTH_MSK GENMASK(10, 8)
147#define FTDMAC020_CH_CSR_DST_WIDTH_SHIFT (8)
148#define FTDMAC020_CH_CSR_MODE BIT(7)
149/* 00 = increase, 01 = decrease, 10 = fix */
150#define FTDMAC020_CH_CSR_SRCAD_CTL_MSK GENMASK(6, 5)
151#define FTDMAC020_CH_CSR_SRCAD_CTL_SHIFT (5)
152#define FTDMAC020_CH_CSR_DSTAD_CTL_MSK GENMASK(4, 3)
153#define FTDMAC020_CH_CSR_DSTAD_CTL_SHIFT (3)
154#define FTDMAC020_CH_CSR_SRC_SEL BIT(2)
155#define FTDMAC020_CH_CSR_DST_SEL BIT(1)
156#define FTDMAC020_CH_CSR_EN BIT(0)
157
158/* FIFO threshold setting */
159#define FTDMAC020_CH_CSR_FIFOTH_1 (0x0)
160#define FTDMAC020_CH_CSR_FIFOTH_2 (0x1)
161#define FTDMAC020_CH_CSR_FIFOTH_4 (0x2)
162#define FTDMAC020_CH_CSR_FIFOTH_8 (0x3)
163#define FTDMAC020_CH_CSR_FIFOTH_16 (0x4)
164/* The FTDMAC020 supports 64bit wide transfers */
165#define FTDMAC020_WIDTH_64BIT (0x3)
166/* Address can be increased, decreased or fixed */
167#define FTDMAC020_CH_CSR_SRCAD_CTL_INC (0x0)
168#define FTDMAC020_CH_CSR_SRCAD_CTL_DEC (0x1)
169#define FTDMAC020_CH_CSR_SRCAD_CTL_FIXED (0x2)
170
171#define FTDMAC020_CH_CFG_LLP_CNT_MASK GENMASK(19, 16)
172#define FTDMAC020_CH_CFG_LLP_CNT_SHIFT (16)
173#define FTDMAC020_CH_CFG_BUSY BIT(8)
174#define FTDMAC020_CH_CFG_INT_ABT_MASK BIT(2)
175#define FTDMAC020_CH_CFG_INT_ERR_MASK BIT(1)
176#define FTDMAC020_CH_CFG_INT_TC_MASK BIT(0)
177
178/* Inside the LLIs, the applicable CSR fields are mapped differently */
179#define FTDMAC020_LLI_TC_MSK BIT(28)
180#define FTDMAC020_LLI_SRC_WIDTH_MSK GENMASK(27, 25)
181#define FTDMAC020_LLI_SRC_WIDTH_SHIFT (25)
182#define FTDMAC020_LLI_DST_WIDTH_MSK GENMASK(24, 22)
183#define FTDMAC020_LLI_DST_WIDTH_SHIFT (22)
184#define FTDMAC020_LLI_SRCAD_CTL_MSK GENMASK(21, 20)
185#define FTDMAC020_LLI_SRCAD_CTL_SHIFT (20)
186#define FTDMAC020_LLI_DSTAD_CTL_MSK GENMASK(19, 18)
187#define FTDMAC020_LLI_DSTAD_CTL_SHIFT (18)
188#define FTDMAC020_LLI_SRC_SEL BIT(17)
189#define FTDMAC020_LLI_DST_SEL BIT(16)
190#define FTDMAC020_LLI_TRANSFER_SIZE_MASK GENMASK(11, 0)
191#define FTDMAC020_LLI_TRANSFER_SIZE_SHIFT (0)
192
193#define FTDMAC020_CFG_LLP_CNT_MASK GENMASK(19, 16)
194#define FTDMAC020_CFG_LLP_CNT_SHIFT (16)
195#define FTDMAC020_CFG_BUSY BIT(8)
196#define FTDMAC020_CFG_INT_ABT_MSK BIT(2)
197#define FTDMAC020_CFG_INT_ERR_MSK BIT(1)
198#define FTDMAC020_CFG_INT_TC_MSK BIT(0)
199
200/* DMA linked list chain structure */
201
202struct pl080_lli {
203 u32 src_addr;
204 u32 dst_addr;
205 u32 next_lli;
206 u32 control0;
207};
208
209struct pl080s_lli {
210 u32 src_addr;
211 u32 dst_addr;
212 u32 next_lli;
213 u32 control0;
214 u32 control1;
215};
216
217#endif /* ASM_PL080_H */
218

source code of linux/include/linux/amba/pl080.h