1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
4 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
5 | * Leo Duran <leo.duran@amd.com> |
6 | */ |
7 | |
8 | #ifndef _ASM_X86_AMD_IOMMU_H |
9 | #define _ASM_X86_AMD_IOMMU_H |
10 | |
11 | #include <linux/types.h> |
12 | |
13 | struct amd_iommu; |
14 | |
15 | /* |
16 | * This is mainly used to communicate information back-and-forth |
17 | * between SVM and IOMMU for setting up and tearing down posted |
18 | * interrupt |
19 | */ |
20 | struct amd_iommu_pi_data { |
21 | u32 ga_tag; |
22 | u32 prev_ga_tag; |
23 | u64 base; |
24 | bool is_guest_mode; |
25 | struct vcpu_data *vcpu_data; |
26 | void *ir_data; |
27 | }; |
28 | |
29 | #ifdef CONFIG_AMD_IOMMU |
30 | |
31 | struct task_struct; |
32 | struct pci_dev; |
33 | |
34 | extern int amd_iommu_detect(void); |
35 | |
36 | /** |
37 | * amd_iommu_init_device() - Init device for use with IOMMUv2 driver |
38 | * @pdev: The PCI device to initialize |
39 | * @pasids: Number of PASIDs to support for this device |
40 | * |
41 | * This function does all setup for the device pdev so that it can be |
42 | * used with IOMMUv2. |
43 | * Returns 0 on success or negative value on error. |
44 | */ |
45 | extern int amd_iommu_init_device(struct pci_dev *pdev, int pasids); |
46 | |
47 | /** |
48 | * amd_iommu_free_device() - Free all IOMMUv2 related device resources |
49 | * and disable IOMMUv2 usage for this device |
50 | * @pdev: The PCI device to disable IOMMUv2 usage for' |
51 | */ |
52 | extern void amd_iommu_free_device(struct pci_dev *pdev); |
53 | |
54 | /** |
55 | * amd_iommu_bind_pasid() - Bind a given task to a PASID on a device |
56 | * @pdev: The PCI device to bind the task to |
57 | * @pasid: The PASID on the device the task should be bound to |
58 | * @task: the task to bind |
59 | * |
60 | * The function returns 0 on success or a negative value on error. |
61 | */ |
62 | extern int amd_iommu_bind_pasid(struct pci_dev *pdev, u32 pasid, |
63 | struct task_struct *task); |
64 | |
65 | /** |
66 | * amd_iommu_unbind_pasid() - Unbind a PASID from its task on |
67 | * a device |
68 | * @pdev: The device of the PASID |
69 | * @pasid: The PASID to unbind |
70 | * |
71 | * When this function returns the device is no longer using the PASID |
72 | * and the PASID is no longer bound to its task. |
73 | */ |
74 | extern void amd_iommu_unbind_pasid(struct pci_dev *pdev, u32 pasid); |
75 | |
76 | /** |
77 | * amd_iommu_set_invalid_ppr_cb() - Register a call-back for failed |
78 | * PRI requests |
79 | * @pdev: The PCI device the call-back should be registered for |
80 | * @cb: The call-back function |
81 | * |
82 | * The IOMMUv2 driver invokes this call-back when it is unable to |
83 | * successfully handle a PRI request. The device driver can then decide |
84 | * which PRI response the device should see. Possible return values for |
85 | * the call-back are: |
86 | * |
87 | * - AMD_IOMMU_INV_PRI_RSP_SUCCESS - Send SUCCESS back to the device |
88 | * - AMD_IOMMU_INV_PRI_RSP_INVALID - Send INVALID back to the device |
89 | * - AMD_IOMMU_INV_PRI_RSP_FAIL - Send Failure back to the device, |
90 | * the device is required to disable |
91 | * PRI when it receives this response |
92 | * |
93 | * The function returns 0 on success or negative value on error. |
94 | */ |
95 | #define AMD_IOMMU_INV_PRI_RSP_SUCCESS 0 |
96 | #define AMD_IOMMU_INV_PRI_RSP_INVALID 1 |
97 | #define AMD_IOMMU_INV_PRI_RSP_FAIL 2 |
98 | |
99 | typedef int (*amd_iommu_invalid_ppr_cb)(struct pci_dev *pdev, |
100 | u32 pasid, |
101 | unsigned long address, |
102 | u16); |
103 | |
104 | extern int amd_iommu_set_invalid_ppr_cb(struct pci_dev *pdev, |
105 | amd_iommu_invalid_ppr_cb cb); |
106 | |
107 | #define PPR_FAULT_EXEC (1 << 1) |
108 | #define PPR_FAULT_READ (1 << 2) |
109 | #define PPR_FAULT_WRITE (1 << 5) |
110 | #define PPR_FAULT_USER (1 << 6) |
111 | #define PPR_FAULT_RSVD (1 << 7) |
112 | #define PPR_FAULT_GN (1 << 8) |
113 | |
114 | /** |
115 | * amd_iommu_device_info() - Get information about IOMMUv2 support of a |
116 | * PCI device |
117 | * @pdev: PCI device to query information from |
118 | * @info: A pointer to an amd_iommu_device_info structure which will contain |
119 | * the information about the PCI device |
120 | * |
121 | * Returns 0 on success, negative value on error |
122 | */ |
123 | |
124 | #define AMD_IOMMU_DEVICE_FLAG_ATS_SUP 0x1 /* ATS feature supported */ |
125 | #define AMD_IOMMU_DEVICE_FLAG_PRI_SUP 0x2 /* PRI feature supported */ |
126 | #define AMD_IOMMU_DEVICE_FLAG_PASID_SUP 0x4 /* PASID context supported */ |
127 | #define AMD_IOMMU_DEVICE_FLAG_EXEC_SUP 0x8 /* Device may request execution |
128 | on memory pages */ |
129 | #define AMD_IOMMU_DEVICE_FLAG_PRIV_SUP 0x10 /* Device may request |
130 | super-user privileges */ |
131 | |
132 | struct amd_iommu_device_info { |
133 | int max_pasids; |
134 | u32 flags; |
135 | }; |
136 | |
137 | extern int amd_iommu_device_info(struct pci_dev *pdev, |
138 | struct amd_iommu_device_info *info); |
139 | |
140 | /** |
141 | * amd_iommu_set_invalidate_ctx_cb() - Register a call-back for invalidating |
142 | * a pasid context. This call-back is |
143 | * invoked when the IOMMUv2 driver needs to |
144 | * invalidate a PASID context, for example |
145 | * because the task that is bound to that |
146 | * context is about to exit. |
147 | * |
148 | * @pdev: The PCI device the call-back should be registered for |
149 | * @cb: The call-back function |
150 | */ |
151 | |
152 | typedef void (*amd_iommu_invalidate_ctx)(struct pci_dev *pdev, u32 pasid); |
153 | |
154 | extern int amd_iommu_set_invalidate_ctx_cb(struct pci_dev *pdev, |
155 | amd_iommu_invalidate_ctx cb); |
156 | #else /* CONFIG_AMD_IOMMU */ |
157 | |
158 | static inline int amd_iommu_detect(void) { return -ENODEV; } |
159 | |
160 | #endif /* CONFIG_AMD_IOMMU */ |
161 | |
162 | #if defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) |
163 | |
164 | /* IOMMU AVIC Function */ |
165 | extern int amd_iommu_register_ga_log_notifier(int (*notifier)(u32)); |
166 | |
167 | extern int |
168 | amd_iommu_update_ga(int cpu, bool is_run, void *data); |
169 | |
170 | extern int amd_iommu_activate_guest_mode(void *data); |
171 | extern int amd_iommu_deactivate_guest_mode(void *data); |
172 | |
173 | #else /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */ |
174 | |
175 | static inline int |
176 | amd_iommu_register_ga_log_notifier(int (*notifier)(u32)) |
177 | { |
178 | return 0; |
179 | } |
180 | |
181 | static inline int |
182 | amd_iommu_update_ga(int cpu, bool is_run, void *data) |
183 | { |
184 | return 0; |
185 | } |
186 | |
187 | static inline int amd_iommu_activate_guest_mode(void *data) |
188 | { |
189 | return 0; |
190 | } |
191 | |
192 | static inline int amd_iommu_deactivate_guest_mode(void *data) |
193 | { |
194 | return 0; |
195 | } |
196 | #endif /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */ |
197 | |
198 | int amd_iommu_get_num_iommus(void); |
199 | bool amd_iommu_pc_supported(void); |
200 | u8 amd_iommu_pc_get_max_banks(unsigned int idx); |
201 | u8 amd_iommu_pc_get_max_counters(unsigned int idx); |
202 | int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, |
203 | u64 *value); |
204 | int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, |
205 | u64 *value); |
206 | struct amd_iommu *get_amd_iommu(unsigned int idx); |
207 | |
208 | #ifdef CONFIG_AMD_MEM_ENCRYPT |
209 | int amd_iommu_snp_enable(void); |
210 | #endif |
211 | |
212 | #endif /* _ASM_X86_AMD_IOMMU_H */ |
213 | |