1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | #ifndef LINUX_BCMA_DRIVER_CC_H_ |
3 | #define LINUX_BCMA_DRIVER_CC_H_ |
4 | |
5 | #include <linux/platform_device.h> |
6 | #include <linux/platform_data/brcmnand.h> |
7 | #include <linux/gpio/driver.h> |
8 | |
9 | /** ChipCommon core registers. **/ |
10 | #define BCMA_CC_ID 0x0000 |
11 | #define BCMA_CC_ID_ID 0x0000FFFF |
12 | #define BCMA_CC_ID_ID_SHIFT 0 |
13 | #define BCMA_CC_ID_REV 0x000F0000 |
14 | #define BCMA_CC_ID_REV_SHIFT 16 |
15 | #define BCMA_CC_ID_PKG 0x00F00000 |
16 | #define BCMA_CC_ID_PKG_SHIFT 20 |
17 | #define BCMA_CC_ID_NRCORES 0x0F000000 |
18 | #define BCMA_CC_ID_NRCORES_SHIFT 24 |
19 | #define BCMA_CC_ID_TYPE 0xF0000000 |
20 | #define BCMA_CC_ID_TYPE_SHIFT 28 |
21 | #define BCMA_CC_CAP 0x0004 /* Capabilities */ |
22 | #define BCMA_CC_CAP_NRUART 0x00000003 /* # of UARTs */ |
23 | #define BCMA_CC_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */ |
24 | #define BCMA_CC_CAP_UARTCLK 0x00000018 /* UART clock select */ |
25 | #define BCMA_CC_CAP_UARTCLK_INT 0x00000008 /* UARTs are driven by internal divided clock */ |
26 | #define BCMA_CC_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */ |
27 | #define BCMA_CC_CAP_EXTBUS 0x000000C0 /* External buses present */ |
28 | #define BCMA_CC_CAP_FLASHT 0x00000700 /* Flash Type */ |
29 | #define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */ |
30 | #define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */ |
31 | #define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */ |
32 | #define BCMA_CC_FLASHT_NAND 0x00000300 /* NAND flash */ |
33 | #define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */ |
34 | #define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */ |
35 | #define BCMA_PLLTYPE_NONE 0x00000000 |
36 | #define BCMA_PLLTYPE_1 0x00010000 /* 48Mhz base, 3 dividers */ |
37 | #define BCMA_PLLTYPE_2 0x00020000 /* 48Mhz, 4 dividers */ |
38 | #define BCMA_PLLTYPE_3 0x00030000 /* 25Mhz, 2 dividers */ |
39 | #define BCMA_PLLTYPE_4 0x00008000 /* 48Mhz, 4 dividers */ |
40 | #define BCMA_PLLTYPE_5 0x00018000 /* 25Mhz, 4 dividers */ |
41 | #define BCMA_PLLTYPE_6 0x00028000 /* 100/200 or 120/240 only */ |
42 | #define BCMA_PLLTYPE_7 0x00038000 /* 25Mhz, 4 dividers */ |
43 | #define BCMA_CC_CAP_PCTL 0x00040000 /* Power Control */ |
44 | #define BCMA_CC_CAP_OTPS 0x00380000 /* OTP size */ |
45 | #define BCMA_CC_CAP_OTPS_SHIFT 19 |
46 | #define BCMA_CC_CAP_OTPS_BASE 5 |
47 | #define BCMA_CC_CAP_JTAGM 0x00400000 /* JTAG master present */ |
48 | #define BCMA_CC_CAP_BROM 0x00800000 /* Internal boot ROM active */ |
49 | #define BCMA_CC_CAP_64BIT 0x08000000 /* 64-bit Backplane */ |
50 | #define BCMA_CC_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */ |
51 | #define BCMA_CC_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */ |
52 | #define BCMA_CC_CAP_SPROM 0x40000000 /* SPROM present */ |
53 | #define BCMA_CC_CAP_NFLASH 0x80000000 /* NAND flash present (rev >= 35 or BCM4706?) */ |
54 | #define BCMA_CC_CORECTL 0x0008 |
55 | #define BCMA_CC_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */ |
56 | #define BCMA_CC_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */ |
57 | #define BCMA_CC_CORECTL_UARTCLKEN 0x00000008 /* UART clock enable (rev >= 21) */ |
58 | #define BCMA_CC_BIST 0x000C |
59 | #define BCMA_CC_OTPS 0x0010 /* OTP status */ |
60 | #define BCMA_CC_OTPS_PROGFAIL 0x80000000 |
61 | #define BCMA_CC_OTPS_PROTECT 0x00000007 |
62 | #define BCMA_CC_OTPS_HW_PROTECT 0x00000001 |
63 | #define BCMA_CC_OTPS_SW_PROTECT 0x00000002 |
64 | #define BCMA_CC_OTPS_CID_PROTECT 0x00000004 |
65 | #define BCMA_CC_OTPS_GU_PROG_IND 0x00000F00 /* General Use programmed indication */ |
66 | #define BCMA_CC_OTPS_GU_PROG_IND_SHIFT 8 |
67 | #define BCMA_CC_OTPS_GU_PROG_HW 0x00000100 /* HW region programmed */ |
68 | #define BCMA_CC_OTPC 0x0014 /* OTP control */ |
69 | #define BCMA_CC_OTPC_RECWAIT 0xFF000000 |
70 | #define BCMA_CC_OTPC_PROGWAIT 0x00FFFF00 |
71 | #define BCMA_CC_OTPC_PRW_SHIFT 8 |
72 | #define BCMA_CC_OTPC_MAXFAIL 0x00000038 |
73 | #define BCMA_CC_OTPC_VSEL 0x00000006 |
74 | #define BCMA_CC_OTPC_SELVL 0x00000001 |
75 | #define BCMA_CC_OTPP 0x0018 /* OTP prog */ |
76 | #define BCMA_CC_OTPP_COL 0x000000FF |
77 | #define BCMA_CC_OTPP_ROW 0x0000FF00 |
78 | #define BCMA_CC_OTPP_ROW_SHIFT 8 |
79 | #define BCMA_CC_OTPP_READERR 0x10000000 |
80 | #define BCMA_CC_OTPP_VALUE 0x20000000 |
81 | #define BCMA_CC_OTPP_READ 0x40000000 |
82 | #define BCMA_CC_OTPP_START 0x80000000 |
83 | #define BCMA_CC_OTPP_BUSY 0x80000000 |
84 | #define BCMA_CC_OTPL 0x001C /* OTP layout */ |
85 | #define BCMA_CC_OTPL_GURGN_OFFSET 0x00000FFF /* offset of general use region */ |
86 | #define BCMA_CC_IRQSTAT 0x0020 |
87 | #define BCMA_CC_IRQMASK 0x0024 |
88 | #define BCMA_CC_IRQ_GPIO 0x00000001 /* gpio intr */ |
89 | #define BCMA_CC_IRQ_EXT 0x00000002 /* ro: ext intr pin (corerev >= 3) */ |
90 | #define BCMA_CC_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */ |
91 | #define BCMA_CC_CHIPCTL 0x0028 /* Rev >= 11 only */ |
92 | #define BCMA_CC_CHIPSTAT 0x002C /* Rev >= 11 only */ |
93 | #define BCMA_CC_CHIPST_4313_SPROM_PRESENT 1 |
94 | #define BCMA_CC_CHIPST_4313_OTP_PRESENT 2 |
95 | #define BCMA_CC_CHIPST_4331_SPROM_PRESENT 2 |
96 | #define BCMA_CC_CHIPST_4331_OTP_PRESENT 4 |
97 | #define BCMA_CC_CHIPST_43228_ILP_DIV_EN 0x00000001 |
98 | #define BCMA_CC_CHIPST_43228_OTP_PRESENT 0x00000002 |
99 | #define BCMA_CC_CHIPST_43228_SERDES_REFCLK_PADSEL 0x00000004 |
100 | #define BCMA_CC_CHIPST_43228_SDIO_MODE 0x00000008 |
101 | #define BCMA_CC_CHIPST_43228_SDIO_OTP_PRESENT 0x00000010 |
102 | #define BCMA_CC_CHIPST_43228_SDIO_RESET 0x00000020 |
103 | #define BCMA_CC_CHIPST_4706_PKG_OPTION BIT(0) /* 0: full-featured package 1: low-cost package */ |
104 | #define BCMA_CC_CHIPST_4706_SFLASH_PRESENT BIT(1) /* 0: parallel, 1: serial flash is present */ |
105 | #define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */ |
106 | #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */ |
107 | #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */ |
108 | #define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */ |
109 | #define BCMA_CC_CHIPST_4360_XTAL_40MZ 0x00000001 |
110 | #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */ |
111 | #define BCMA_CC_JCMD_START 0x80000000 |
112 | #define BCMA_CC_JCMD_BUSY 0x80000000 |
113 | #define BCMA_CC_JCMD_PAUSE 0x40000000 |
114 | #define BCMA_CC_JCMD0_ACC_MASK 0x0000F000 |
115 | #define BCMA_CC_JCMD0_ACC_IRDR 0x00000000 |
116 | #define BCMA_CC_JCMD0_ACC_DR 0x00001000 |
117 | #define BCMA_CC_JCMD0_ACC_IR 0x00002000 |
118 | #define BCMA_CC_JCMD0_ACC_RESET 0x00003000 |
119 | #define BCMA_CC_JCMD0_ACC_IRPDR 0x00004000 |
120 | #define BCMA_CC_JCMD0_ACC_PDR 0x00005000 |
121 | #define BCMA_CC_JCMD0_IRW_MASK 0x00000F00 |
122 | #define BCMA_CC_JCMD_ACC_MASK 0x000F0000 /* Changes for corerev 11 */ |
123 | #define BCMA_CC_JCMD_ACC_IRDR 0x00000000 |
124 | #define BCMA_CC_JCMD_ACC_DR 0x00010000 |
125 | #define BCMA_CC_JCMD_ACC_IR 0x00020000 |
126 | #define BCMA_CC_JCMD_ACC_RESET 0x00030000 |
127 | #define BCMA_CC_JCMD_ACC_IRPDR 0x00040000 |
128 | #define BCMA_CC_JCMD_ACC_PDR 0x00050000 |
129 | #define BCMA_CC_JCMD_IRW_MASK 0x00001F00 |
130 | #define BCMA_CC_JCMD_IRW_SHIFT 8 |
131 | #define BCMA_CC_JCMD_DRW_MASK 0x0000003F |
132 | #define BCMA_CC_JIR 0x0034 /* Rev >= 10 only */ |
133 | #define BCMA_CC_JDR 0x0038 /* Rev >= 10 only */ |
134 | #define BCMA_CC_JCTL 0x003C /* Rev >= 10 only */ |
135 | #define BCMA_CC_JCTL_FORCE_CLK 4 /* Force clock */ |
136 | #define BCMA_CC_JCTL_EXT_EN 2 /* Enable external targets */ |
137 | #define BCMA_CC_JCTL_EN 1 /* Enable Jtag master */ |
138 | #define BCMA_CC_FLASHCTL 0x0040 |
139 | /* Start/busy bit in flashcontrol */ |
140 | #define BCMA_CC_FLASHCTL_OPCODE 0x000000ff |
141 | #define BCMA_CC_FLASHCTL_ACTION 0x00000700 |
142 | #define BCMA_CC_FLASHCTL_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */ |
143 | #define BCMA_CC_FLASHCTL_START 0x80000000 |
144 | #define BCMA_CC_FLASHCTL_BUSY BCMA_CC_FLASHCTL_START |
145 | /* Flashcontrol action + opcodes for ST flashes */ |
146 | #define BCMA_CC_FLASHCTL_ST_WREN 0x0006 /* Write Enable */ |
147 | #define BCMA_CC_FLASHCTL_ST_WRDIS 0x0004 /* Write Disable */ |
148 | #define BCMA_CC_FLASHCTL_ST_RDSR 0x0105 /* Read Status Register */ |
149 | #define BCMA_CC_FLASHCTL_ST_WRSR 0x0101 /* Write Status Register */ |
150 | #define BCMA_CC_FLASHCTL_ST_READ 0x0303 /* Read Data Bytes */ |
151 | #define BCMA_CC_FLASHCTL_ST_PP 0x0302 /* Page Program */ |
152 | #define BCMA_CC_FLASHCTL_ST_SE 0x02d8 /* Sector Erase */ |
153 | #define BCMA_CC_FLASHCTL_ST_BE 0x00c7 /* Bulk Erase */ |
154 | #define BCMA_CC_FLASHCTL_ST_DP 0x00b9 /* Deep Power-down */ |
155 | #define BCMA_CC_FLASHCTL_ST_RES 0x03ab /* Read Electronic Signature */ |
156 | #define BCMA_CC_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */ |
157 | #define BCMA_CC_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */ |
158 | /* Flashcontrol action + opcodes for Atmel flashes */ |
159 | #define BCMA_CC_FLASHCTL_AT_READ 0x07e8 |
160 | #define BCMA_CC_FLASHCTL_AT_PAGE_READ 0x07d2 |
161 | #define BCMA_CC_FLASHCTL_AT_STATUS 0x01d7 |
162 | #define BCMA_CC_FLASHCTL_AT_BUF1_WRITE 0x0384 |
163 | #define BCMA_CC_FLASHCTL_AT_BUF2_WRITE 0x0387 |
164 | #define BCMA_CC_FLASHCTL_AT_BUF1_ERASE_PROGRAM 0x0283 |
165 | #define BCMA_CC_FLASHCTL_AT_BUF2_ERASE_PROGRAM 0x0286 |
166 | #define BCMA_CC_FLASHCTL_AT_BUF1_PROGRAM 0x0288 |
167 | #define BCMA_CC_FLASHCTL_AT_BUF2_PROGRAM 0x0289 |
168 | #define BCMA_CC_FLASHCTL_AT_PAGE_ERASE 0x0281 |
169 | #define BCMA_CC_FLASHCTL_AT_BLOCK_ERASE 0x0250 |
170 | #define BCMA_CC_FLASHCTL_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382 |
171 | #define BCMA_CC_FLASHCTL_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385 |
172 | #define BCMA_CC_FLASHCTL_AT_BUF1_LOAD 0x0253 |
173 | #define BCMA_CC_FLASHCTL_AT_BUF2_LOAD 0x0255 |
174 | #define BCMA_CC_FLASHCTL_AT_BUF1_COMPARE 0x0260 |
175 | #define BCMA_CC_FLASHCTL_AT_BUF2_COMPARE 0x0261 |
176 | #define BCMA_CC_FLASHCTL_AT_BUF1_REPROGRAM 0x0258 |
177 | #define BCMA_CC_FLASHCTL_AT_BUF2_REPROGRAM 0x0259 |
178 | #define BCMA_CC_FLASHADDR 0x0044 |
179 | #define BCMA_CC_FLASHDATA 0x0048 |
180 | /* Status register bits for ST flashes */ |
181 | #define BCMA_CC_FLASHDATA_ST_WIP 0x01 /* Write In Progress */ |
182 | #define BCMA_CC_FLASHDATA_ST_WEL 0x02 /* Write Enable Latch */ |
183 | #define BCMA_CC_FLASHDATA_ST_BP_MASK 0x1c /* Block Protect */ |
184 | #define BCMA_CC_FLASHDATA_ST_BP_SHIFT 2 |
185 | #define BCMA_CC_FLASHDATA_ST_SRWD 0x80 /* Status Register Write Disable */ |
186 | /* Status register bits for Atmel flashes */ |
187 | #define BCMA_CC_FLASHDATA_AT_READY 0x80 |
188 | #define BCMA_CC_FLASHDATA_AT_MISMATCH 0x40 |
189 | #define BCMA_CC_FLASHDATA_AT_ID_MASK 0x38 |
190 | #define BCMA_CC_FLASHDATA_AT_ID_SHIFT 3 |
191 | #define BCMA_CC_BCAST_ADDR 0x0050 |
192 | #define BCMA_CC_BCAST_DATA 0x0054 |
193 | #define BCMA_CC_GPIOPULLUP 0x0058 /* Rev >= 20 only */ |
194 | #define BCMA_CC_GPIOPULLDOWN 0x005C /* Rev >= 20 only */ |
195 | #define BCMA_CC_GPIOIN 0x0060 |
196 | #define BCMA_CC_GPIOOUT 0x0064 |
197 | #define BCMA_CC_GPIOOUTEN 0x0068 |
198 | #define BCMA_CC_GPIOCTL 0x006C |
199 | #define BCMA_CC_GPIOPOL 0x0070 |
200 | #define BCMA_CC_GPIOIRQ 0x0074 |
201 | #define BCMA_CC_WATCHDOG 0x0080 |
202 | #define BCMA_CC_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */ |
203 | #define BCMA_CC_GPIOTIMER_OFFTIME 0x0000FFFF |
204 | #define BCMA_CC_GPIOTIMER_OFFTIME_SHIFT 0 |
205 | #define BCMA_CC_GPIOTIMER_ONTIME 0xFFFF0000 |
206 | #define BCMA_CC_GPIOTIMER_ONTIME_SHIFT 16 |
207 | #define BCMA_CC_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */ |
208 | #define BCMA_CC_CLOCK_N 0x0090 |
209 | #define BCMA_CC_CLOCK_SB 0x0094 |
210 | #define BCMA_CC_CLOCK_PCI 0x0098 |
211 | #define BCMA_CC_CLOCK_M2 0x009C |
212 | #define BCMA_CC_CLOCK_MIPS 0x00A0 |
213 | #define BCMA_CC_CLKDIV 0x00A4 /* Rev >= 3 only */ |
214 | #define BCMA_CC_CLKDIV_SFLASH 0x0F000000 |
215 | #define BCMA_CC_CLKDIV_SFLASH_SHIFT 24 |
216 | #define BCMA_CC_CLKDIV_OTP 0x000F0000 |
217 | #define BCMA_CC_CLKDIV_OTP_SHIFT 16 |
218 | #define BCMA_CC_CLKDIV_JTAG 0x00000F00 |
219 | #define BCMA_CC_CLKDIV_JTAG_SHIFT 8 |
220 | #define BCMA_CC_CLKDIV_UART 0x000000FF |
221 | #define BCMA_CC_CAP_EXT 0x00AC /* Capabilities */ |
222 | #define BCMA_CC_CAP_EXT_SECI_PRESENT 0x00000001 |
223 | #define BCMA_CC_CAP_EXT_GSIO_PRESENT 0x00000002 |
224 | #define BCMA_CC_CAP_EXT_GCI_PRESENT 0x00000004 |
225 | #define BCMA_CC_CAP_EXT_SECI_PUART_PRESENT 0x00000008 /* UART present */ |
226 | #define BCMA_CC_CAP_EXT_AOB_PRESENT 0x00000040 |
227 | #define BCMA_CC_PLLONDELAY 0x00B0 /* Rev >= 4 only */ |
228 | #define BCMA_CC_FREFSELDELAY 0x00B4 /* Rev >= 4 only */ |
229 | #define BCMA_CC_SLOWCLKCTL 0x00B8 /* 6 <= Rev <= 9 only */ |
230 | #define BCMA_CC_SLOWCLKCTL_SRC 0x00000007 /* slow clock source mask */ |
231 | #define BCMA_CC_SLOWCLKCTL_SRC_LPO 0x00000000 /* source of slow clock is LPO */ |
232 | #define BCMA_CC_SLOWCLKCTL_SRC_XTAL 0x00000001 /* source of slow clock is crystal */ |
233 | #define BCMA_CC_SLOECLKCTL_SRC_PCI 0x00000002 /* source of slow clock is PCI */ |
234 | #define BCMA_CC_SLOWCLKCTL_LPOFREQ 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */ |
235 | #define BCMA_CC_SLOWCLKCTL_LPOPD 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */ |
236 | #define BCMA_CC_SLOWCLKCTL_FSLOW 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */ |
237 | #define BCMA_CC_SLOWCLKCTL_IPLL 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */ |
238 | #define BCMA_CC_SLOWCLKCTL_ENXTAL 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */ |
239 | #define BCMA_CC_SLOWCLKCTL_XTALPU 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */ |
240 | #define BCMA_CC_SLOWCLKCTL_CLKDIV 0xFFFF0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */ |
241 | #define BCMA_CC_SLOWCLKCTL_CLKDIV_SHIFT 16 |
242 | #define BCMA_CC_SYSCLKCTL 0x00C0 /* Rev >= 3 only */ |
243 | #define BCMA_CC_SYSCLKCTL_IDLPEN 0x00000001 /* ILPen: Enable Idle Low Power */ |
244 | #define BCMA_CC_SYSCLKCTL_ALPEN 0x00000002 /* ALPen: Enable Active Low Power */ |
245 | #define BCMA_CC_SYSCLKCTL_PLLEN 0x00000004 /* ForcePLLOn */ |
246 | #define BCMA_CC_SYSCLKCTL_FORCEALP 0x00000008 /* Force ALP (or HT if ALPen is not set */ |
247 | #define BCMA_CC_SYSCLKCTL_FORCEHT 0x00000010 /* Force HT */ |
248 | #define BCMA_CC_SYSCLKCTL_CLKDIV 0xFFFF0000 /* ClkDiv (ILP = 1/(4+divisor)) */ |
249 | #define BCMA_CC_SYSCLKCTL_CLKDIV_SHIFT 16 |
250 | #define BCMA_CC_CLKSTSTR 0x00C4 /* Rev >= 3 only */ |
251 | #define BCMA_CC_EROM 0x00FC |
252 | #define BCMA_CC_PCMCIA_CFG 0x0100 |
253 | #define BCMA_CC_PCMCIA_MEMWAIT 0x0104 |
254 | #define BCMA_CC_PCMCIA_ATTRWAIT 0x0108 |
255 | #define BCMA_CC_PCMCIA_IOWAIT 0x010C |
256 | #define BCMA_CC_IDE_CFG 0x0110 |
257 | #define BCMA_CC_IDE_MEMWAIT 0x0114 |
258 | #define BCMA_CC_IDE_ATTRWAIT 0x0118 |
259 | #define BCMA_CC_IDE_IOWAIT 0x011C |
260 | #define BCMA_CC_PROG_CFG 0x0120 |
261 | #define BCMA_CC_PROG_WAITCNT 0x0124 |
262 | #define BCMA_CC_FLASH_CFG 0x0128 |
263 | #define BCMA_CC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */ |
264 | #define BCMA_CC_FLASH_WAITCNT 0x012C |
265 | #define BCMA_CC_SROM_CONTROL 0x0190 |
266 | #define BCMA_CC_SROM_CONTROL_START 0x80000000 |
267 | #define BCMA_CC_SROM_CONTROL_BUSY 0x80000000 |
268 | #define BCMA_CC_SROM_CONTROL_OPCODE 0x60000000 |
269 | #define BCMA_CC_SROM_CONTROL_OP_READ 0x00000000 |
270 | #define BCMA_CC_SROM_CONTROL_OP_WRITE 0x20000000 |
271 | #define BCMA_CC_SROM_CONTROL_OP_WRDIS 0x40000000 |
272 | #define BCMA_CC_SROM_CONTROL_OP_WREN 0x60000000 |
273 | #define BCMA_CC_SROM_CONTROL_OTPSEL 0x00000010 |
274 | #define BCMA_CC_SROM_CONTROL_OTP_PRESENT 0x00000020 |
275 | #define BCMA_CC_SROM_CONTROL_LOCK 0x00000008 |
276 | #define BCMA_CC_SROM_CONTROL_SIZE_MASK 0x00000006 |
277 | #define BCMA_CC_SROM_CONTROL_SIZE_1K 0x00000000 |
278 | #define BCMA_CC_SROM_CONTROL_SIZE_4K 0x00000002 |
279 | #define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004 |
280 | #define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1 |
281 | #define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001 |
282 | /* Block 0x140 - 0x190 registers are chipset specific */ |
283 | #define BCMA_CC_4706_FLASHSCFG 0x18C /* Flash struct configuration */ |
284 | #define BCMA_CC_4706_FLASHSCFG_MASK 0x000000ff |
285 | #define BCMA_CC_4706_FLASHSCFG_SF1 0x00000001 /* 2nd serial flash present */ |
286 | #define BCMA_CC_4706_FLASHSCFG_PF1 0x00000002 /* 2nd parallel flash present */ |
287 | #define BCMA_CC_4706_FLASHSCFG_SF1_TYPE 0x00000004 /* 2nd serial flash type : 0 : ST, 1 : Atmel */ |
288 | #define BCMA_CC_4706_FLASHSCFG_NF1 0x00000008 /* 2nd NAND flash present */ |
289 | #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_MASK 0x000000f0 |
290 | #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_4MB 0x00000010 /* 4MB */ |
291 | #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_8MB 0x00000020 /* 8MB */ |
292 | #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_16MB 0x00000030 /* 16MB */ |
293 | #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_32MB 0x00000040 /* 32MB */ |
294 | #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_64MB 0x00000050 /* 64MB */ |
295 | #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_128MB 0x00000060 /* 128MB */ |
296 | #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_256MB 0x00000070 /* 256MB */ |
297 | /* NAND flash registers for BCM4706 (corerev = 31) */ |
298 | #define BCMA_CC_NFLASH_CTL 0x01A0 |
299 | #define BCMA_CC_NFLASH_CTL_ERR 0x08000000 |
300 | #define BCMA_CC_NFLASH_CONF 0x01A4 |
301 | #define BCMA_CC_NFLASH_COL_ADDR 0x01A8 |
302 | #define BCMA_CC_NFLASH_ROW_ADDR 0x01AC |
303 | #define BCMA_CC_NFLASH_DATA 0x01B0 |
304 | #define BCMA_CC_NFLASH_WAITCNT0 0x01B4 |
305 | /* 0x1E0 is defined as shared BCMA_CLKCTLST */ |
306 | #define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */ |
307 | #define BCMA_CC_UART0_DATA 0x0300 |
308 | #define BCMA_CC_UART0_IMR 0x0304 |
309 | #define BCMA_CC_UART0_FCR 0x0308 |
310 | #define BCMA_CC_UART0_LCR 0x030C |
311 | #define BCMA_CC_UART0_MCR 0x0310 |
312 | #define BCMA_CC_UART0_LSR 0x0314 |
313 | #define BCMA_CC_UART0_MSR 0x0318 |
314 | #define BCMA_CC_UART0_SCRATCH 0x031C |
315 | #define BCMA_CC_UART1_DATA 0x0400 |
316 | #define BCMA_CC_UART1_IMR 0x0404 |
317 | #define BCMA_CC_UART1_FCR 0x0408 |
318 | #define BCMA_CC_UART1_LCR 0x040C |
319 | #define BCMA_CC_UART1_MCR 0x0410 |
320 | #define BCMA_CC_UART1_LSR 0x0414 |
321 | #define BCMA_CC_UART1_MSR 0x0418 |
322 | #define BCMA_CC_UART1_SCRATCH 0x041C |
323 | /* PMU registers (rev >= 20) */ |
324 | #define BCMA_CC_PMU_CTL 0x0600 /* PMU control */ |
325 | #define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */ |
326 | #define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16 |
327 | #define BCMA_CC_PMU_CTL_RES 0x00006000 /* reset control mask */ |
328 | #define BCMA_CC_PMU_CTL_RES_SHIFT 13 |
329 | #define BCMA_CC_PMU_CTL_RES_RELOAD 0x2 /* reload POR values */ |
330 | #define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400 |
331 | #define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */ |
332 | #define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */ |
333 | #define BCMA_CC_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */ |
334 | #define BCMA_CC_PMU_CTL_XTALFREQ 0x0000007C /* Crystal freq */ |
335 | #define BCMA_CC_PMU_CTL_XTALFREQ_SHIFT 2 |
336 | #define BCMA_CC_PMU_CTL_ILPDIVEN 0x00000002 /* ILP div enable */ |
337 | #define BCMA_CC_PMU_CTL_LPOSEL 0x00000001 /* LPO sel */ |
338 | #define BCMA_CC_PMU_CAP 0x0604 /* PMU capabilities */ |
339 | #define BCMA_CC_PMU_CAP_REVISION 0x000000FF /* Revision mask */ |
340 | #define BCMA_CC_PMU_STAT 0x0608 /* PMU status */ |
341 | #define BCMA_CC_PMU_STAT_EXT_LPO_AVAIL 0x00000100 |
342 | #define BCMA_CC_PMU_STAT_WDRESET 0x00000080 |
343 | #define BCMA_CC_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */ |
344 | #define BCMA_CC_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */ |
345 | #define BCMA_CC_PMU_STAT_HAVEALP 0x00000008 /* ALP available */ |
346 | #define BCMA_CC_PMU_STAT_HAVEHT 0x00000004 /* HT available */ |
347 | #define BCMA_CC_PMU_STAT_RESINIT 0x00000003 /* Res init */ |
348 | #define BCMA_CC_PMU_RES_STAT 0x060C /* PMU res status */ |
349 | #define BCMA_CC_PMU_RES_PEND 0x0610 /* PMU res pending */ |
350 | #define BCMA_CC_PMU_TIMER 0x0614 /* PMU timer */ |
351 | #define BCMA_CC_PMU_MINRES_MSK 0x0618 /* PMU min res mask */ |
352 | #define BCMA_CC_PMU_MAXRES_MSK 0x061C /* PMU max res mask */ |
353 | #define BCMA_CC_PMU_RES_TABSEL 0x0620 /* PMU res table sel */ |
354 | #define BCMA_CC_PMU_RES_DEPMSK 0x0624 /* PMU res dep mask */ |
355 | #define BCMA_CC_PMU_RES_UPDNTM 0x0628 /* PMU res updown timer */ |
356 | #define BCMA_CC_PMU_RES_TIMER 0x062C /* PMU res timer */ |
357 | #define BCMA_CC_PMU_CLKSTRETCH 0x0630 /* PMU clockstretch */ |
358 | #define BCMA_CC_PMU_WATCHDOG 0x0634 /* PMU watchdog */ |
359 | #define BCMA_CC_PMU_RES_REQTS 0x0640 /* PMU res req timer sel */ |
360 | #define BCMA_CC_PMU_RES_REQT 0x0644 /* PMU res req timer */ |
361 | #define BCMA_CC_PMU_RES_REQM 0x0648 /* PMU res req mask */ |
362 | #define BCMA_CC_PMU_CHIPCTL_ADDR 0x0650 |
363 | #define BCMA_CC_PMU_CHIPCTL_DATA 0x0654 |
364 | #define BCMA_CC_PMU_REGCTL_ADDR 0x0658 |
365 | #define BCMA_CC_PMU_REGCTL_DATA 0x065C |
366 | #define BCMA_CC_PMU_PLLCTL_ADDR 0x0660 |
367 | #define BCMA_CC_PMU_PLLCTL_DATA 0x0664 |
368 | #define BCMA_CC_PMU_STRAPOPT 0x0668 /* (corerev >= 28) */ |
369 | #define BCMA_CC_PMU_XTAL_FREQ 0x066C /* (pmurev >= 10) */ |
370 | #define BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK 0x00001FFF |
371 | #define BCMA_CC_PMU_XTAL_FREQ_MEASURE_MASK 0x80000000 |
372 | #define BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT 31 |
373 | #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */ |
374 | /* NAND flash MLC controller registers (corerev >= 38) */ |
375 | #define BCMA_CC_NAND_REVISION 0x0C00 |
376 | #define BCMA_CC_NAND_CMD_START 0x0C04 |
377 | #define BCMA_CC_NAND_CMD_ADDR_X 0x0C08 |
378 | #define BCMA_CC_NAND_CMD_ADDR 0x0C0C |
379 | #define BCMA_CC_NAND_CMD_END_ADDR 0x0C10 |
380 | #define BCMA_CC_NAND_CS_NAND_SELECT 0x0C14 |
381 | #define BCMA_CC_NAND_CS_NAND_XOR 0x0C18 |
382 | #define BCMA_CC_NAND_SPARE_RD0 0x0C20 |
383 | #define BCMA_CC_NAND_SPARE_RD4 0x0C24 |
384 | #define BCMA_CC_NAND_SPARE_RD8 0x0C28 |
385 | #define BCMA_CC_NAND_SPARE_RD12 0x0C2C |
386 | #define BCMA_CC_NAND_SPARE_WR0 0x0C30 |
387 | #define BCMA_CC_NAND_SPARE_WR4 0x0C34 |
388 | #define BCMA_CC_NAND_SPARE_WR8 0x0C38 |
389 | #define BCMA_CC_NAND_SPARE_WR12 0x0C3C |
390 | #define BCMA_CC_NAND_ACC_CONTROL 0x0C40 |
391 | #define BCMA_CC_NAND_CONFIG 0x0C48 |
392 | #define BCMA_CC_NAND_TIMING_1 0x0C50 |
393 | #define BCMA_CC_NAND_TIMING_2 0x0C54 |
394 | #define BCMA_CC_NAND_SEMAPHORE 0x0C58 |
395 | #define BCMA_CC_NAND_DEVID 0x0C60 |
396 | #define BCMA_CC_NAND_DEVID_X 0x0C64 |
397 | #define BCMA_CC_NAND_BLOCK_LOCK_STATUS 0x0C68 |
398 | #define BCMA_CC_NAND_INTFC_STATUS 0x0C6C |
399 | #define BCMA_CC_NAND_ECC_CORR_ADDR_X 0x0C70 |
400 | #define BCMA_CC_NAND_ECC_CORR_ADDR 0x0C74 |
401 | #define BCMA_CC_NAND_ECC_UNC_ADDR_X 0x0C78 |
402 | #define BCMA_CC_NAND_ECC_UNC_ADDR 0x0C7C |
403 | #define BCMA_CC_NAND_READ_ERROR_COUNT 0x0C80 |
404 | #define BCMA_CC_NAND_CORR_STAT_THRESHOLD 0x0C84 |
405 | #define BCMA_CC_NAND_READ_ADDR_X 0x0C90 |
406 | #define BCMA_CC_NAND_READ_ADDR 0x0C94 |
407 | #define BCMA_CC_NAND_PAGE_PROGRAM_ADDR_X 0x0C98 |
408 | #define BCMA_CC_NAND_PAGE_PROGRAM_ADDR 0x0C9C |
409 | #define BCMA_CC_NAND_COPY_BACK_ADDR_X 0x0CA0 |
410 | #define BCMA_CC_NAND_COPY_BACK_ADDR 0x0CA4 |
411 | #define BCMA_CC_NAND_BLOCK_ERASE_ADDR_X 0x0CA8 |
412 | #define BCMA_CC_NAND_BLOCK_ERASE_ADDR 0x0CAC |
413 | #define BCMA_CC_NAND_INV_READ_ADDR_X 0x0CB0 |
414 | #define BCMA_CC_NAND_INV_READ_ADDR 0x0CB4 |
415 | #define BCMA_CC_NAND_BLK_WR_PROTECT 0x0CC0 |
416 | #define BCMA_CC_NAND_ACC_CONTROL_CS1 0x0CD0 |
417 | #define BCMA_CC_NAND_CONFIG_CS1 0x0CD4 |
418 | #define BCMA_CC_NAND_TIMING_1_CS1 0x0CD8 |
419 | #define BCMA_CC_NAND_TIMING_2_CS1 0x0CDC |
420 | #define BCMA_CC_NAND_SPARE_RD16 0x0D30 |
421 | #define BCMA_CC_NAND_SPARE_RD20 0x0D34 |
422 | #define BCMA_CC_NAND_SPARE_RD24 0x0D38 |
423 | #define BCMA_CC_NAND_SPARE_RD28 0x0D3C |
424 | #define BCMA_CC_NAND_CACHE_ADDR 0x0D40 |
425 | #define BCMA_CC_NAND_CACHE_DATA 0x0D44 |
426 | #define BCMA_CC_NAND_CTRL_CONFIG 0x0D48 |
427 | #define BCMA_CC_NAND_CTRL_STATUS 0x0D4C |
428 | |
429 | /* Divider allocation in 4716/47162/5356 */ |
430 | #define BCMA_CC_PMU5_MAINPLL_CPU 1 |
431 | #define BCMA_CC_PMU5_MAINPLL_MEM 2 |
432 | #define BCMA_CC_PMU5_MAINPLL_SSB 3 |
433 | |
434 | /* PLL usage in 4716/47162 */ |
435 | #define BCMA_CC_PMU4716_MAINPLL_PLL0 12 |
436 | |
437 | /* PLL usage in 5356/5357 */ |
438 | #define BCMA_CC_PMU5356_MAINPLL_PLL0 0 |
439 | #define BCMA_CC_PMU5357_MAINPLL_PLL0 0 |
440 | |
441 | /* 4706 PMU */ |
442 | #define BCMA_CC_PMU4706_MAINPLL_PLL0 0 |
443 | #define BCMA_CC_PMU6_4706_PROCPLL_OFF 4 /* The CPU PLL */ |
444 | #define BCMA_CC_PMU6_4706_PROC_P2DIV_MASK 0x000f0000 |
445 | #define BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT 16 |
446 | #define BCMA_CC_PMU6_4706_PROC_P1DIV_MASK 0x0000f000 |
447 | #define BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT 12 |
448 | #define BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK 0x00000ff8 |
449 | #define BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT 3 |
450 | #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007 |
451 | #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0 |
452 | |
453 | /* PMU rev 15 */ |
454 | #define BCMA_CC_PMU15_PLL_PLLCTL0 0 |
455 | #define BCMA_CC_PMU15_PLL_PC0_CLKSEL_MASK 0x00000003 |
456 | #define BCMA_CC_PMU15_PLL_PC0_CLKSEL_SHIFT 0 |
457 | #define BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK 0x003FFFFC |
458 | #define BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT 2 |
459 | #define BCMA_CC_PMU15_PLL_PC0_PRESCALE_MASK 0x00C00000 |
460 | #define BCMA_CC_PMU15_PLL_PC0_PRESCALE_SHIFT 22 |
461 | #define BCMA_CC_PMU15_PLL_PC0_KPCTRL_MASK 0x07000000 |
462 | #define BCMA_CC_PMU15_PLL_PC0_KPCTRL_SHIFT 24 |
463 | #define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_MASK 0x38000000 |
464 | #define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_SHIFT 27 |
465 | #define BCMA_CC_PMU15_PLL_PC0_FDCMODE_MASK 0x40000000 |
466 | #define BCMA_CC_PMU15_PLL_PC0_FDCMODE_SHIFT 30 |
467 | #define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_MASK 0x80000000 |
468 | #define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_SHIFT 31 |
469 | |
470 | /* ALP clock on pre-PMU chips */ |
471 | #define BCMA_CC_PMU_ALP_CLOCK 20000000 |
472 | /* HT clock for systems with PMU-enabled chipcommon */ |
473 | #define BCMA_CC_PMU_HT_CLOCK 80000000 |
474 | |
475 | /* PMU rev 5 (& 6) */ |
476 | #define BCMA_CC_PPL_P1P2_OFF 0 |
477 | #define BCMA_CC_PPL_P1_MASK 0x0f000000 |
478 | #define BCMA_CC_PPL_P1_SHIFT 24 |
479 | #define BCMA_CC_PPL_P2_MASK 0x00f00000 |
480 | #define BCMA_CC_PPL_P2_SHIFT 20 |
481 | #define BCMA_CC_PPL_M14_OFF 1 |
482 | #define BCMA_CC_PPL_MDIV_MASK 0x000000ff |
483 | #define BCMA_CC_PPL_MDIV_WIDTH 8 |
484 | #define BCMA_CC_PPL_NM5_OFF 2 |
485 | #define BCMA_CC_PPL_NDIV_MASK 0xfff00000 |
486 | #define BCMA_CC_PPL_NDIV_SHIFT 20 |
487 | #define BCMA_CC_PPL_FMAB_OFF 3 |
488 | #define BCMA_CC_PPL_MRAT_MASK 0xf0000000 |
489 | #define BCMA_CC_PPL_MRAT_SHIFT 28 |
490 | #define BCMA_CC_PPL_ABRAT_MASK 0x08000000 |
491 | #define BCMA_CC_PPL_ABRAT_SHIFT 27 |
492 | #define BCMA_CC_PPL_FDIV_MASK 0x07ffffff |
493 | #define BCMA_CC_PPL_PLLCTL_OFF 4 |
494 | #define BCMA_CC_PPL_PCHI_OFF 5 |
495 | #define BCMA_CC_PPL_PCHI_MASK 0x0000003f |
496 | |
497 | #define BCMA_CC_PMU_PLL_CTL0 0 |
498 | #define BCMA_CC_PMU_PLL_CTL1 1 |
499 | #define BCMA_CC_PMU_PLL_CTL2 2 |
500 | #define BCMA_CC_PMU_PLL_CTL3 3 |
501 | #define BCMA_CC_PMU_PLL_CTL4 4 |
502 | #define BCMA_CC_PMU_PLL_CTL5 5 |
503 | |
504 | #define BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000 |
505 | #define BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT 20 |
506 | |
507 | #define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000 |
508 | #define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT 20 |
509 | |
510 | #define BCMA_CCB_MII_MNG_CTL 0x0000 |
511 | #define BCMA_CCB_MII_MNG_CMD_DATA 0x0004 |
512 | |
513 | /* BCM4331 ChipControl numbers. */ |
514 | #define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */ |
515 | #define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */ |
516 | #define BCMA_CHIPCTL_4331_EXT_LNA BIT(2) /* 0 disable */ |
517 | #define BCMA_CHIPCTL_4331_SPROM_GPIO13_15 BIT(3) /* sprom/gpio13-15 mux */ |
518 | #define BCMA_CHIPCTL_4331_EXTPA_EN BIT(4) /* 0 ext pa disable, 1 ext pa enabled */ |
519 | #define BCMA_CHIPCTL_4331_GPIOCLK_ON_SPROMCS BIT(5) /* set drive out GPIO_CLK on sprom_cs pin */ |
520 | #define BCMA_CHIPCTL_4331_PCIE_MDIO_ON_SPROMCS BIT(6) /* use sprom_cs pin as PCIE mdio interface */ |
521 | #define BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5 BIT(7) /* aband extpa will be at gpio2/5 and sprom_dout */ |
522 | #define BCMA_CHIPCTL_4331_OVR_PIPEAUXCLKEN BIT(8) /* override core control on pipe_AuxClkEnable */ |
523 | #define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN BIT(9) /* override core control on pipe_AuxPowerDown */ |
524 | #define BCMA_CHIPCTL_4331_PCIE_AUXCLKEN BIT(10) /* pcie_auxclkenable */ |
525 | #define BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN BIT(11) /* pcie_pipe_pllpowerdown */ |
526 | #define BCMA_CHIPCTL_4331_EXTPA_EN2 BIT(12) /* 0 ext pa disable, 1 ext pa enabled */ |
527 | #define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4 BIT(16) /* enable bt_shd0 at gpio4 */ |
528 | #define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5 BIT(17) /* enable bt_shd1 at gpio5 */ |
529 | |
530 | /* 43224 chip-specific ChipControl register bits */ |
531 | #define BCMA_CCTRL_43224_GPIO_TOGGLE 0x8000 /* gpio[3:0] pins as btcoex or s/w gpio */ |
532 | #define BCMA_CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */ |
533 | #define BCMA_CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */ |
534 | |
535 | /* 4313 Chip specific ChipControl register bits */ |
536 | #define BCMA_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */ |
537 | |
538 | /* BCM5357 ChipControl register bits */ |
539 | #define BCMA_CHIPCTL_5357_EXTPA BIT(14) |
540 | #define BCMA_CHIPCTL_5357_ANT_MUX_2O3 BIT(15) |
541 | #define BCMA_CHIPCTL_5357_NFLASH BIT(16) |
542 | #define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18) |
543 | #define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19) |
544 | |
545 | #define BCMA_RES_4314_LPLDO_PU BIT(0) |
546 | #define BCMA_RES_4314_PMU_SLEEP_DIS BIT(1) |
547 | #define BCMA_RES_4314_PMU_BG_PU BIT(2) |
548 | #define BCMA_RES_4314_CBUCK_LPOM_PU BIT(3) |
549 | #define BCMA_RES_4314_CBUCK_PFM_PU BIT(4) |
550 | #define BCMA_RES_4314_CLDO_PU BIT(5) |
551 | #define BCMA_RES_4314_LPLDO2_LVM BIT(6) |
552 | #define BCMA_RES_4314_WL_PMU_PU BIT(7) |
553 | #define BCMA_RES_4314_LNLDO_PU BIT(8) |
554 | #define BCMA_RES_4314_LDO3P3_PU BIT(9) |
555 | #define BCMA_RES_4314_OTP_PU BIT(10) |
556 | #define BCMA_RES_4314_XTAL_PU BIT(11) |
557 | #define BCMA_RES_4314_WL_PWRSW_PU BIT(12) |
558 | #define BCMA_RES_4314_LQ_AVAIL BIT(13) |
559 | #define BCMA_RES_4314_LOGIC_RET BIT(14) |
560 | #define BCMA_RES_4314_MEM_SLEEP BIT(15) |
561 | #define BCMA_RES_4314_MACPHY_RET BIT(16) |
562 | #define BCMA_RES_4314_WL_CORE_READY BIT(17) |
563 | #define BCMA_RES_4314_ILP_REQ BIT(18) |
564 | #define BCMA_RES_4314_ALP_AVAIL BIT(19) |
565 | #define BCMA_RES_4314_MISC_PWRSW_PU BIT(20) |
566 | #define BCMA_RES_4314_SYNTH_PWRSW_PU BIT(21) |
567 | #define BCMA_RES_4314_RX_PWRSW_PU BIT(22) |
568 | #define BCMA_RES_4314_RADIO_PU BIT(23) |
569 | #define BCMA_RES_4314_VCO_LDO_PU BIT(24) |
570 | #define BCMA_RES_4314_AFE_LDO_PU BIT(25) |
571 | #define BCMA_RES_4314_RX_LDO_PU BIT(26) |
572 | #define BCMA_RES_4314_TX_LDO_PU BIT(27) |
573 | #define BCMA_RES_4314_HT_AVAIL BIT(28) |
574 | #define BCMA_RES_4314_MACPHY_CLK_AVAIL BIT(29) |
575 | |
576 | /* Data for the PMU, if available. |
577 | * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU) |
578 | */ |
579 | struct bcma_chipcommon_pmu { |
580 | struct bcma_device *core; /* Can be separated core or just ChipCommon one */ |
581 | u8 rev; /* PMU revision */ |
582 | u32 crystalfreq; /* The active crystal frequency (in kHz) */ |
583 | }; |
584 | |
585 | #ifdef CONFIG_BCMA_PFLASH |
586 | struct bcma_pflash { |
587 | bool present; |
588 | }; |
589 | #endif |
590 | |
591 | #ifdef CONFIG_BCMA_SFLASH |
592 | struct mtd_info; |
593 | |
594 | struct bcma_sflash { |
595 | bool present; |
596 | u32 blocksize; |
597 | u16 numblocks; |
598 | u32 size; |
599 | }; |
600 | #endif |
601 | |
602 | #ifdef CONFIG_BCMA_NFLASH |
603 | struct bcma_nflash { |
604 | /* Must be the fist member for the brcmnand driver to |
605 | * de-reference that structure. |
606 | */ |
607 | struct brcmnand_platform_data brcmnand_info; |
608 | bool present; |
609 | bool boot; /* This is the flash the SoC boots from */ |
610 | }; |
611 | #endif |
612 | |
613 | #ifdef CONFIG_BCMA_DRIVER_MIPS |
614 | struct bcma_serial_port { |
615 | void *regs; |
616 | unsigned long clockspeed; |
617 | unsigned int irq; |
618 | unsigned int baud_base; |
619 | unsigned int reg_shift; |
620 | }; |
621 | #endif /* CONFIG_BCMA_DRIVER_MIPS */ |
622 | |
623 | struct bcma_drv_cc { |
624 | struct bcma_device *core; |
625 | u32 status; |
626 | u32 capabilities; |
627 | u32 capabilities_ext; |
628 | u8 setup_done:1; |
629 | u8 early_setup_done:1; |
630 | /* Fast Powerup Delay constant */ |
631 | u16 fast_pwrup_delay; |
632 | struct bcma_chipcommon_pmu pmu; |
633 | #ifdef CONFIG_BCMA_PFLASH |
634 | struct bcma_pflash pflash; |
635 | #endif |
636 | #ifdef CONFIG_BCMA_SFLASH |
637 | struct bcma_sflash sflash; |
638 | #endif |
639 | #ifdef CONFIG_BCMA_NFLASH |
640 | struct bcma_nflash nflash; |
641 | #endif |
642 | |
643 | #ifdef CONFIG_BCMA_DRIVER_MIPS |
644 | int nr_serial_ports; |
645 | struct bcma_serial_port serial_ports[4]; |
646 | #endif /* CONFIG_BCMA_DRIVER_MIPS */ |
647 | u32 ticks_per_ms; |
648 | struct platform_device *watchdog; |
649 | |
650 | /* Lock for GPIO register access. */ |
651 | spinlock_t gpio_lock; |
652 | #ifdef CONFIG_BCMA_DRIVER_GPIO |
653 | struct gpio_chip gpio; |
654 | #endif |
655 | }; |
656 | |
657 | struct bcma_drv_cc_b { |
658 | struct bcma_device *core; |
659 | u8 setup_done:1; |
660 | void __iomem *mii; |
661 | }; |
662 | |
663 | /* Register access */ |
664 | #define bcma_cc_read32(cc, offset) \ |
665 | bcma_read32((cc)->core, offset) |
666 | #define bcma_cc_write32(cc, offset, val) \ |
667 | bcma_write32((cc)->core, offset, val) |
668 | |
669 | #define bcma_cc_mask32(cc, offset, mask) \ |
670 | bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) & (mask)) |
671 | #define bcma_cc_set32(cc, offset, set) \ |
672 | bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) | (set)) |
673 | #define bcma_cc_maskset32(cc, offset, mask, set) \ |
674 | bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set)) |
675 | |
676 | /* PMU registers access */ |
677 | #define bcma_pmu_read32(cc, offset) \ |
678 | bcma_read32((cc)->pmu.core, offset) |
679 | #define bcma_pmu_write32(cc, offset, val) \ |
680 | bcma_write32((cc)->pmu.core, offset, val) |
681 | |
682 | #define bcma_pmu_mask32(cc, offset, mask) \ |
683 | bcma_pmu_write32(cc, offset, bcma_pmu_read32(cc, offset) & (mask)) |
684 | #define bcma_pmu_set32(cc, offset, set) \ |
685 | bcma_pmu_write32(cc, offset, bcma_pmu_read32(cc, offset) | (set)) |
686 | #define bcma_pmu_maskset32(cc, offset, mask, set) \ |
687 | bcma_pmu_write32(cc, offset, (bcma_pmu_read32(cc, offset) & (mask)) | (set)) |
688 | |
689 | extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks); |
690 | |
691 | extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc); |
692 | |
693 | void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value); |
694 | |
695 | u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask); |
696 | |
697 | /* Chipcommon GPIO pin access. */ |
698 | u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask); |
699 | u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value); |
700 | u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value); |
701 | u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value); |
702 | u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value); |
703 | u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value); |
704 | u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value); |
705 | u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value); |
706 | |
707 | /* PMU support */ |
708 | extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, |
709 | u32 value); |
710 | extern void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, |
711 | u32 mask, u32 set); |
712 | extern void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc, |
713 | u32 offset, u32 mask, u32 set); |
714 | extern void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, |
715 | u32 offset, u32 mask, u32 set); |
716 | extern void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid); |
717 | |
718 | extern u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc); |
719 | |
720 | void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value); |
721 | |
722 | #endif /* LINUX_BCMA_DRIVER_CC_H_ */ |
723 | |