1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
5 */
6#ifndef __LINUX_CLK_PROVIDER_H
7#define __LINUX_CLK_PROVIDER_H
8
9#include <linux/io.h>
10#include <linux/of.h>
11#include <linux/of_clk.h>
12
13#ifdef CONFIG_COMMON_CLK
14
15/*
16 * flags used across common struct clk. these flags should only affect the
17 * top-level framework. custom flags for dealing with hardware specifics
18 * belong in struct clk_foo
19 *
20 * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
21 */
22#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
23#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
24#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
25#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
26 /* unused */
27#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
28#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
29#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
30#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
31#define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
32#define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
33#define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
34/* parents need enable during gate/ungate, set rate and re-parent */
35#define CLK_OPS_PARENT_ENABLE BIT(12)
36/* duty cycle call may be forwarded to the parent clock */
37#define CLK_DUTY_CYCLE_PARENT BIT(13)
38
39struct clk;
40struct clk_hw;
41struct clk_core;
42struct dentry;
43
44/**
45 * struct clk_rate_request - Structure encoding the clk constraints that
46 * a clock user might require.
47 *
48 * @rate: Requested clock rate. This field will be adjusted by
49 * clock drivers according to hardware capabilities.
50 * @min_rate: Minimum rate imposed by clk users.
51 * @max_rate: Maximum rate imposed by clk users.
52 * @best_parent_rate: The best parent rate a parent can provide to fulfill the
53 * requested constraints.
54 * @best_parent_hw: The most appropriate parent clock that fulfills the
55 * requested constraints.
56 *
57 */
58struct clk_rate_request {
59 unsigned long rate;
60 unsigned long min_rate;
61 unsigned long max_rate;
62 unsigned long best_parent_rate;
63 struct clk_hw *best_parent_hw;
64};
65
66/**
67 * struct clk_duty - Struture encoding the duty cycle ratio of a clock
68 *
69 * @num: Numerator of the duty cycle ratio
70 * @den: Denominator of the duty cycle ratio
71 */
72struct clk_duty {
73 unsigned int num;
74 unsigned int den;
75};
76
77/**
78 * struct clk_ops - Callback operations for hardware clocks; these are to
79 * be provided by the clock implementation, and will be called by drivers
80 * through the clk_* api.
81 *
82 * @prepare: Prepare the clock for enabling. This must not return until
83 * the clock is fully prepared, and it's safe to call clk_enable.
84 * This callback is intended to allow clock implementations to
85 * do any initialisation that may sleep. Called with
86 * prepare_lock held.
87 *
88 * @unprepare: Release the clock from its prepared state. This will typically
89 * undo any work done in the @prepare callback. Called with
90 * prepare_lock held.
91 *
92 * @is_prepared: Queries the hardware to determine if the clock is prepared.
93 * This function is allowed to sleep. Optional, if this op is not
94 * set then the prepare count will be used.
95 *
96 * @unprepare_unused: Unprepare the clock atomically. Only called from
97 * clk_disable_unused for prepare clocks with special needs.
98 * Called with prepare mutex held. This function may sleep.
99 *
100 * @enable: Enable the clock atomically. This must not return until the
101 * clock is generating a valid clock signal, usable by consumer
102 * devices. Called with enable_lock held. This function must not
103 * sleep.
104 *
105 * @disable: Disable the clock atomically. Called with enable_lock held.
106 * This function must not sleep.
107 *
108 * @is_enabled: Queries the hardware to determine if the clock is enabled.
109 * This function must not sleep. Optional, if this op is not
110 * set then the enable count will be used.
111 *
112 * @disable_unused: Disable the clock atomically. Only called from
113 * clk_disable_unused for gate clocks with special needs.
114 * Called with enable_lock held. This function must not
115 * sleep.
116 *
117 * @save_context: Save the context of the clock in prepration for poweroff.
118 *
119 * @restore_context: Restore the context of the clock after a restoration
120 * of power.
121 *
122 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The
123 * parent rate is an input parameter. It is up to the caller to
124 * ensure that the prepare_mutex is held across this call.
125 * Returns the calculated rate. Optional, but recommended - if
126 * this op is not set then clock rate will be initialized to 0.
127 *
128 * @round_rate: Given a target rate as input, returns the closest rate actually
129 * supported by the clock. The parent rate is an input/output
130 * parameter.
131 *
132 * @determine_rate: Given a target rate as input, returns the closest rate
133 * actually supported by the clock, and optionally the parent clock
134 * that should be used to provide the clock rate.
135 *
136 * @set_parent: Change the input source of this clock; for clocks with multiple
137 * possible parents specify a new parent by passing in the index
138 * as a u8 corresponding to the parent in either the .parent_names
139 * or .parents arrays. This function in affect translates an
140 * array index into the value programmed into the hardware.
141 * Returns 0 on success, -EERROR otherwise.
142 *
143 * @get_parent: Queries the hardware to determine the parent of a clock. The
144 * return value is a u8 which specifies the index corresponding to
145 * the parent clock. This index can be applied to either the
146 * .parent_names or .parents arrays. In short, this function
147 * translates the parent value read from hardware into an array
148 * index. Currently only called when the clock is initialized by
149 * __clk_init. This callback is mandatory for clocks with
150 * multiple parents. It is optional (and unnecessary) for clocks
151 * with 0 or 1 parents.
152 *
153 * @set_rate: Change the rate of this clock. The requested rate is specified
154 * by the second argument, which should typically be the return
155 * of .round_rate call. The third argument gives the parent rate
156 * which is likely helpful for most .set_rate implementation.
157 * Returns 0 on success, -EERROR otherwise.
158 *
159 * @set_rate_and_parent: Change the rate and the parent of this clock. The
160 * requested rate is specified by the second argument, which
161 * should typically be the return of .round_rate call. The
162 * third argument gives the parent rate which is likely helpful
163 * for most .set_rate_and_parent implementation. The fourth
164 * argument gives the parent index. This callback is optional (and
165 * unnecessary) for clocks with 0 or 1 parents as well as
166 * for clocks that can tolerate switching the rate and the parent
167 * separately via calls to .set_parent and .set_rate.
168 * Returns 0 on success, -EERROR otherwise.
169 *
170 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
171 * is expressed in ppb (parts per billion). The parent accuracy is
172 * an input parameter.
173 * Returns the calculated accuracy. Optional - if this op is not
174 * set then clock accuracy will be initialized to parent accuracy
175 * or 0 (perfect clock) if clock has no parent.
176 *
177 * @get_phase: Queries the hardware to get the current phase of a clock.
178 * Returned values are 0-359 degrees on success, negative
179 * error codes on failure.
180 *
181 * @set_phase: Shift the phase this clock signal in degrees specified
182 * by the second argument. Valid values for degrees are
183 * 0-359. Return 0 on success, otherwise -EERROR.
184 *
185 * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio
186 * of a clock. Returned values denominator cannot be 0 and must be
187 * superior or equal to the numerator.
188 *
189 * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by
190 * the numerator (2nd argurment) and denominator (3rd argument).
191 * Argument must be a valid ratio (denominator > 0
192 * and >= numerator) Return 0 on success, otherwise -EERROR.
193 *
194 * @init: Perform platform-specific initialization magic.
195 * This is not not used by any of the basic clock types.
196 * Please consider other ways of solving initialization problems
197 * before using this callback, as its use is discouraged.
198 *
199 * @debug_init: Set up type-specific debugfs entries for this clock. This
200 * is called once, after the debugfs directory entry for this
201 * clock has been created. The dentry pointer representing that
202 * directory is provided as an argument. Called with
203 * prepare_lock held. Returns 0 on success, -EERROR otherwise.
204 *
205 *
206 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
207 * implementations to split any work between atomic (enable) and sleepable
208 * (prepare) contexts. If enabling a clock requires code that might sleep,
209 * this must be done in clk_prepare. Clock enable code that will never be
210 * called in a sleepable context may be implemented in clk_enable.
211 *
212 * Typically, drivers will call clk_prepare when a clock may be needed later
213 * (eg. when a device is opened), and clk_enable when the clock is actually
214 * required (eg. from an interrupt). Note that clk_prepare MUST have been
215 * called before clk_enable.
216 */
217struct clk_ops {
218 int (*prepare)(struct clk_hw *hw);
219 void (*unprepare)(struct clk_hw *hw);
220 int (*is_prepared)(struct clk_hw *hw);
221 void (*unprepare_unused)(struct clk_hw *hw);
222 int (*enable)(struct clk_hw *hw);
223 void (*disable)(struct clk_hw *hw);
224 int (*is_enabled)(struct clk_hw *hw);
225 void (*disable_unused)(struct clk_hw *hw);
226 int (*save_context)(struct clk_hw *hw);
227 void (*restore_context)(struct clk_hw *hw);
228 unsigned long (*recalc_rate)(struct clk_hw *hw,
229 unsigned long parent_rate);
230 long (*round_rate)(struct clk_hw *hw, unsigned long rate,
231 unsigned long *parent_rate);
232 int (*determine_rate)(struct clk_hw *hw,
233 struct clk_rate_request *req);
234 int (*set_parent)(struct clk_hw *hw, u8 index);
235 u8 (*get_parent)(struct clk_hw *hw);
236 int (*set_rate)(struct clk_hw *hw, unsigned long rate,
237 unsigned long parent_rate);
238 int (*set_rate_and_parent)(struct clk_hw *hw,
239 unsigned long rate,
240 unsigned long parent_rate, u8 index);
241 unsigned long (*recalc_accuracy)(struct clk_hw *hw,
242 unsigned long parent_accuracy);
243 int (*get_phase)(struct clk_hw *hw);
244 int (*set_phase)(struct clk_hw *hw, int degrees);
245 int (*get_duty_cycle)(struct clk_hw *hw,
246 struct clk_duty *duty);
247 int (*set_duty_cycle)(struct clk_hw *hw,
248 struct clk_duty *duty);
249 void (*init)(struct clk_hw *hw);
250 void (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
251};
252
253/**
254 * struct clk_init_data - holds init data that's common to all clocks and is
255 * shared between the clock provider and the common clock framework.
256 *
257 * @name: clock name
258 * @ops: operations this clock supports
259 * @parent_names: array of string names for all possible parents
260 * @num_parents: number of possible parents
261 * @flags: framework-level hints and quirks
262 */
263struct clk_init_data {
264 const char *name;
265 const struct clk_ops *ops;
266 const char * const *parent_names;
267 u8 num_parents;
268 unsigned long flags;
269};
270
271/**
272 * struct clk_hw - handle for traversing from a struct clk to its corresponding
273 * hardware-specific structure. struct clk_hw should be declared within struct
274 * clk_foo and then referenced by the struct clk instance that uses struct
275 * clk_foo's clk_ops
276 *
277 * @core: pointer to the struct clk_core instance that points back to this
278 * struct clk_hw instance
279 *
280 * @clk: pointer to the per-user struct clk instance that can be used to call
281 * into the clk API
282 *
283 * @init: pointer to struct clk_init_data that contains the init data shared
284 * with the common clock framework.
285 */
286struct clk_hw {
287 struct clk_core *core;
288 struct clk *clk;
289 const struct clk_init_data *init;
290};
291
292/*
293 * DOC: Basic clock implementations common to many platforms
294 *
295 * Each basic clock hardware type is comprised of a structure describing the
296 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
297 * unique flags for that hardware type, a registration function and an
298 * alternative macro for static initialization
299 */
300
301/**
302 * struct clk_fixed_rate - fixed-rate clock
303 * @hw: handle between common and hardware-specific interfaces
304 * @fixed_rate: constant frequency of clock
305 */
306struct clk_fixed_rate {
307 struct clk_hw hw;
308 unsigned long fixed_rate;
309 unsigned long fixed_accuracy;
310 u8 flags;
311};
312
313#define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw)
314
315extern const struct clk_ops clk_fixed_rate_ops;
316struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
317 const char *parent_name, unsigned long flags,
318 unsigned long fixed_rate);
319struct clk_hw *clk_hw_register_fixed_rate(struct device *dev, const char *name,
320 const char *parent_name, unsigned long flags,
321 unsigned long fixed_rate);
322struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev,
323 const char *name, const char *parent_name, unsigned long flags,
324 unsigned long fixed_rate, unsigned long fixed_accuracy);
325void clk_unregister_fixed_rate(struct clk *clk);
326struct clk_hw *clk_hw_register_fixed_rate_with_accuracy(struct device *dev,
327 const char *name, const char *parent_name, unsigned long flags,
328 unsigned long fixed_rate, unsigned long fixed_accuracy);
329void clk_hw_unregister_fixed_rate(struct clk_hw *hw);
330
331void of_fixed_clk_setup(struct device_node *np);
332
333/**
334 * struct clk_gate - gating clock
335 *
336 * @hw: handle between common and hardware-specific interfaces
337 * @reg: register controlling gate
338 * @bit_idx: single bit controlling gate
339 * @flags: hardware-specific flags
340 * @lock: register lock
341 *
342 * Clock which can gate its output. Implements .enable & .disable
343 *
344 * Flags:
345 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
346 * enable the clock. Setting this flag does the opposite: setting the bit
347 * disable the clock and clearing it enables the clock
348 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
349 * of this register, and mask of gate bits are in higher 16-bit of this
350 * register. While setting the gate bits, higher 16-bit should also be
351 * updated to indicate changing gate bits.
352 */
353struct clk_gate {
354 struct clk_hw hw;
355 void __iomem *reg;
356 u8 bit_idx;
357 u8 flags;
358 spinlock_t *lock;
359};
360
361#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
362
363#define CLK_GATE_SET_TO_DISABLE BIT(0)
364#define CLK_GATE_HIWORD_MASK BIT(1)
365
366extern const struct clk_ops clk_gate_ops;
367struct clk *clk_register_gate(struct device *dev, const char *name,
368 const char *parent_name, unsigned long flags,
369 void __iomem *reg, u8 bit_idx,
370 u8 clk_gate_flags, spinlock_t *lock);
371struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name,
372 const char *parent_name, unsigned long flags,
373 void __iomem *reg, u8 bit_idx,
374 u8 clk_gate_flags, spinlock_t *lock);
375void clk_unregister_gate(struct clk *clk);
376void clk_hw_unregister_gate(struct clk_hw *hw);
377int clk_gate_is_enabled(struct clk_hw *hw);
378
379struct clk_div_table {
380 unsigned int val;
381 unsigned int div;
382};
383
384/**
385 * struct clk_divider - adjustable divider clock
386 *
387 * @hw: handle between common and hardware-specific interfaces
388 * @reg: register containing the divider
389 * @shift: shift to the divider bit field
390 * @width: width of the divider bit field
391 * @table: array of value/divider pairs, last entry should have div = 0
392 * @lock: register lock
393 *
394 * Clock with an adjustable divider affecting its output frequency. Implements
395 * .recalc_rate, .set_rate and .round_rate
396 *
397 * Flags:
398 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
399 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
400 * the raw value read from the register, with the value of zero considered
401 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
402 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
403 * the hardware register
404 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
405 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
406 * Some hardware implementations gracefully handle this case and allow a
407 * zero divisor by not modifying their input clock
408 * (divide by one / bypass).
409 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
410 * of this register, and mask of divider bits are in higher 16-bit of this
411 * register. While setting the divider bits, higher 16-bit should also be
412 * updated to indicate changing divider bits.
413 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
414 * to the closest integer instead of the up one.
415 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
416 * not be changed by the clock framework.
417 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
418 * except when the value read from the register is zero, the divisor is
419 * 2^width of the field.
420 */
421struct clk_divider {
422 struct clk_hw hw;
423 void __iomem *reg;
424 u8 shift;
425 u8 width;
426 u8 flags;
427 const struct clk_div_table *table;
428 spinlock_t *lock;
429};
430
431#define clk_div_mask(width) ((1 << (width)) - 1)
432#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
433
434#define CLK_DIVIDER_ONE_BASED BIT(0)
435#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
436#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
437#define CLK_DIVIDER_HIWORD_MASK BIT(3)
438#define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
439#define CLK_DIVIDER_READ_ONLY BIT(5)
440#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
441
442extern const struct clk_ops clk_divider_ops;
443extern const struct clk_ops clk_divider_ro_ops;
444
445unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
446 unsigned int val, const struct clk_div_table *table,
447 unsigned long flags, unsigned long width);
448long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
449 unsigned long rate, unsigned long *prate,
450 const struct clk_div_table *table,
451 u8 width, unsigned long flags);
452long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
453 unsigned long rate, unsigned long *prate,
454 const struct clk_div_table *table, u8 width,
455 unsigned long flags, unsigned int val);
456int divider_get_val(unsigned long rate, unsigned long parent_rate,
457 const struct clk_div_table *table, u8 width,
458 unsigned long flags);
459
460struct clk *clk_register_divider(struct device *dev, const char *name,
461 const char *parent_name, unsigned long flags,
462 void __iomem *reg, u8 shift, u8 width,
463 u8 clk_divider_flags, spinlock_t *lock);
464struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name,
465 const char *parent_name, unsigned long flags,
466 void __iomem *reg, u8 shift, u8 width,
467 u8 clk_divider_flags, spinlock_t *lock);
468struct clk *clk_register_divider_table(struct device *dev, const char *name,
469 const char *parent_name, unsigned long flags,
470 void __iomem *reg, u8 shift, u8 width,
471 u8 clk_divider_flags, const struct clk_div_table *table,
472 spinlock_t *lock);
473struct clk_hw *clk_hw_register_divider_table(struct device *dev,
474 const char *name, const char *parent_name, unsigned long flags,
475 void __iomem *reg, u8 shift, u8 width,
476 u8 clk_divider_flags, const struct clk_div_table *table,
477 spinlock_t *lock);
478void clk_unregister_divider(struct clk *clk);
479void clk_hw_unregister_divider(struct clk_hw *hw);
480
481/**
482 * struct clk_mux - multiplexer clock
483 *
484 * @hw: handle between common and hardware-specific interfaces
485 * @reg: register controlling multiplexer
486 * @table: array of register values corresponding to the parent index
487 * @shift: shift to multiplexer bit field
488 * @mask: mask of mutliplexer bit field
489 * @flags: hardware-specific flags
490 * @lock: register lock
491 *
492 * Clock with multiple selectable parents. Implements .get_parent, .set_parent
493 * and .recalc_rate
494 *
495 * Flags:
496 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
497 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
498 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
499 * register, and mask of mux bits are in higher 16-bit of this register.
500 * While setting the mux bits, higher 16-bit should also be updated to
501 * indicate changing mux bits.
502 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
503 * frequency.
504 */
505struct clk_mux {
506 struct clk_hw hw;
507 void __iomem *reg;
508 u32 *table;
509 u32 mask;
510 u8 shift;
511 u8 flags;
512 spinlock_t *lock;
513};
514
515#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
516
517#define CLK_MUX_INDEX_ONE BIT(0)
518#define CLK_MUX_INDEX_BIT BIT(1)
519#define CLK_MUX_HIWORD_MASK BIT(2)
520#define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
521#define CLK_MUX_ROUND_CLOSEST BIT(4)
522
523extern const struct clk_ops clk_mux_ops;
524extern const struct clk_ops clk_mux_ro_ops;
525
526struct clk *clk_register_mux(struct device *dev, const char *name,
527 const char * const *parent_names, u8 num_parents,
528 unsigned long flags,
529 void __iomem *reg, u8 shift, u8 width,
530 u8 clk_mux_flags, spinlock_t *lock);
531struct clk_hw *clk_hw_register_mux(struct device *dev, const char *name,
532 const char * const *parent_names, u8 num_parents,
533 unsigned long flags,
534 void __iomem *reg, u8 shift, u8 width,
535 u8 clk_mux_flags, spinlock_t *lock);
536
537struct clk *clk_register_mux_table(struct device *dev, const char *name,
538 const char * const *parent_names, u8 num_parents,
539 unsigned long flags,
540 void __iomem *reg, u8 shift, u32 mask,
541 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
542struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name,
543 const char * const *parent_names, u8 num_parents,
544 unsigned long flags,
545 void __iomem *reg, u8 shift, u32 mask,
546 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
547
548int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
549 unsigned int val);
550unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index);
551
552void clk_unregister_mux(struct clk *clk);
553void clk_hw_unregister_mux(struct clk_hw *hw);
554
555void of_fixed_factor_clk_setup(struct device_node *node);
556
557/**
558 * struct clk_fixed_factor - fixed multiplier and divider clock
559 *
560 * @hw: handle between common and hardware-specific interfaces
561 * @mult: multiplier
562 * @div: divider
563 *
564 * Clock with a fixed multiplier and divider. The output frequency is the
565 * parent clock rate divided by div and multiplied by mult.
566 * Implements .recalc_rate, .set_rate and .round_rate
567 */
568
569struct clk_fixed_factor {
570 struct clk_hw hw;
571 unsigned int mult;
572 unsigned int div;
573};
574
575#define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
576
577extern const struct clk_ops clk_fixed_factor_ops;
578struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
579 const char *parent_name, unsigned long flags,
580 unsigned int mult, unsigned int div);
581void clk_unregister_fixed_factor(struct clk *clk);
582struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
583 const char *name, const char *parent_name, unsigned long flags,
584 unsigned int mult, unsigned int div);
585void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
586
587/**
588 * struct clk_fractional_divider - adjustable fractional divider clock
589 *
590 * @hw: handle between common and hardware-specific interfaces
591 * @reg: register containing the divider
592 * @mshift: shift to the numerator bit field
593 * @mwidth: width of the numerator bit field
594 * @nshift: shift to the denominator bit field
595 * @nwidth: width of the denominator bit field
596 * @lock: register lock
597 *
598 * Clock with adjustable fractional divider affecting its output frequency.
599 *
600 * Flags:
601 * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
602 * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED
603 * is set then the numerator and denominator are both the value read
604 * plus one.
605 */
606struct clk_fractional_divider {
607 struct clk_hw hw;
608 void __iomem *reg;
609 u8 mshift;
610 u8 mwidth;
611 u32 mmask;
612 u8 nshift;
613 u8 nwidth;
614 u32 nmask;
615 u8 flags;
616 void (*approximation)(struct clk_hw *hw,
617 unsigned long rate, unsigned long *parent_rate,
618 unsigned long *m, unsigned long *n);
619 spinlock_t *lock;
620};
621
622#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
623
624#define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)
625
626extern const struct clk_ops clk_fractional_divider_ops;
627struct clk *clk_register_fractional_divider(struct device *dev,
628 const char *name, const char *parent_name, unsigned long flags,
629 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
630 u8 clk_divider_flags, spinlock_t *lock);
631struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
632 const char *name, const char *parent_name, unsigned long flags,
633 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
634 u8 clk_divider_flags, spinlock_t *lock);
635void clk_hw_unregister_fractional_divider(struct clk_hw *hw);
636
637/**
638 * struct clk_multiplier - adjustable multiplier clock
639 *
640 * @hw: handle between common and hardware-specific interfaces
641 * @reg: register containing the multiplier
642 * @shift: shift to the multiplier bit field
643 * @width: width of the multiplier bit field
644 * @lock: register lock
645 *
646 * Clock with an adjustable multiplier affecting its output frequency.
647 * Implements .recalc_rate, .set_rate and .round_rate
648 *
649 * Flags:
650 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
651 * from the register, with 0 being a valid value effectively
652 * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
653 * set, then a null multiplier will be considered as a bypass,
654 * leaving the parent rate unmodified.
655 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
656 * rounded to the closest integer instead of the down one.
657 */
658struct clk_multiplier {
659 struct clk_hw hw;
660 void __iomem *reg;
661 u8 shift;
662 u8 width;
663 u8 flags;
664 spinlock_t *lock;
665};
666
667#define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
668
669#define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
670#define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
671
672extern const struct clk_ops clk_multiplier_ops;
673
674/***
675 * struct clk_composite - aggregate clock of mux, divider and gate clocks
676 *
677 * @hw: handle between common and hardware-specific interfaces
678 * @mux_hw: handle between composite and hardware-specific mux clock
679 * @rate_hw: handle between composite and hardware-specific rate clock
680 * @gate_hw: handle between composite and hardware-specific gate clock
681 * @mux_ops: clock ops for mux
682 * @rate_ops: clock ops for rate
683 * @gate_ops: clock ops for gate
684 */
685struct clk_composite {
686 struct clk_hw hw;
687 struct clk_ops ops;
688
689 struct clk_hw *mux_hw;
690 struct clk_hw *rate_hw;
691 struct clk_hw *gate_hw;
692
693 const struct clk_ops *mux_ops;
694 const struct clk_ops *rate_ops;
695 const struct clk_ops *gate_ops;
696};
697
698#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
699
700struct clk *clk_register_composite(struct device *dev, const char *name,
701 const char * const *parent_names, int num_parents,
702 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
703 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
704 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
705 unsigned long flags);
706void clk_unregister_composite(struct clk *clk);
707struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
708 const char * const *parent_names, int num_parents,
709 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
710 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
711 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
712 unsigned long flags);
713void clk_hw_unregister_composite(struct clk_hw *hw);
714
715/***
716 * struct clk_gpio_gate - gpio gated clock
717 *
718 * @hw: handle between common and hardware-specific interfaces
719 * @gpiod: gpio descriptor
720 *
721 * Clock with a gpio control for enabling and disabling the parent clock.
722 * Implements .enable, .disable and .is_enabled
723 */
724
725struct clk_gpio {
726 struct clk_hw hw;
727 struct gpio_desc *gpiod;
728};
729
730#define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw)
731
732extern const struct clk_ops clk_gpio_gate_ops;
733struct clk *clk_register_gpio_gate(struct device *dev, const char *name,
734 const char *parent_name, struct gpio_desc *gpiod,
735 unsigned long flags);
736struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name,
737 const char *parent_name, struct gpio_desc *gpiod,
738 unsigned long flags);
739void clk_hw_unregister_gpio_gate(struct clk_hw *hw);
740
741/**
742 * struct clk_gpio_mux - gpio controlled clock multiplexer
743 *
744 * @hw: see struct clk_gpio
745 * @gpiod: gpio descriptor to select the parent of this clock multiplexer
746 *
747 * Clock with a gpio control for selecting the parent clock.
748 * Implements .get_parent, .set_parent and .determine_rate
749 */
750
751extern const struct clk_ops clk_gpio_mux_ops;
752struct clk *clk_register_gpio_mux(struct device *dev, const char *name,
753 const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod,
754 unsigned long flags);
755struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name,
756 const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod,
757 unsigned long flags);
758void clk_hw_unregister_gpio_mux(struct clk_hw *hw);
759
760/**
761 * clk_register - allocate a new clock, register it and return an opaque cookie
762 * @dev: device that is registering this clock
763 * @hw: link to hardware-specific clock data
764 *
765 * clk_register is the primary interface for populating the clock tree with new
766 * clock nodes. It returns a pointer to the newly allocated struct clk which
767 * cannot be dereferenced by driver code but may be used in conjuction with the
768 * rest of the clock API. In the event of an error clk_register will return an
769 * error code; drivers must test for an error code after calling clk_register.
770 */
771struct clk *clk_register(struct device *dev, struct clk_hw *hw);
772struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
773
774int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw);
775int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw);
776
777void clk_unregister(struct clk *clk);
778void devm_clk_unregister(struct device *dev, struct clk *clk);
779
780void clk_hw_unregister(struct clk_hw *hw);
781void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw);
782
783/* helper functions */
784const char *__clk_get_name(const struct clk *clk);
785const char *clk_hw_get_name(const struct clk_hw *hw);
786struct clk_hw *__clk_get_hw(struct clk *clk);
787unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
788struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
789struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
790 unsigned int index);
791unsigned int __clk_get_enable_count(struct clk *clk);
792unsigned long clk_hw_get_rate(const struct clk_hw *hw);
793unsigned long __clk_get_flags(struct clk *clk);
794unsigned long clk_hw_get_flags(const struct clk_hw *hw);
795#define clk_hw_can_set_rate_parent(hw) \
796 (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT)
797
798bool clk_hw_is_prepared(const struct clk_hw *hw);
799bool clk_hw_rate_is_protected(const struct clk_hw *hw);
800bool clk_hw_is_enabled(const struct clk_hw *hw);
801bool __clk_is_enabled(struct clk *clk);
802struct clk *__clk_lookup(const char *name);
803int __clk_mux_determine_rate(struct clk_hw *hw,
804 struct clk_rate_request *req);
805int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
806int __clk_mux_determine_rate_closest(struct clk_hw *hw,
807 struct clk_rate_request *req);
808int clk_mux_determine_rate_flags(struct clk_hw *hw,
809 struct clk_rate_request *req,
810 unsigned long flags);
811void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
812void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
813 unsigned long max_rate);
814
815static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
816{
817 dst->clk = src->clk;
818 dst->core = src->core;
819}
820
821static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate,
822 unsigned long *prate,
823 const struct clk_div_table *table,
824 u8 width, unsigned long flags)
825{
826 return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
827 rate, prate, table, width, flags);
828}
829
830static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate,
831 unsigned long *prate,
832 const struct clk_div_table *table,
833 u8 width, unsigned long flags,
834 unsigned int val)
835{
836 return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw),
837 rate, prate, table, width, flags,
838 val);
839}
840
841/*
842 * FIXME clock api without lock protection
843 */
844unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
845
846struct of_device_id;
847
848struct clk_onecell_data {
849 struct clk **clks;
850 unsigned int clk_num;
851};
852
853struct clk_hw_onecell_data {
854 unsigned int num;
855 struct clk_hw *hws[];
856};
857
858extern struct of_device_id __clk_of_table;
859
860#define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)
861
862/*
863 * Use this macro when you have a driver that requires two initialization
864 * routines, one at of_clk_init(), and one at platform device probe
865 */
866#define CLK_OF_DECLARE_DRIVER(name, compat, fn) \
867 static void __init name##_of_clk_init_driver(struct device_node *np) \
868 { \
869 of_node_clear_flag(np, OF_POPULATED); \
870 fn(np); \
871 } \
872 OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver)
873
874#define CLK_HW_INIT(_name, _parent, _ops, _flags) \
875 (&(struct clk_init_data) { \
876 .flags = _flags, \
877 .name = _name, \
878 .parent_names = (const char *[]) { _parent }, \
879 .num_parents = 1, \
880 .ops = _ops, \
881 })
882
883#define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \
884 (&(struct clk_init_data) { \
885 .flags = _flags, \
886 .name = _name, \
887 .parent_names = _parents, \
888 .num_parents = ARRAY_SIZE(_parents), \
889 .ops = _ops, \
890 })
891
892#define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \
893 (&(struct clk_init_data) { \
894 .flags = _flags, \
895 .name = _name, \
896 .parent_names = NULL, \
897 .num_parents = 0, \
898 .ops = _ops, \
899 })
900
901#define CLK_FIXED_FACTOR(_struct, _name, _parent, \
902 _div, _mult, _flags) \
903 struct clk_fixed_factor _struct = { \
904 .div = _div, \
905 .mult = _mult, \
906 .hw.init = CLK_HW_INIT(_name, \
907 _parent, \
908 &clk_fixed_factor_ops, \
909 _flags), \
910 }
911
912#ifdef CONFIG_OF
913int of_clk_add_provider(struct device_node *np,
914 struct clk *(*clk_src_get)(struct of_phandle_args *args,
915 void *data),
916 void *data);
917int of_clk_add_hw_provider(struct device_node *np,
918 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
919 void *data),
920 void *data);
921int devm_of_clk_add_hw_provider(struct device *dev,
922 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
923 void *data),
924 void *data);
925void of_clk_del_provider(struct device_node *np);
926void devm_of_clk_del_provider(struct device *dev);
927struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
928 void *data);
929struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec,
930 void *data);
931struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
932struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec,
933 void *data);
934int of_clk_parent_fill(struct device_node *np, const char **parents,
935 unsigned int size);
936int of_clk_detect_critical(struct device_node *np, int index,
937 unsigned long *flags);
938
939#else /* !CONFIG_OF */
940
941static inline int of_clk_add_provider(struct device_node *np,
942 struct clk *(*clk_src_get)(struct of_phandle_args *args,
943 void *data),
944 void *data)
945{
946 return 0;
947}
948static inline int of_clk_add_hw_provider(struct device_node *np,
949 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
950 void *data),
951 void *data)
952{
953 return 0;
954}
955static inline int devm_of_clk_add_hw_provider(struct device *dev,
956 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
957 void *data),
958 void *data)
959{
960 return 0;
961}
962static inline void of_clk_del_provider(struct device_node *np) {}
963static inline void devm_of_clk_del_provider(struct device *dev) {}
964static inline struct clk *of_clk_src_simple_get(
965 struct of_phandle_args *clkspec, void *data)
966{
967 return ERR_PTR(-ENOENT);
968}
969static inline struct clk_hw *
970of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)
971{
972 return ERR_PTR(-ENOENT);
973}
974static inline struct clk *of_clk_src_onecell_get(
975 struct of_phandle_args *clkspec, void *data)
976{
977 return ERR_PTR(-ENOENT);
978}
979static inline struct clk_hw *
980of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
981{
982 return ERR_PTR(-ENOENT);
983}
984static inline int of_clk_parent_fill(struct device_node *np,
985 const char **parents, unsigned int size)
986{
987 return 0;
988}
989static inline int of_clk_detect_critical(struct device_node *np, int index,
990 unsigned long *flags)
991{
992 return 0;
993}
994#endif /* CONFIG_OF */
995
996/*
997 * wrap access to peripherals in accessor routines
998 * for improved portability across platforms
999 */
1000
1001#if IS_ENABLED(CONFIG_PPC)
1002
1003static inline u32 clk_readl(u32 __iomem *reg)
1004{
1005 return ioread32be(reg);
1006}
1007
1008static inline void clk_writel(u32 val, u32 __iomem *reg)
1009{
1010 iowrite32be(val, reg);
1011}
1012
1013#else /* platform dependent I/O accessors */
1014
1015static inline u32 clk_readl(u32 __iomem *reg)
1016{
1017 return readl(reg);
1018}
1019
1020static inline void clk_writel(u32 val, u32 __iomem *reg)
1021{
1022 writel(val, reg);
1023}
1024
1025#endif /* platform dependent I/O accessors */
1026
1027void clk_gate_restore_context(struct clk_hw *hw);
1028
1029#endif /* CONFIG_COMMON_CLK */
1030#endif /* CLK_PROVIDER_H */
1031