1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> |
4 | * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> |
5 | */ |
6 | #ifndef __LINUX_CLK_PROVIDER_H |
7 | #define __LINUX_CLK_PROVIDER_H |
8 | |
9 | #include <linux/of.h> |
10 | #include <linux/of_clk.h> |
11 | |
12 | /* |
13 | * flags used across common struct clk. these flags should only affect the |
14 | * top-level framework. custom flags for dealing with hardware specifics |
15 | * belong in struct clk_foo |
16 | * |
17 | * Please update clk_flags[] in drivers/clk/clk.c when making changes here! |
18 | */ |
19 | #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ |
20 | #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ |
21 | #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ |
22 | #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ |
23 | /* unused */ |
24 | /* unused */ |
25 | #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ |
26 | #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ |
27 | #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ |
28 | #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */ |
29 | #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */ |
30 | #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */ |
31 | /* parents need enable during gate/ungate, set rate and re-parent */ |
32 | #define CLK_OPS_PARENT_ENABLE BIT(12) |
33 | /* duty cycle call may be forwarded to the parent clock */ |
34 | #define CLK_DUTY_CYCLE_PARENT BIT(13) |
35 | |
36 | struct clk; |
37 | struct clk_hw; |
38 | struct clk_core; |
39 | struct dentry; |
40 | |
41 | /** |
42 | * struct clk_rate_request - Structure encoding the clk constraints that |
43 | * a clock user might require. |
44 | * |
45 | * Should be initialized by calling clk_hw_init_rate_request(). |
46 | * |
47 | * @core: Pointer to the struct clk_core affected by this request |
48 | * @rate: Requested clock rate. This field will be adjusted by |
49 | * clock drivers according to hardware capabilities. |
50 | * @min_rate: Minimum rate imposed by clk users. |
51 | * @max_rate: Maximum rate imposed by clk users. |
52 | * @best_parent_rate: The best parent rate a parent can provide to fulfill the |
53 | * requested constraints. |
54 | * @best_parent_hw: The most appropriate parent clock that fulfills the |
55 | * requested constraints. |
56 | * |
57 | */ |
58 | struct clk_rate_request { |
59 | struct clk_core *core; |
60 | unsigned long rate; |
61 | unsigned long min_rate; |
62 | unsigned long max_rate; |
63 | unsigned long best_parent_rate; |
64 | struct clk_hw *best_parent_hw; |
65 | }; |
66 | |
67 | void clk_hw_init_rate_request(const struct clk_hw *hw, |
68 | struct clk_rate_request *req, |
69 | unsigned long rate); |
70 | void clk_hw_forward_rate_request(const struct clk_hw *core, |
71 | const struct clk_rate_request *old_req, |
72 | const struct clk_hw *parent, |
73 | struct clk_rate_request *req, |
74 | unsigned long parent_rate); |
75 | |
76 | /** |
77 | * struct clk_duty - Structure encoding the duty cycle ratio of a clock |
78 | * |
79 | * @num: Numerator of the duty cycle ratio |
80 | * @den: Denominator of the duty cycle ratio |
81 | */ |
82 | struct clk_duty { |
83 | unsigned int num; |
84 | unsigned int den; |
85 | }; |
86 | |
87 | /** |
88 | * struct clk_ops - Callback operations for hardware clocks; these are to |
89 | * be provided by the clock implementation, and will be called by drivers |
90 | * through the clk_* api. |
91 | * |
92 | * @prepare: Prepare the clock for enabling. This must not return until |
93 | * the clock is fully prepared, and it's safe to call clk_enable. |
94 | * This callback is intended to allow clock implementations to |
95 | * do any initialisation that may sleep. Called with |
96 | * prepare_lock held. |
97 | * |
98 | * @unprepare: Release the clock from its prepared state. This will typically |
99 | * undo any work done in the @prepare callback. Called with |
100 | * prepare_lock held. |
101 | * |
102 | * @is_prepared: Queries the hardware to determine if the clock is prepared. |
103 | * This function is allowed to sleep. Optional, if this op is not |
104 | * set then the prepare count will be used. |
105 | * |
106 | * @unprepare_unused: Unprepare the clock atomically. Only called from |
107 | * clk_disable_unused for prepare clocks with special needs. |
108 | * Called with prepare mutex held. This function may sleep. |
109 | * |
110 | * @enable: Enable the clock atomically. This must not return until the |
111 | * clock is generating a valid clock signal, usable by consumer |
112 | * devices. Called with enable_lock held. This function must not |
113 | * sleep. |
114 | * |
115 | * @disable: Disable the clock atomically. Called with enable_lock held. |
116 | * This function must not sleep. |
117 | * |
118 | * @is_enabled: Queries the hardware to determine if the clock is enabled. |
119 | * This function must not sleep. Optional, if this op is not |
120 | * set then the enable count will be used. |
121 | * |
122 | * @disable_unused: Disable the clock atomically. Only called from |
123 | * clk_disable_unused for gate clocks with special needs. |
124 | * Called with enable_lock held. This function must not |
125 | * sleep. |
126 | * |
127 | * @save_context: Save the context of the clock in prepration for poweroff. |
128 | * |
129 | * @restore_context: Restore the context of the clock after a restoration |
130 | * of power. |
131 | * |
132 | * @recalc_rate: Recalculate the rate of this clock, by querying hardware. The |
133 | * parent rate is an input parameter. It is up to the caller to |
134 | * ensure that the prepare_mutex is held across this call. If the |
135 | * driver cannot figure out a rate for this clock, it must return |
136 | * 0. Returns the calculated rate. Optional, but recommended - if |
137 | * this op is not set then clock rate will be initialized to 0. |
138 | * |
139 | * @round_rate: Given a target rate as input, returns the closest rate actually |
140 | * supported by the clock. The parent rate is an input/output |
141 | * parameter. |
142 | * |
143 | * @determine_rate: Given a target rate as input, returns the closest rate |
144 | * actually supported by the clock, and optionally the parent clock |
145 | * that should be used to provide the clock rate. |
146 | * |
147 | * @set_parent: Change the input source of this clock; for clocks with multiple |
148 | * possible parents specify a new parent by passing in the index |
149 | * as a u8 corresponding to the parent in either the .parent_names |
150 | * or .parents arrays. This function in affect translates an |
151 | * array index into the value programmed into the hardware. |
152 | * Returns 0 on success, -EERROR otherwise. |
153 | * |
154 | * @get_parent: Queries the hardware to determine the parent of a clock. The |
155 | * return value is a u8 which specifies the index corresponding to |
156 | * the parent clock. This index can be applied to either the |
157 | * .parent_names or .parents arrays. In short, this function |
158 | * translates the parent value read from hardware into an array |
159 | * index. Currently only called when the clock is initialized by |
160 | * __clk_init. This callback is mandatory for clocks with |
161 | * multiple parents. It is optional (and unnecessary) for clocks |
162 | * with 0 or 1 parents. |
163 | * |
164 | * @set_rate: Change the rate of this clock. The requested rate is specified |
165 | * by the second argument, which should typically be the return |
166 | * of .round_rate call. The third argument gives the parent rate |
167 | * which is likely helpful for most .set_rate implementation. |
168 | * Returns 0 on success, -EERROR otherwise. |
169 | * |
170 | * @set_rate_and_parent: Change the rate and the parent of this clock. The |
171 | * requested rate is specified by the second argument, which |
172 | * should typically be the return of .round_rate call. The |
173 | * third argument gives the parent rate which is likely helpful |
174 | * for most .set_rate_and_parent implementation. The fourth |
175 | * argument gives the parent index. This callback is optional (and |
176 | * unnecessary) for clocks with 0 or 1 parents as well as |
177 | * for clocks that can tolerate switching the rate and the parent |
178 | * separately via calls to .set_parent and .set_rate. |
179 | * Returns 0 on success, -EERROR otherwise. |
180 | * |
181 | * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy |
182 | * is expressed in ppb (parts per billion). The parent accuracy is |
183 | * an input parameter. |
184 | * Returns the calculated accuracy. Optional - if this op is not |
185 | * set then clock accuracy will be initialized to parent accuracy |
186 | * or 0 (perfect clock) if clock has no parent. |
187 | * |
188 | * @get_phase: Queries the hardware to get the current phase of a clock. |
189 | * Returned values are 0-359 degrees on success, negative |
190 | * error codes on failure. |
191 | * |
192 | * @set_phase: Shift the phase this clock signal in degrees specified |
193 | * by the second argument. Valid values for degrees are |
194 | * 0-359. Return 0 on success, otherwise -EERROR. |
195 | * |
196 | * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio |
197 | * of a clock. Returned values denominator cannot be 0 and must be |
198 | * superior or equal to the numerator. |
199 | * |
200 | * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by |
201 | * the numerator (2nd argurment) and denominator (3rd argument). |
202 | * Argument must be a valid ratio (denominator > 0 |
203 | * and >= numerator) Return 0 on success, otherwise -EERROR. |
204 | * |
205 | * @init: Perform platform-specific initialization magic. |
206 | * This is not used by any of the basic clock types. |
207 | * This callback exist for HW which needs to perform some |
208 | * initialisation magic for CCF to get an accurate view of the |
209 | * clock. It may also be used dynamic resource allocation is |
210 | * required. It shall not used to deal with clock parameters, |
211 | * such as rate or parents. |
212 | * Returns 0 on success, -EERROR otherwise. |
213 | * |
214 | * @terminate: Free any resource allocated by init. |
215 | * |
216 | * @debug_init: Set up type-specific debugfs entries for this clock. This |
217 | * is called once, after the debugfs directory entry for this |
218 | * clock has been created. The dentry pointer representing that |
219 | * directory is provided as an argument. Called with |
220 | * prepare_lock held. Returns 0 on success, -EERROR otherwise. |
221 | * |
222 | * |
223 | * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow |
224 | * implementations to split any work between atomic (enable) and sleepable |
225 | * (prepare) contexts. If enabling a clock requires code that might sleep, |
226 | * this must be done in clk_prepare. Clock enable code that will never be |
227 | * called in a sleepable context may be implemented in clk_enable. |
228 | * |
229 | * Typically, drivers will call clk_prepare when a clock may be needed later |
230 | * (eg. when a device is opened), and clk_enable when the clock is actually |
231 | * required (eg. from an interrupt). Note that clk_prepare MUST have been |
232 | * called before clk_enable. |
233 | */ |
234 | struct clk_ops { |
235 | int (*prepare)(struct clk_hw *hw); |
236 | void (*unprepare)(struct clk_hw *hw); |
237 | int (*is_prepared)(struct clk_hw *hw); |
238 | void (*unprepare_unused)(struct clk_hw *hw); |
239 | int (*enable)(struct clk_hw *hw); |
240 | void (*disable)(struct clk_hw *hw); |
241 | int (*is_enabled)(struct clk_hw *hw); |
242 | void (*disable_unused)(struct clk_hw *hw); |
243 | int (*save_context)(struct clk_hw *hw); |
244 | void (*restore_context)(struct clk_hw *hw); |
245 | unsigned long (*recalc_rate)(struct clk_hw *hw, |
246 | unsigned long parent_rate); |
247 | long (*round_rate)(struct clk_hw *hw, unsigned long rate, |
248 | unsigned long *parent_rate); |
249 | int (*determine_rate)(struct clk_hw *hw, |
250 | struct clk_rate_request *req); |
251 | int (*set_parent)(struct clk_hw *hw, u8 index); |
252 | u8 (*get_parent)(struct clk_hw *hw); |
253 | int (*set_rate)(struct clk_hw *hw, unsigned long rate, |
254 | unsigned long parent_rate); |
255 | int (*set_rate_and_parent)(struct clk_hw *hw, |
256 | unsigned long rate, |
257 | unsigned long parent_rate, u8 index); |
258 | unsigned long (*recalc_accuracy)(struct clk_hw *hw, |
259 | unsigned long parent_accuracy); |
260 | int (*get_phase)(struct clk_hw *hw); |
261 | int (*set_phase)(struct clk_hw *hw, int degrees); |
262 | int (*get_duty_cycle)(struct clk_hw *hw, |
263 | struct clk_duty *duty); |
264 | int (*set_duty_cycle)(struct clk_hw *hw, |
265 | struct clk_duty *duty); |
266 | int (*init)(struct clk_hw *hw); |
267 | void (*terminate)(struct clk_hw *hw); |
268 | void (*debug_init)(struct clk_hw *hw, struct dentry *dentry); |
269 | }; |
270 | |
271 | /** |
272 | * struct clk_parent_data - clk parent information |
273 | * @hw: parent clk_hw pointer (used for clk providers with internal clks) |
274 | * @fw_name: parent name local to provider registering clk |
275 | * @name: globally unique parent name (used as a fallback) |
276 | * @index: parent index local to provider registering clk (if @fw_name absent) |
277 | */ |
278 | struct clk_parent_data { |
279 | const struct clk_hw *hw; |
280 | const char *fw_name; |
281 | const char *name; |
282 | int index; |
283 | }; |
284 | |
285 | /** |
286 | * struct clk_init_data - holds init data that's common to all clocks and is |
287 | * shared between the clock provider and the common clock framework. |
288 | * |
289 | * @name: clock name |
290 | * @ops: operations this clock supports |
291 | * @parent_names: array of string names for all possible parents |
292 | * @parent_data: array of parent data for all possible parents (when some |
293 | * parents are external to the clk controller) |
294 | * @parent_hws: array of pointers to all possible parents (when all parents |
295 | * are internal to the clk controller) |
296 | * @num_parents: number of possible parents |
297 | * @flags: framework-level hints and quirks |
298 | */ |
299 | struct clk_init_data { |
300 | const char *name; |
301 | const struct clk_ops *ops; |
302 | /* Only one of the following three should be assigned */ |
303 | const char * const *parent_names; |
304 | const struct clk_parent_data *parent_data; |
305 | const struct clk_hw **parent_hws; |
306 | u8 num_parents; |
307 | unsigned long flags; |
308 | }; |
309 | |
310 | /** |
311 | * struct clk_hw - handle for traversing from a struct clk to its corresponding |
312 | * hardware-specific structure. struct clk_hw should be declared within struct |
313 | * clk_foo and then referenced by the struct clk instance that uses struct |
314 | * clk_foo's clk_ops |
315 | * |
316 | * @core: pointer to the struct clk_core instance that points back to this |
317 | * struct clk_hw instance |
318 | * |
319 | * @clk: pointer to the per-user struct clk instance that can be used to call |
320 | * into the clk API |
321 | * |
322 | * @init: pointer to struct clk_init_data that contains the init data shared |
323 | * with the common clock framework. This pointer will be set to NULL once |
324 | * a clk_register() variant is called on this clk_hw pointer. |
325 | */ |
326 | struct clk_hw { |
327 | struct clk_core *core; |
328 | struct clk *clk; |
329 | const struct clk_init_data *init; |
330 | }; |
331 | |
332 | /* |
333 | * DOC: Basic clock implementations common to many platforms |
334 | * |
335 | * Each basic clock hardware type is comprised of a structure describing the |
336 | * clock hardware, implementations of the relevant callbacks in struct clk_ops, |
337 | * unique flags for that hardware type, a registration function and an |
338 | * alternative macro for static initialization |
339 | */ |
340 | |
341 | /** |
342 | * struct clk_fixed_rate - fixed-rate clock |
343 | * @hw: handle between common and hardware-specific interfaces |
344 | * @fixed_rate: constant frequency of clock |
345 | * @fixed_accuracy: constant accuracy of clock in ppb (parts per billion) |
346 | * @flags: hardware specific flags |
347 | * |
348 | * Flags: |
349 | * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk |
350 | * instead of what's set in @fixed_accuracy. |
351 | */ |
352 | struct clk_fixed_rate { |
353 | struct clk_hw hw; |
354 | unsigned long fixed_rate; |
355 | unsigned long fixed_accuracy; |
356 | unsigned long flags; |
357 | }; |
358 | |
359 | #define CLK_FIXED_RATE_PARENT_ACCURACY BIT(0) |
360 | |
361 | extern const struct clk_ops clk_fixed_rate_ops; |
362 | struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev, |
363 | struct device_node *np, const char *name, |
364 | const char *parent_name, const struct clk_hw *parent_hw, |
365 | const struct clk_parent_data *parent_data, unsigned long flags, |
366 | unsigned long fixed_rate, unsigned long fixed_accuracy, |
367 | unsigned long clk_fixed_flags, bool devm); |
368 | struct clk *clk_register_fixed_rate(struct device *dev, const char *name, |
369 | const char *parent_name, unsigned long flags, |
370 | unsigned long fixed_rate); |
371 | /** |
372 | * clk_hw_register_fixed_rate - register fixed-rate clock with the clock |
373 | * framework |
374 | * @dev: device that is registering this clock |
375 | * @name: name of this clock |
376 | * @parent_name: name of clock's parent |
377 | * @flags: framework-specific flags |
378 | * @fixed_rate: non-adjustable clock rate |
379 | */ |
380 | #define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \ |
381 | __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \ |
382 | NULL, (flags), (fixed_rate), 0, 0, false) |
383 | |
384 | /** |
385 | * devm_clk_hw_register_fixed_rate - register fixed-rate clock with the clock |
386 | * framework |
387 | * @dev: device that is registering this clock |
388 | * @name: name of this clock |
389 | * @parent_name: name of clock's parent |
390 | * @flags: framework-specific flags |
391 | * @fixed_rate: non-adjustable clock rate |
392 | */ |
393 | #define devm_clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \ |
394 | __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \ |
395 | NULL, (flags), (fixed_rate), 0, 0, true) |
396 | /** |
397 | * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with |
398 | * the clock framework |
399 | * @dev: device that is registering this clock |
400 | * @name: name of this clock |
401 | * @parent_hw: pointer to parent clk |
402 | * @flags: framework-specific flags |
403 | * @fixed_rate: non-adjustable clock rate |
404 | */ |
405 | #define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags, \ |
406 | fixed_rate) \ |
407 | __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \ |
408 | NULL, (flags), (fixed_rate), 0, 0, false) |
409 | /** |
410 | * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with |
411 | * the clock framework |
412 | * @dev: device that is registering this clock |
413 | * @name: name of this clock |
414 | * @parent_data: parent clk data |
415 | * @flags: framework-specific flags |
416 | * @fixed_rate: non-adjustable clock rate |
417 | */ |
418 | #define clk_hw_register_fixed_rate_parent_data(dev, name, parent_data, flags, \ |
419 | fixed_rate) \ |
420 | __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \ |
421 | (parent_data), (flags), (fixed_rate), 0, \ |
422 | 0, false) |
423 | /** |
424 | * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with |
425 | * the clock framework |
426 | * @dev: device that is registering this clock |
427 | * @name: name of this clock |
428 | * @parent_name: name of clock's parent |
429 | * @flags: framework-specific flags |
430 | * @fixed_rate: non-adjustable clock rate |
431 | * @fixed_accuracy: non-adjustable clock accuracy |
432 | */ |
433 | #define clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name, \ |
434 | flags, fixed_rate, \ |
435 | fixed_accuracy) \ |
436 | __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), \ |
437 | NULL, NULL, (flags), (fixed_rate), \ |
438 | (fixed_accuracy), 0, false) |
439 | /** |
440 | * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate |
441 | * clock with the clock framework |
442 | * @dev: device that is registering this clock |
443 | * @name: name of this clock |
444 | * @parent_hw: pointer to parent clk |
445 | * @flags: framework-specific flags |
446 | * @fixed_rate: non-adjustable clock rate |
447 | * @fixed_accuracy: non-adjustable clock accuracy |
448 | */ |
449 | #define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name, \ |
450 | parent_hw, flags, fixed_rate, fixed_accuracy) \ |
451 | __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw) \ |
452 | NULL, NULL, (flags), (fixed_rate), \ |
453 | (fixed_accuracy), 0, false) |
454 | /** |
455 | * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate |
456 | * clock with the clock framework |
457 | * @dev: device that is registering this clock |
458 | * @name: name of this clock |
459 | * @parent_data: name of clock's parent |
460 | * @flags: framework-specific flags |
461 | * @fixed_rate: non-adjustable clock rate |
462 | * @fixed_accuracy: non-adjustable clock accuracy |
463 | */ |
464 | #define clk_hw_register_fixed_rate_with_accuracy_parent_data(dev, name, \ |
465 | parent_data, flags, fixed_rate, fixed_accuracy) \ |
466 | __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \ |
467 | (parent_data), NULL, (flags), \ |
468 | (fixed_rate), (fixed_accuracy), 0, false) |
469 | /** |
470 | * clk_hw_register_fixed_rate_parent_accuracy - register fixed-rate clock with |
471 | * the clock framework |
472 | * @dev: device that is registering this clock |
473 | * @name: name of this clock |
474 | * @parent_data: name of clock's parent |
475 | * @flags: framework-specific flags |
476 | * @fixed_rate: non-adjustable clock rate |
477 | */ |
478 | #define clk_hw_register_fixed_rate_parent_accuracy(dev, name, parent_data, \ |
479 | flags, fixed_rate) \ |
480 | __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \ |
481 | (parent_data), (flags), (fixed_rate), 0, \ |
482 | CLK_FIXED_RATE_PARENT_ACCURACY, false) |
483 | |
484 | void clk_unregister_fixed_rate(struct clk *clk); |
485 | void clk_hw_unregister_fixed_rate(struct clk_hw *hw); |
486 | |
487 | void of_fixed_clk_setup(struct device_node *np); |
488 | |
489 | /** |
490 | * struct clk_gate - gating clock |
491 | * |
492 | * @hw: handle between common and hardware-specific interfaces |
493 | * @reg: register controlling gate |
494 | * @bit_idx: single bit controlling gate |
495 | * @flags: hardware-specific flags |
496 | * @lock: register lock |
497 | * |
498 | * Clock which can gate its output. Implements .enable & .disable |
499 | * |
500 | * Flags: |
501 | * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to |
502 | * enable the clock. Setting this flag does the opposite: setting the bit |
503 | * disable the clock and clearing it enables the clock |
504 | * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit |
505 | * of this register, and mask of gate bits are in higher 16-bit of this |
506 | * register. While setting the gate bits, higher 16-bit should also be |
507 | * updated to indicate changing gate bits. |
508 | * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for |
509 | * the gate register. Setting this flag makes the register accesses big |
510 | * endian. |
511 | */ |
512 | struct clk_gate { |
513 | struct clk_hw hw; |
514 | void __iomem *reg; |
515 | u8 bit_idx; |
516 | u8 flags; |
517 | spinlock_t *lock; |
518 | }; |
519 | |
520 | #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) |
521 | |
522 | #define CLK_GATE_SET_TO_DISABLE BIT(0) |
523 | #define CLK_GATE_HIWORD_MASK BIT(1) |
524 | #define CLK_GATE_BIG_ENDIAN BIT(2) |
525 | |
526 | extern const struct clk_ops clk_gate_ops; |
527 | struct clk_hw *__clk_hw_register_gate(struct device *dev, |
528 | struct device_node *np, const char *name, |
529 | const char *parent_name, const struct clk_hw *parent_hw, |
530 | const struct clk_parent_data *parent_data, |
531 | unsigned long flags, |
532 | void __iomem *reg, u8 bit_idx, |
533 | u8 clk_gate_flags, spinlock_t *lock); |
534 | struct clk_hw *__devm_clk_hw_register_gate(struct device *dev, |
535 | struct device_node *np, const char *name, |
536 | const char *parent_name, const struct clk_hw *parent_hw, |
537 | const struct clk_parent_data *parent_data, |
538 | unsigned long flags, |
539 | void __iomem *reg, u8 bit_idx, |
540 | u8 clk_gate_flags, spinlock_t *lock); |
541 | struct clk *clk_register_gate(struct device *dev, const char *name, |
542 | const char *parent_name, unsigned long flags, |
543 | void __iomem *reg, u8 bit_idx, |
544 | u8 clk_gate_flags, spinlock_t *lock); |
545 | /** |
546 | * clk_hw_register_gate - register a gate clock with the clock framework |
547 | * @dev: device that is registering this clock |
548 | * @name: name of this clock |
549 | * @parent_name: name of this clock's parent |
550 | * @flags: framework-specific flags for this clock |
551 | * @reg: register address to control gating of this clock |
552 | * @bit_idx: which bit in the register controls gating of this clock |
553 | * @clk_gate_flags: gate-specific flags for this clock |
554 | * @lock: shared register lock for this clock |
555 | */ |
556 | #define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx, \ |
557 | clk_gate_flags, lock) \ |
558 | __clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \ |
559 | NULL, (flags), (reg), (bit_idx), \ |
560 | (clk_gate_flags), (lock)) |
561 | /** |
562 | * clk_hw_register_gate_parent_hw - register a gate clock with the clock |
563 | * framework |
564 | * @dev: device that is registering this clock |
565 | * @name: name of this clock |
566 | * @parent_hw: pointer to parent clk |
567 | * @flags: framework-specific flags for this clock |
568 | * @reg: register address to control gating of this clock |
569 | * @bit_idx: which bit in the register controls gating of this clock |
570 | * @clk_gate_flags: gate-specific flags for this clock |
571 | * @lock: shared register lock for this clock |
572 | */ |
573 | #define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg, \ |
574 | bit_idx, clk_gate_flags, lock) \ |
575 | __clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \ |
576 | NULL, (flags), (reg), (bit_idx), \ |
577 | (clk_gate_flags), (lock)) |
578 | /** |
579 | * clk_hw_register_gate_parent_data - register a gate clock with the clock |
580 | * framework |
581 | * @dev: device that is registering this clock |
582 | * @name: name of this clock |
583 | * @parent_data: parent clk data |
584 | * @flags: framework-specific flags for this clock |
585 | * @reg: register address to control gating of this clock |
586 | * @bit_idx: which bit in the register controls gating of this clock |
587 | * @clk_gate_flags: gate-specific flags for this clock |
588 | * @lock: shared register lock for this clock |
589 | */ |
590 | #define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg, \ |
591 | bit_idx, clk_gate_flags, lock) \ |
592 | __clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \ |
593 | (flags), (reg), (bit_idx), \ |
594 | (clk_gate_flags), (lock)) |
595 | /** |
596 | * devm_clk_hw_register_gate - register a gate clock with the clock framework |
597 | * @dev: device that is registering this clock |
598 | * @name: name of this clock |
599 | * @parent_name: name of this clock's parent |
600 | * @flags: framework-specific flags for this clock |
601 | * @reg: register address to control gating of this clock |
602 | * @bit_idx: which bit in the register controls gating of this clock |
603 | * @clk_gate_flags: gate-specific flags for this clock |
604 | * @lock: shared register lock for this clock |
605 | */ |
606 | #define devm_clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx,\ |
607 | clk_gate_flags, lock) \ |
608 | __devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \ |
609 | NULL, (flags), (reg), (bit_idx), \ |
610 | (clk_gate_flags), (lock)) |
611 | /** |
612 | * devm_clk_hw_register_gate_parent_data - register a gate clock with the |
613 | * clock framework |
614 | * @dev: device that is registering this clock |
615 | * @name: name of this clock |
616 | * @parent_data: parent clk data |
617 | * @flags: framework-specific flags for this clock |
618 | * @reg: register address to control gating of this clock |
619 | * @bit_idx: which bit in the register controls gating of this clock |
620 | * @clk_gate_flags: gate-specific flags for this clock |
621 | * @lock: shared register lock for this clock |
622 | */ |
623 | #define devm_clk_hw_register_gate_parent_data(dev, name, parent_data, flags, \ |
624 | reg, bit_idx, clk_gate_flags, \ |
625 | lock) \ |
626 | __devm_clk_hw_register_gate((dev), NULL, (name), NULL, NULL, \ |
627 | (parent_data), (flags), (reg), (bit_idx), \ |
628 | (clk_gate_flags), (lock)) |
629 | |
630 | void clk_unregister_gate(struct clk *clk); |
631 | void clk_hw_unregister_gate(struct clk_hw *hw); |
632 | int clk_gate_is_enabled(struct clk_hw *hw); |
633 | |
634 | struct clk_div_table { |
635 | unsigned int val; |
636 | unsigned int div; |
637 | }; |
638 | |
639 | /** |
640 | * struct clk_divider - adjustable divider clock |
641 | * |
642 | * @hw: handle between common and hardware-specific interfaces |
643 | * @reg: register containing the divider |
644 | * @shift: shift to the divider bit field |
645 | * @width: width of the divider bit field |
646 | * @table: array of value/divider pairs, last entry should have div = 0 |
647 | * @lock: register lock |
648 | * |
649 | * Clock with an adjustable divider affecting its output frequency. Implements |
650 | * .recalc_rate, .set_rate and .round_rate |
651 | * |
652 | * @flags: |
653 | * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the |
654 | * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is |
655 | * the raw value read from the register, with the value of zero considered |
656 | * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. |
657 | * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from |
658 | * the hardware register |
659 | * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have |
660 | * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. |
661 | * Some hardware implementations gracefully handle this case and allow a |
662 | * zero divisor by not modifying their input clock |
663 | * (divide by one / bypass). |
664 | * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit |
665 | * of this register, and mask of divider bits are in higher 16-bit of this |
666 | * register. While setting the divider bits, higher 16-bit should also be |
667 | * updated to indicate changing divider bits. |
668 | * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded |
669 | * to the closest integer instead of the up one. |
670 | * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should |
671 | * not be changed by the clock framework. |
672 | * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED |
673 | * except when the value read from the register is zero, the divisor is |
674 | * 2^width of the field. |
675 | * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used |
676 | * for the divider register. Setting this flag makes the register accesses |
677 | * big endian. |
678 | */ |
679 | struct clk_divider { |
680 | struct clk_hw hw; |
681 | void __iomem *reg; |
682 | u8 shift; |
683 | u8 width; |
684 | u8 flags; |
685 | const struct clk_div_table *table; |
686 | spinlock_t *lock; |
687 | }; |
688 | |
689 | #define clk_div_mask(width) ((1 << (width)) - 1) |
690 | #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) |
691 | |
692 | #define CLK_DIVIDER_ONE_BASED BIT(0) |
693 | #define CLK_DIVIDER_POWER_OF_TWO BIT(1) |
694 | #define CLK_DIVIDER_ALLOW_ZERO BIT(2) |
695 | #define CLK_DIVIDER_HIWORD_MASK BIT(3) |
696 | #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) |
697 | #define CLK_DIVIDER_READ_ONLY BIT(5) |
698 | #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) |
699 | #define CLK_DIVIDER_BIG_ENDIAN BIT(7) |
700 | |
701 | extern const struct clk_ops clk_divider_ops; |
702 | extern const struct clk_ops clk_divider_ro_ops; |
703 | |
704 | unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, |
705 | unsigned int val, const struct clk_div_table *table, |
706 | unsigned long flags, unsigned long width); |
707 | long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, |
708 | unsigned long rate, unsigned long *prate, |
709 | const struct clk_div_table *table, |
710 | u8 width, unsigned long flags); |
711 | long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, |
712 | unsigned long rate, unsigned long *prate, |
713 | const struct clk_div_table *table, u8 width, |
714 | unsigned long flags, unsigned int val); |
715 | int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, |
716 | const struct clk_div_table *table, u8 width, |
717 | unsigned long flags); |
718 | int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, |
719 | const struct clk_div_table *table, u8 width, |
720 | unsigned long flags, unsigned int val); |
721 | int divider_get_val(unsigned long rate, unsigned long parent_rate, |
722 | const struct clk_div_table *table, u8 width, |
723 | unsigned long flags); |
724 | |
725 | struct clk_hw *__clk_hw_register_divider(struct device *dev, |
726 | struct device_node *np, const char *name, |
727 | const char *parent_name, const struct clk_hw *parent_hw, |
728 | const struct clk_parent_data *parent_data, unsigned long flags, |
729 | void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, |
730 | const struct clk_div_table *table, spinlock_t *lock); |
731 | struct clk_hw *__devm_clk_hw_register_divider(struct device *dev, |
732 | struct device_node *np, const char *name, |
733 | const char *parent_name, const struct clk_hw *parent_hw, |
734 | const struct clk_parent_data *parent_data, unsigned long flags, |
735 | void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, |
736 | const struct clk_div_table *table, spinlock_t *lock); |
737 | struct clk *clk_register_divider_table(struct device *dev, const char *name, |
738 | const char *parent_name, unsigned long flags, |
739 | void __iomem *reg, u8 shift, u8 width, |
740 | u8 clk_divider_flags, const struct clk_div_table *table, |
741 | spinlock_t *lock); |
742 | /** |
743 | * clk_register_divider - register a divider clock with the clock framework |
744 | * @dev: device registering this clock |
745 | * @name: name of this clock |
746 | * @parent_name: name of clock's parent |
747 | * @flags: framework-specific flags |
748 | * @reg: register address to adjust divider |
749 | * @shift: number of bits to shift the bitfield |
750 | * @width: width of the bitfield |
751 | * @clk_divider_flags: divider-specific flags for this clock |
752 | * @lock: shared register lock for this clock |
753 | */ |
754 | #define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \ |
755 | clk_divider_flags, lock) \ |
756 | clk_register_divider_table((dev), (name), (parent_name), (flags), \ |
757 | (reg), (shift), (width), \ |
758 | (clk_divider_flags), NULL, (lock)) |
759 | /** |
760 | * clk_hw_register_divider - register a divider clock with the clock framework |
761 | * @dev: device registering this clock |
762 | * @name: name of this clock |
763 | * @parent_name: name of clock's parent |
764 | * @flags: framework-specific flags |
765 | * @reg: register address to adjust divider |
766 | * @shift: number of bits to shift the bitfield |
767 | * @width: width of the bitfield |
768 | * @clk_divider_flags: divider-specific flags for this clock |
769 | * @lock: shared register lock for this clock |
770 | */ |
771 | #define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \ |
772 | width, clk_divider_flags, lock) \ |
773 | __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \ |
774 | NULL, (flags), (reg), (shift), (width), \ |
775 | (clk_divider_flags), NULL, (lock)) |
776 | /** |
777 | * clk_hw_register_divider_parent_hw - register a divider clock with the clock |
778 | * framework |
779 | * @dev: device registering this clock |
780 | * @name: name of this clock |
781 | * @parent_hw: pointer to parent clk |
782 | * @flags: framework-specific flags |
783 | * @reg: register address to adjust divider |
784 | * @shift: number of bits to shift the bitfield |
785 | * @width: width of the bitfield |
786 | * @clk_divider_flags: divider-specific flags for this clock |
787 | * @lock: shared register lock for this clock |
788 | */ |
789 | #define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg, \ |
790 | shift, width, clk_divider_flags, \ |
791 | lock) \ |
792 | __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \ |
793 | NULL, (flags), (reg), (shift), (width), \ |
794 | (clk_divider_flags), NULL, (lock)) |
795 | /** |
796 | * clk_hw_register_divider_parent_data - register a divider clock with the clock |
797 | * framework |
798 | * @dev: device registering this clock |
799 | * @name: name of this clock |
800 | * @parent_data: parent clk data |
801 | * @flags: framework-specific flags |
802 | * @reg: register address to adjust divider |
803 | * @shift: number of bits to shift the bitfield |
804 | * @width: width of the bitfield |
805 | * @clk_divider_flags: divider-specific flags for this clock |
806 | * @lock: shared register lock for this clock |
807 | */ |
808 | #define clk_hw_register_divider_parent_data(dev, name, parent_data, flags, \ |
809 | reg, shift, width, \ |
810 | clk_divider_flags, lock) \ |
811 | __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \ |
812 | (parent_data), (flags), (reg), (shift), \ |
813 | (width), (clk_divider_flags), NULL, (lock)) |
814 | /** |
815 | * clk_hw_register_divider_table - register a table based divider clock with |
816 | * the clock framework |
817 | * @dev: device registering this clock |
818 | * @name: name of this clock |
819 | * @parent_name: name of clock's parent |
820 | * @flags: framework-specific flags |
821 | * @reg: register address to adjust divider |
822 | * @shift: number of bits to shift the bitfield |
823 | * @width: width of the bitfield |
824 | * @clk_divider_flags: divider-specific flags for this clock |
825 | * @table: array of divider/value pairs ending with a div set to 0 |
826 | * @lock: shared register lock for this clock |
827 | */ |
828 | #define clk_hw_register_divider_table(dev, name, parent_name, flags, reg, \ |
829 | shift, width, clk_divider_flags, table, \ |
830 | lock) \ |
831 | __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \ |
832 | NULL, (flags), (reg), (shift), (width), \ |
833 | (clk_divider_flags), (table), (lock)) |
834 | /** |
835 | * clk_hw_register_divider_table_parent_hw - register a table based divider |
836 | * clock with the clock framework |
837 | * @dev: device registering this clock |
838 | * @name: name of this clock |
839 | * @parent_hw: pointer to parent clk |
840 | * @flags: framework-specific flags |
841 | * @reg: register address to adjust divider |
842 | * @shift: number of bits to shift the bitfield |
843 | * @width: width of the bitfield |
844 | * @clk_divider_flags: divider-specific flags for this clock |
845 | * @table: array of divider/value pairs ending with a div set to 0 |
846 | * @lock: shared register lock for this clock |
847 | */ |
848 | #define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags, \ |
849 | reg, shift, width, \ |
850 | clk_divider_flags, table, \ |
851 | lock) \ |
852 | __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \ |
853 | NULL, (flags), (reg), (shift), (width), \ |
854 | (clk_divider_flags), (table), (lock)) |
855 | /** |
856 | * clk_hw_register_divider_table_parent_data - register a table based divider |
857 | * clock with the clock framework |
858 | * @dev: device registering this clock |
859 | * @name: name of this clock |
860 | * @parent_data: parent clk data |
861 | * @flags: framework-specific flags |
862 | * @reg: register address to adjust divider |
863 | * @shift: number of bits to shift the bitfield |
864 | * @width: width of the bitfield |
865 | * @clk_divider_flags: divider-specific flags for this clock |
866 | * @table: array of divider/value pairs ending with a div set to 0 |
867 | * @lock: shared register lock for this clock |
868 | */ |
869 | #define clk_hw_register_divider_table_parent_data(dev, name, parent_data, \ |
870 | flags, reg, shift, width, \ |
871 | clk_divider_flags, table, \ |
872 | lock) \ |
873 | __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \ |
874 | (parent_data), (flags), (reg), (shift), \ |
875 | (width), (clk_divider_flags), (table), \ |
876 | (lock)) |
877 | /** |
878 | * devm_clk_hw_register_divider - register a divider clock with the clock framework |
879 | * @dev: device registering this clock |
880 | * @name: name of this clock |
881 | * @parent_name: name of clock's parent |
882 | * @flags: framework-specific flags |
883 | * @reg: register address to adjust divider |
884 | * @shift: number of bits to shift the bitfield |
885 | * @width: width of the bitfield |
886 | * @clk_divider_flags: divider-specific flags for this clock |
887 | * @lock: shared register lock for this clock |
888 | */ |
889 | #define devm_clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \ |
890 | width, clk_divider_flags, lock) \ |
891 | __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \ |
892 | NULL, (flags), (reg), (shift), (width), \ |
893 | (clk_divider_flags), NULL, (lock)) |
894 | /** |
895 | * devm_clk_hw_register_divider_parent_hw - register a divider clock with the clock framework |
896 | * @dev: device registering this clock |
897 | * @name: name of this clock |
898 | * @parent_hw: pointer to parent clk |
899 | * @flags: framework-specific flags |
900 | * @reg: register address to adjust divider |
901 | * @shift: number of bits to shift the bitfield |
902 | * @width: width of the bitfield |
903 | * @clk_divider_flags: divider-specific flags for this clock |
904 | * @lock: shared register lock for this clock |
905 | */ |
906 | #define devm_clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, \ |
907 | reg, shift, width, \ |
908 | clk_divider_flags, lock) \ |
909 | __devm_clk_hw_register_divider((dev), NULL, (name), NULL, \ |
910 | (parent_hw), NULL, (flags), (reg), \ |
911 | (shift), (width), (clk_divider_flags), \ |
912 | NULL, (lock)) |
913 | /** |
914 | * devm_clk_hw_register_divider_table - register a table based divider clock |
915 | * with the clock framework (devres variant) |
916 | * @dev: device registering this clock |
917 | * @name: name of this clock |
918 | * @parent_name: name of clock's parent |
919 | * @flags: framework-specific flags |
920 | * @reg: register address to adjust divider |
921 | * @shift: number of bits to shift the bitfield |
922 | * @width: width of the bitfield |
923 | * @clk_divider_flags: divider-specific flags for this clock |
924 | * @table: array of divider/value pairs ending with a div set to 0 |
925 | * @lock: shared register lock for this clock |
926 | */ |
927 | #define devm_clk_hw_register_divider_table(dev, name, parent_name, flags, \ |
928 | reg, shift, width, \ |
929 | clk_divider_flags, table, lock) \ |
930 | __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), \ |
931 | NULL, NULL, (flags), (reg), (shift), \ |
932 | (width), (clk_divider_flags), (table), \ |
933 | (lock)) |
934 | |
935 | void clk_unregister_divider(struct clk *clk); |
936 | void clk_hw_unregister_divider(struct clk_hw *hw); |
937 | |
938 | /** |
939 | * struct clk_mux - multiplexer clock |
940 | * |
941 | * @hw: handle between common and hardware-specific interfaces |
942 | * @reg: register controlling multiplexer |
943 | * @table: array of register values corresponding to the parent index |
944 | * @shift: shift to multiplexer bit field |
945 | * @mask: mask of mutliplexer bit field |
946 | * @flags: hardware-specific flags |
947 | * @lock: register lock |
948 | * |
949 | * Clock with multiple selectable parents. Implements .get_parent, .set_parent |
950 | * and .recalc_rate |
951 | * |
952 | * Flags: |
953 | * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 |
954 | * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) |
955 | * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this |
956 | * register, and mask of mux bits are in higher 16-bit of this register. |
957 | * While setting the mux bits, higher 16-bit should also be updated to |
958 | * indicate changing mux bits. |
959 | * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the |
960 | * .get_parent clk_op. |
961 | * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired |
962 | * frequency. |
963 | * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for |
964 | * the mux register. Setting this flag makes the register accesses big |
965 | * endian. |
966 | */ |
967 | struct clk_mux { |
968 | struct clk_hw hw; |
969 | void __iomem *reg; |
970 | const u32 *table; |
971 | u32 mask; |
972 | u8 shift; |
973 | u8 flags; |
974 | spinlock_t *lock; |
975 | }; |
976 | |
977 | #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) |
978 | |
979 | #define CLK_MUX_INDEX_ONE BIT(0) |
980 | #define CLK_MUX_INDEX_BIT BIT(1) |
981 | #define CLK_MUX_HIWORD_MASK BIT(2) |
982 | #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */ |
983 | #define CLK_MUX_ROUND_CLOSEST BIT(4) |
984 | #define CLK_MUX_BIG_ENDIAN BIT(5) |
985 | |
986 | extern const struct clk_ops clk_mux_ops; |
987 | extern const struct clk_ops clk_mux_ro_ops; |
988 | |
989 | struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np, |
990 | const char *name, u8 num_parents, |
991 | const char * const *parent_names, |
992 | const struct clk_hw **parent_hws, |
993 | const struct clk_parent_data *parent_data, |
994 | unsigned long flags, void __iomem *reg, u8 shift, u32 mask, |
995 | u8 clk_mux_flags, const u32 *table, spinlock_t *lock); |
996 | struct clk_hw *__devm_clk_hw_register_mux(struct device *dev, struct device_node *np, |
997 | const char *name, u8 num_parents, |
998 | const char * const *parent_names, |
999 | const struct clk_hw **parent_hws, |
1000 | const struct clk_parent_data *parent_data, |
1001 | unsigned long flags, void __iomem *reg, u8 shift, u32 mask, |
1002 | u8 clk_mux_flags, const u32 *table, spinlock_t *lock); |
1003 | struct clk *clk_register_mux_table(struct device *dev, const char *name, |
1004 | const char * const *parent_names, u8 num_parents, |
1005 | unsigned long flags, void __iomem *reg, u8 shift, u32 mask, |
1006 | u8 clk_mux_flags, const u32 *table, spinlock_t *lock); |
1007 | |
1008 | #define clk_register_mux(dev, name, parent_names, num_parents, flags, reg, \ |
1009 | shift, width, clk_mux_flags, lock) \ |
1010 | clk_register_mux_table((dev), (name), (parent_names), (num_parents), \ |
1011 | (flags), (reg), (shift), BIT((width)) - 1, \ |
1012 | (clk_mux_flags), NULL, (lock)) |
1013 | #define clk_hw_register_mux_table(dev, name, parent_names, num_parents, \ |
1014 | flags, reg, shift, mask, clk_mux_flags, \ |
1015 | table, lock) \ |
1016 | __clk_hw_register_mux((dev), NULL, (name), (num_parents), \ |
1017 | (parent_names), NULL, NULL, (flags), (reg), \ |
1018 | (shift), (mask), (clk_mux_flags), (table), \ |
1019 | (lock)) |
1020 | #define clk_hw_register_mux_table_parent_data(dev, name, parent_data, \ |
1021 | num_parents, flags, reg, shift, mask, \ |
1022 | clk_mux_flags, table, lock) \ |
1023 | __clk_hw_register_mux((dev), NULL, (name), (num_parents), \ |
1024 | NULL, NULL, (parent_data), (flags), (reg), \ |
1025 | (shift), (mask), (clk_mux_flags), (table), \ |
1026 | (lock)) |
1027 | #define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \ |
1028 | shift, width, clk_mux_flags, lock) \ |
1029 | __clk_hw_register_mux((dev), NULL, (name), (num_parents), \ |
1030 | (parent_names), NULL, NULL, (flags), (reg), \ |
1031 | (shift), BIT((width)) - 1, (clk_mux_flags), \ |
1032 | NULL, (lock)) |
1033 | #define clk_hw_register_mux_hws(dev, name, parent_hws, num_parents, flags, \ |
1034 | reg, shift, width, clk_mux_flags, lock) \ |
1035 | __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \ |
1036 | (parent_hws), NULL, (flags), (reg), (shift), \ |
1037 | BIT((width)) - 1, (clk_mux_flags), NULL, (lock)) |
1038 | #define clk_hw_register_mux_parent_data(dev, name, parent_data, num_parents, \ |
1039 | flags, reg, shift, width, \ |
1040 | clk_mux_flags, lock) \ |
1041 | __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \ |
1042 | (parent_data), (flags), (reg), (shift), \ |
1043 | BIT((width)) - 1, (clk_mux_flags), NULL, (lock)) |
1044 | #define clk_hw_register_mux_parent_data_table(dev, name, parent_data, \ |
1045 | num_parents, flags, reg, shift, \ |
1046 | width, clk_mux_flags, table, \ |
1047 | lock) \ |
1048 | __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \ |
1049 | (parent_data), (flags), (reg), (shift), \ |
1050 | BIT((width)) - 1, (clk_mux_flags), table, (lock)) |
1051 | #define devm_clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \ |
1052 | shift, width, clk_mux_flags, lock) \ |
1053 | __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), \ |
1054 | (parent_names), NULL, NULL, (flags), (reg), \ |
1055 | (shift), BIT((width)) - 1, (clk_mux_flags), \ |
1056 | NULL, (lock)) |
1057 | #define devm_clk_hw_register_mux_parent_hws(dev, name, parent_hws, \ |
1058 | num_parents, flags, reg, shift, \ |
1059 | width, clk_mux_flags, lock) \ |
1060 | __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \ |
1061 | (parent_hws), NULL, (flags), (reg), \ |
1062 | (shift), BIT((width)) - 1, \ |
1063 | (clk_mux_flags), NULL, (lock)) |
1064 | #define devm_clk_hw_register_mux_parent_data_table(dev, name, parent_data, \ |
1065 | num_parents, flags, reg, shift, \ |
1066 | width, clk_mux_flags, table, \ |
1067 | lock) \ |
1068 | __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \ |
1069 | NULL, (parent_data), (flags), (reg), (shift), \ |
1070 | BIT((width)) - 1, (clk_mux_flags), table, (lock)) |
1071 | |
1072 | int clk_mux_val_to_index(struct clk_hw *hw, const u32 *table, unsigned int flags, |
1073 | unsigned int val); |
1074 | unsigned int clk_mux_index_to_val(const u32 *table, unsigned int flags, u8 index); |
1075 | |
1076 | void clk_unregister_mux(struct clk *clk); |
1077 | void clk_hw_unregister_mux(struct clk_hw *hw); |
1078 | |
1079 | void of_fixed_factor_clk_setup(struct device_node *node); |
1080 | |
1081 | /** |
1082 | * struct clk_fixed_factor - fixed multiplier and divider clock |
1083 | * |
1084 | * @hw: handle between common and hardware-specific interfaces |
1085 | * @mult: multiplier |
1086 | * @div: divider |
1087 | * |
1088 | * Clock with a fixed multiplier and divider. The output frequency is the |
1089 | * parent clock rate divided by div and multiplied by mult. |
1090 | * Implements .recalc_rate, .set_rate and .round_rate |
1091 | */ |
1092 | |
1093 | struct clk_fixed_factor { |
1094 | struct clk_hw hw; |
1095 | unsigned int mult; |
1096 | unsigned int div; |
1097 | }; |
1098 | |
1099 | #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw) |
1100 | |
1101 | extern const struct clk_ops clk_fixed_factor_ops; |
1102 | struct clk *clk_register_fixed_factor(struct device *dev, const char *name, |
1103 | const char *parent_name, unsigned long flags, |
1104 | unsigned int mult, unsigned int div); |
1105 | void clk_unregister_fixed_factor(struct clk *clk); |
1106 | struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, |
1107 | const char *name, const char *parent_name, unsigned long flags, |
1108 | unsigned int mult, unsigned int div); |
1109 | void clk_hw_unregister_fixed_factor(struct clk_hw *hw); |
1110 | struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, |
1111 | const char *name, const char *parent_name, unsigned long flags, |
1112 | unsigned int mult, unsigned int div); |
1113 | struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev, |
1114 | const char *name, unsigned int index, unsigned long flags, |
1115 | unsigned int mult, unsigned int div); |
1116 | |
1117 | struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev, |
1118 | const char *name, const struct clk_hw *parent_hw, |
1119 | unsigned long flags, unsigned int mult, unsigned int div); |
1120 | |
1121 | struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev, |
1122 | const char *name, const struct clk_hw *parent_hw, |
1123 | unsigned long flags, unsigned int mult, unsigned int div); |
1124 | /** |
1125 | * struct clk_fractional_divider - adjustable fractional divider clock |
1126 | * |
1127 | * @hw: handle between common and hardware-specific interfaces |
1128 | * @reg: register containing the divider |
1129 | * @mshift: shift to the numerator bit field |
1130 | * @mwidth: width of the numerator bit field |
1131 | * @nshift: shift to the denominator bit field |
1132 | * @nwidth: width of the denominator bit field |
1133 | * @approximation: clk driver's callback for calculating the divider clock |
1134 | * @lock: register lock |
1135 | * |
1136 | * Clock with adjustable fractional divider affecting its output frequency. |
1137 | * |
1138 | * @flags: |
1139 | * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator |
1140 | * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED |
1141 | * is set then the numerator and denominator are both the value read |
1142 | * plus one. |
1143 | * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are |
1144 | * used for the divider register. Setting this flag makes the register |
1145 | * accesses big endian. |
1146 | * CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - By default the resulting fraction might |
1147 | * be saturated and the caller will get quite far from the good enough |
1148 | * approximation. Instead the caller may require, by setting this flag, |
1149 | * to shift left by a few bits in case, when the asked one is quite small |
1150 | * to satisfy the desired range of denominator. It assumes that on the |
1151 | * caller's side the power-of-two capable prescaler exists. |
1152 | */ |
1153 | struct clk_fractional_divider { |
1154 | struct clk_hw hw; |
1155 | void __iomem *reg; |
1156 | u8 mshift; |
1157 | u8 mwidth; |
1158 | u8 nshift; |
1159 | u8 nwidth; |
1160 | u8 flags; |
1161 | void (*approximation)(struct clk_hw *hw, |
1162 | unsigned long rate, unsigned long *parent_rate, |
1163 | unsigned long *m, unsigned long *n); |
1164 | spinlock_t *lock; |
1165 | }; |
1166 | |
1167 | #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) |
1168 | |
1169 | #define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0) |
1170 | #define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1) |
1171 | #define CLK_FRAC_DIVIDER_POWER_OF_TWO_PS BIT(2) |
1172 | |
1173 | struct clk *clk_register_fractional_divider(struct device *dev, |
1174 | const char *name, const char *parent_name, unsigned long flags, |
1175 | void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, |
1176 | u8 clk_divider_flags, spinlock_t *lock); |
1177 | struct clk_hw *clk_hw_register_fractional_divider(struct device *dev, |
1178 | const char *name, const char *parent_name, unsigned long flags, |
1179 | void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, |
1180 | u8 clk_divider_flags, spinlock_t *lock); |
1181 | void clk_hw_unregister_fractional_divider(struct clk_hw *hw); |
1182 | |
1183 | /** |
1184 | * struct clk_multiplier - adjustable multiplier clock |
1185 | * |
1186 | * @hw: handle between common and hardware-specific interfaces |
1187 | * @reg: register containing the multiplier |
1188 | * @shift: shift to the multiplier bit field |
1189 | * @width: width of the multiplier bit field |
1190 | * @lock: register lock |
1191 | * |
1192 | * Clock with an adjustable multiplier affecting its output frequency. |
1193 | * Implements .recalc_rate, .set_rate and .round_rate |
1194 | * |
1195 | * @flags: |
1196 | * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read |
1197 | * from the register, with 0 being a valid value effectively |
1198 | * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is |
1199 | * set, then a null multiplier will be considered as a bypass, |
1200 | * leaving the parent rate unmodified. |
1201 | * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be |
1202 | * rounded to the closest integer instead of the down one. |
1203 | * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are |
1204 | * used for the multiplier register. Setting this flag makes the register |
1205 | * accesses big endian. |
1206 | */ |
1207 | struct clk_multiplier { |
1208 | struct clk_hw hw; |
1209 | void __iomem *reg; |
1210 | u8 shift; |
1211 | u8 width; |
1212 | u8 flags; |
1213 | spinlock_t *lock; |
1214 | }; |
1215 | |
1216 | #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw) |
1217 | |
1218 | #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0) |
1219 | #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1) |
1220 | #define CLK_MULTIPLIER_BIG_ENDIAN BIT(2) |
1221 | |
1222 | extern const struct clk_ops clk_multiplier_ops; |
1223 | |
1224 | /*** |
1225 | * struct clk_composite - aggregate clock of mux, divider and gate clocks |
1226 | * |
1227 | * @hw: handle between common and hardware-specific interfaces |
1228 | * @mux_hw: handle between composite and hardware-specific mux clock |
1229 | * @rate_hw: handle between composite and hardware-specific rate clock |
1230 | * @gate_hw: handle between composite and hardware-specific gate clock |
1231 | * @mux_ops: clock ops for mux |
1232 | * @rate_ops: clock ops for rate |
1233 | * @gate_ops: clock ops for gate |
1234 | */ |
1235 | struct clk_composite { |
1236 | struct clk_hw hw; |
1237 | struct clk_ops ops; |
1238 | |
1239 | struct clk_hw *mux_hw; |
1240 | struct clk_hw *rate_hw; |
1241 | struct clk_hw *gate_hw; |
1242 | |
1243 | const struct clk_ops *mux_ops; |
1244 | const struct clk_ops *rate_ops; |
1245 | const struct clk_ops *gate_ops; |
1246 | }; |
1247 | |
1248 | #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw) |
1249 | |
1250 | struct clk *clk_register_composite(struct device *dev, const char *name, |
1251 | const char * const *parent_names, int num_parents, |
1252 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, |
1253 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, |
1254 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, |
1255 | unsigned long flags); |
1256 | struct clk *clk_register_composite_pdata(struct device *dev, const char *name, |
1257 | const struct clk_parent_data *parent_data, int num_parents, |
1258 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, |
1259 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, |
1260 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, |
1261 | unsigned long flags); |
1262 | void clk_unregister_composite(struct clk *clk); |
1263 | struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name, |
1264 | const char * const *parent_names, int num_parents, |
1265 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, |
1266 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, |
1267 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, |
1268 | unsigned long flags); |
1269 | struct clk_hw *clk_hw_register_composite_pdata(struct device *dev, |
1270 | const char *name, |
1271 | const struct clk_parent_data *parent_data, int num_parents, |
1272 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, |
1273 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, |
1274 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, |
1275 | unsigned long flags); |
1276 | struct clk_hw *devm_clk_hw_register_composite_pdata(struct device *dev, |
1277 | const char *name, const struct clk_parent_data *parent_data, |
1278 | int num_parents, |
1279 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, |
1280 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, |
1281 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, |
1282 | unsigned long flags); |
1283 | void clk_hw_unregister_composite(struct clk_hw *hw); |
1284 | |
1285 | struct clk *clk_register(struct device *dev, struct clk_hw *hw); |
1286 | struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); |
1287 | |
1288 | int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw); |
1289 | int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw); |
1290 | int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw); |
1291 | |
1292 | void clk_unregister(struct clk *clk); |
1293 | |
1294 | void clk_hw_unregister(struct clk_hw *hw); |
1295 | |
1296 | /* helper functions */ |
1297 | const char *__clk_get_name(const struct clk *clk); |
1298 | const char *clk_hw_get_name(const struct clk_hw *hw); |
1299 | #ifdef CONFIG_COMMON_CLK |
1300 | struct clk_hw *__clk_get_hw(struct clk *clk); |
1301 | #else |
1302 | static inline struct clk_hw *__clk_get_hw(struct clk *clk) |
1303 | { |
1304 | return (struct clk_hw *)clk; |
1305 | } |
1306 | #endif |
1307 | |
1308 | struct clk *clk_hw_get_clk(struct clk_hw *hw, const char *con_id); |
1309 | struct clk *devm_clk_hw_get_clk(struct device *dev, struct clk_hw *hw, |
1310 | const char *con_id); |
1311 | |
1312 | unsigned int clk_hw_get_num_parents(const struct clk_hw *hw); |
1313 | struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw); |
1314 | struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw, |
1315 | unsigned int index); |
1316 | int clk_hw_get_parent_index(struct clk_hw *hw); |
1317 | int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent); |
1318 | unsigned int __clk_get_enable_count(struct clk *clk); |
1319 | unsigned long clk_hw_get_rate(const struct clk_hw *hw); |
1320 | unsigned long clk_hw_get_flags(const struct clk_hw *hw); |
1321 | #define clk_hw_can_set_rate_parent(hw) \ |
1322 | (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT) |
1323 | |
1324 | bool clk_hw_is_prepared(const struct clk_hw *hw); |
1325 | bool clk_hw_rate_is_protected(const struct clk_hw *hw); |
1326 | bool clk_hw_is_enabled(const struct clk_hw *hw); |
1327 | bool __clk_is_enabled(struct clk *clk); |
1328 | struct clk *__clk_lookup(const char *name); |
1329 | int __clk_mux_determine_rate(struct clk_hw *hw, |
1330 | struct clk_rate_request *req); |
1331 | int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req); |
1332 | int __clk_mux_determine_rate_closest(struct clk_hw *hw, |
1333 | struct clk_rate_request *req); |
1334 | int clk_mux_determine_rate_flags(struct clk_hw *hw, |
1335 | struct clk_rate_request *req, |
1336 | unsigned long flags); |
1337 | int clk_hw_determine_rate_no_reparent(struct clk_hw *hw, |
1338 | struct clk_rate_request *req); |
1339 | void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent); |
1340 | void clk_hw_get_rate_range(struct clk_hw *hw, unsigned long *min_rate, |
1341 | unsigned long *max_rate); |
1342 | void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate, |
1343 | unsigned long max_rate); |
1344 | |
1345 | static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src) |
1346 | { |
1347 | dst->clk = src->clk; |
1348 | dst->core = src->core; |
1349 | } |
1350 | |
1351 | static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate, |
1352 | unsigned long *prate, |
1353 | const struct clk_div_table *table, |
1354 | u8 width, unsigned long flags) |
1355 | { |
1356 | return divider_round_rate_parent(hw, parent: clk_hw_get_parent(hw), |
1357 | rate, prate, table, width, flags); |
1358 | } |
1359 | |
1360 | static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate, |
1361 | unsigned long *prate, |
1362 | const struct clk_div_table *table, |
1363 | u8 width, unsigned long flags, |
1364 | unsigned int val) |
1365 | { |
1366 | return divider_ro_round_rate_parent(hw, parent: clk_hw_get_parent(hw), |
1367 | rate, prate, table, width, flags, |
1368 | val); |
1369 | } |
1370 | |
1371 | /* |
1372 | * FIXME clock api without lock protection |
1373 | */ |
1374 | unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate); |
1375 | |
1376 | struct clk_onecell_data { |
1377 | struct clk **clks; |
1378 | unsigned int clk_num; |
1379 | }; |
1380 | |
1381 | struct clk_hw_onecell_data { |
1382 | unsigned int num; |
1383 | struct clk_hw *hws[] __counted_by(num); |
1384 | }; |
1385 | |
1386 | #define CLK_OF_DECLARE(name, compat, fn) \ |
1387 | static void __init __##name##_of_clk_init_declare(struct device_node *np) \ |
1388 | { \ |
1389 | fn(np); \ |
1390 | fwnode_dev_initialized(of_fwnode_handle(np), true); \ |
1391 | } \ |
1392 | OF_DECLARE_1(clk, name, compat, __##name##_of_clk_init_declare) |
1393 | |
1394 | /* |
1395 | * Use this macro when you have a driver that requires two initialization |
1396 | * routines, one at of_clk_init(), and one at platform device probe |
1397 | */ |
1398 | #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \ |
1399 | static void __init name##_of_clk_init_driver(struct device_node *np) \ |
1400 | { \ |
1401 | of_node_clear_flag(np, OF_POPULATED); \ |
1402 | fn(np); \ |
1403 | } \ |
1404 | OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver) |
1405 | |
1406 | #define CLK_HW_INIT(_name, _parent, _ops, _flags) \ |
1407 | (&(struct clk_init_data) { \ |
1408 | .flags = _flags, \ |
1409 | .name = _name, \ |
1410 | .parent_names = (const char *[]) { _parent }, \ |
1411 | .num_parents = 1, \ |
1412 | .ops = _ops, \ |
1413 | }) |
1414 | |
1415 | #define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \ |
1416 | (&(struct clk_init_data) { \ |
1417 | .flags = _flags, \ |
1418 | .name = _name, \ |
1419 | .parent_hws = (const struct clk_hw*[]) { _parent }, \ |
1420 | .num_parents = 1, \ |
1421 | .ops = _ops, \ |
1422 | }) |
1423 | |
1424 | /* |
1425 | * This macro is intended for drivers to be able to share the otherwise |
1426 | * individual struct clk_hw[] compound literals created by the compiler |
1427 | * when using CLK_HW_INIT_HW. It does NOT support multiple parents. |
1428 | */ |
1429 | #define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags) \ |
1430 | (&(struct clk_init_data) { \ |
1431 | .flags = _flags, \ |
1432 | .name = _name, \ |
1433 | .parent_hws = _parent, \ |
1434 | .num_parents = 1, \ |
1435 | .ops = _ops, \ |
1436 | }) |
1437 | |
1438 | #define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags) \ |
1439 | (&(struct clk_init_data) { \ |
1440 | .flags = _flags, \ |
1441 | .name = _name, \ |
1442 | .parent_data = (const struct clk_parent_data[]) { \ |
1443 | { .fw_name = _parent }, \ |
1444 | }, \ |
1445 | .num_parents = 1, \ |
1446 | .ops = _ops, \ |
1447 | }) |
1448 | |
1449 | #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \ |
1450 | (&(struct clk_init_data) { \ |
1451 | .flags = _flags, \ |
1452 | .name = _name, \ |
1453 | .parent_names = _parents, \ |
1454 | .num_parents = ARRAY_SIZE(_parents), \ |
1455 | .ops = _ops, \ |
1456 | }) |
1457 | |
1458 | #define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \ |
1459 | (&(struct clk_init_data) { \ |
1460 | .flags = _flags, \ |
1461 | .name = _name, \ |
1462 | .parent_hws = _parents, \ |
1463 | .num_parents = ARRAY_SIZE(_parents), \ |
1464 | .ops = _ops, \ |
1465 | }) |
1466 | |
1467 | #define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \ |
1468 | (&(struct clk_init_data) { \ |
1469 | .flags = _flags, \ |
1470 | .name = _name, \ |
1471 | .parent_data = _parents, \ |
1472 | .num_parents = ARRAY_SIZE(_parents), \ |
1473 | .ops = _ops, \ |
1474 | }) |
1475 | |
1476 | #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \ |
1477 | (&(struct clk_init_data) { \ |
1478 | .flags = _flags, \ |
1479 | .name = _name, \ |
1480 | .parent_names = NULL, \ |
1481 | .num_parents = 0, \ |
1482 | .ops = _ops, \ |
1483 | }) |
1484 | |
1485 | #define CLK_FIXED_FACTOR(_struct, _name, _parent, \ |
1486 | _div, _mult, _flags) \ |
1487 | struct clk_fixed_factor _struct = { \ |
1488 | .div = _div, \ |
1489 | .mult = _mult, \ |
1490 | .hw.init = CLK_HW_INIT(_name, \ |
1491 | _parent, \ |
1492 | &clk_fixed_factor_ops, \ |
1493 | _flags), \ |
1494 | } |
1495 | |
1496 | #define CLK_FIXED_FACTOR_HW(_struct, _name, _parent, \ |
1497 | _div, _mult, _flags) \ |
1498 | struct clk_fixed_factor _struct = { \ |
1499 | .div = _div, \ |
1500 | .mult = _mult, \ |
1501 | .hw.init = CLK_HW_INIT_HW(_name, \ |
1502 | _parent, \ |
1503 | &clk_fixed_factor_ops, \ |
1504 | _flags), \ |
1505 | } |
1506 | |
1507 | /* |
1508 | * This macro allows the driver to reuse the _parent array for multiple |
1509 | * fixed factor clk declarations. |
1510 | */ |
1511 | #define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent, \ |
1512 | _div, _mult, _flags) \ |
1513 | struct clk_fixed_factor _struct = { \ |
1514 | .div = _div, \ |
1515 | .mult = _mult, \ |
1516 | .hw.init = CLK_HW_INIT_HWS(_name, \ |
1517 | _parent, \ |
1518 | &clk_fixed_factor_ops, \ |
1519 | _flags), \ |
1520 | } |
1521 | |
1522 | #define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent, \ |
1523 | _div, _mult, _flags) \ |
1524 | struct clk_fixed_factor _struct = { \ |
1525 | .div = _div, \ |
1526 | .mult = _mult, \ |
1527 | .hw.init = CLK_HW_INIT_FW_NAME(_name, \ |
1528 | _parent, \ |
1529 | &clk_fixed_factor_ops, \ |
1530 | _flags), \ |
1531 | } |
1532 | |
1533 | #ifdef CONFIG_OF |
1534 | int of_clk_add_provider(struct device_node *np, |
1535 | struct clk *(*clk_src_get)(struct of_phandle_args *args, |
1536 | void *data), |
1537 | void *data); |
1538 | int of_clk_add_hw_provider(struct device_node *np, |
1539 | struct clk_hw *(*get)(struct of_phandle_args *clkspec, |
1540 | void *data), |
1541 | void *data); |
1542 | int devm_of_clk_add_hw_provider(struct device *dev, |
1543 | struct clk_hw *(*get)(struct of_phandle_args *clkspec, |
1544 | void *data), |
1545 | void *data); |
1546 | void of_clk_del_provider(struct device_node *np); |
1547 | |
1548 | struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, |
1549 | void *data); |
1550 | struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec, |
1551 | void *data); |
1552 | struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); |
1553 | struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec, |
1554 | void *data); |
1555 | int of_clk_parent_fill(struct device_node *np, const char **parents, |
1556 | unsigned int size); |
1557 | int of_clk_detect_critical(struct device_node *np, int index, |
1558 | unsigned long *flags); |
1559 | |
1560 | #else /* !CONFIG_OF */ |
1561 | |
1562 | static inline int of_clk_add_provider(struct device_node *np, |
1563 | struct clk *(*clk_src_get)(struct of_phandle_args *args, |
1564 | void *data), |
1565 | void *data) |
1566 | { |
1567 | return 0; |
1568 | } |
1569 | static inline int of_clk_add_hw_provider(struct device_node *np, |
1570 | struct clk_hw *(*get)(struct of_phandle_args *clkspec, |
1571 | void *data), |
1572 | void *data) |
1573 | { |
1574 | return 0; |
1575 | } |
1576 | static inline int devm_of_clk_add_hw_provider(struct device *dev, |
1577 | struct clk_hw *(*get)(struct of_phandle_args *clkspec, |
1578 | void *data), |
1579 | void *data) |
1580 | { |
1581 | return 0; |
1582 | } |
1583 | static inline void of_clk_del_provider(struct device_node *np) {} |
1584 | |
1585 | static inline struct clk *of_clk_src_simple_get( |
1586 | struct of_phandle_args *clkspec, void *data) |
1587 | { |
1588 | return ERR_PTR(-ENOENT); |
1589 | } |
1590 | static inline struct clk_hw * |
1591 | of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data) |
1592 | { |
1593 | return ERR_PTR(-ENOENT); |
1594 | } |
1595 | static inline struct clk *of_clk_src_onecell_get( |
1596 | struct of_phandle_args *clkspec, void *data) |
1597 | { |
1598 | return ERR_PTR(-ENOENT); |
1599 | } |
1600 | static inline struct clk_hw * |
1601 | of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data) |
1602 | { |
1603 | return ERR_PTR(-ENOENT); |
1604 | } |
1605 | static inline int of_clk_parent_fill(struct device_node *np, |
1606 | const char **parents, unsigned int size) |
1607 | { |
1608 | return 0; |
1609 | } |
1610 | static inline int of_clk_detect_critical(struct device_node *np, int index, |
1611 | unsigned long *flags) |
1612 | { |
1613 | return 0; |
1614 | } |
1615 | #endif /* CONFIG_OF */ |
1616 | |
1617 | void clk_gate_restore_context(struct clk_hw *hw); |
1618 | |
1619 | #endif /* CLK_PROVIDER_H */ |
1620 | |