| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * include/linux/clk/at91_pmc.h |
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| 4 | * |
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| 5 | * Copyright (C) 2005 Ivan Kokshaysky |
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| 6 | * Copyright (C) SAN People |
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| 7 | * |
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| 8 | * Power Management Controller (PMC) - System peripherals registers. |
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| 9 | * Based on AT91RM9200 datasheet revision E. |
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| 10 | */ |
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| 11 | |
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| 12 | #ifndef AT91_PMC_H |
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| 13 | #define AT91_PMC_H |
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| 14 | |
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| 15 | #include <linux/bits.h> |
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| 16 | |
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| 17 | #define AT91_PMC_V1 (1) /* PMC version 1 */ |
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| 18 | #define AT91_PMC_V2 (2) /* PMC version 2 [SAM9X60] */ |
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| 19 | |
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| 20 | #define AT91_PMC_SCER 0x00 /* System Clock Enable Register */ |
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| 21 | #define AT91_PMC_SCDR 0x04 /* System Clock Disable Register */ |
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| 22 | |
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| 23 | #define AT91_PMC_SCSR 0x08 /* System Clock Status Register */ |
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| 24 | #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ |
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| 25 | #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ |
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| 26 | #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ |
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| 27 | #define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ |
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| 28 | #define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ |
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| 29 | #define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ |
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| 30 | #define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ |
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| 31 | #define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ |
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| 32 | #define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ |
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| 33 | #define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ |
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| 34 | #define AT91_PMC_PCK4 (1 << 12) /* Programmable Clock 4 [AT572D940HF only] */ |
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| 35 | #define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ |
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| 36 | #define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ |
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| 37 | |
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| 38 | #define AT91_PMC_PLL_CTRL0 0x0C /* PLL Control Register 0 [for SAM9X60] */ |
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| 39 | #define AT91_PMC_PLL_CTRL0_ENPLL (1 << 28) /* Enable PLL */ |
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| 40 | #define AT91_PMC_PLL_CTRL0_ENPLLCK (1 << 29) /* Enable PLL clock for PMC */ |
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| 41 | #define AT91_PMC_PLL_CTRL0_ENLOCK (1 << 31) /* Enable PLL lock */ |
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| 42 | |
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| 43 | #define AT91_PMC_PLL_CTRL1 0x10 /* PLL Control Register 1 [for SAM9X60] */ |
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| 44 | |
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| 45 | #define AT91_PMC_PCER 0x10 /* Peripheral Clock Enable Register */ |
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| 46 | #define AT91_PMC_PCDR 0x14 /* Peripheral Clock Disable Register */ |
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| 47 | #define AT91_PMC_PCSR 0x18 /* Peripheral Clock Status Register */ |
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| 48 | |
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| 49 | #define AT91_PMC_PLL_ACR 0x18 /* PLL Analog Control Register [for SAM9X60] */ |
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| 50 | #define AT91_PMC_PLL_ACR_DEFAULT_UPLL UL(0x12020010) /* Default PLL ACR value for UPLL */ |
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| 51 | #define AT91_PMC_PLL_ACR_DEFAULT_PLLA UL(0x00020010) /* Default PLL ACR value for PLLA */ |
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| 52 | #define AT91_PMC_PLL_ACR_UTMIVR (1 << 12) /* UPLL Voltage regulator Control */ |
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| 53 | #define AT91_PMC_PLL_ACR_UTMIBG (1 << 13) /* UPLL Bandgap Control */ |
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| 54 | |
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| 55 | #define AT91_CKGR_UCKR 0x1C /* UTMI Clock Register [some SAM9] */ |
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| 56 | #define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ |
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| 57 | #define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ |
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| 58 | #define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ |
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| 59 | #define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */ |
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| 60 | |
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| 61 | #define AT91_PMC_PLL_UPDT 0x1C /* PMC PLL update register [for SAM9X60] */ |
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| 62 | #define AT91_PMC_PLL_UPDT_UPDATE (1 << 8) /* Update PLL settings */ |
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| 63 | #define AT91_PMC_PLL_UPDT_ID (1 << 0) /* PLL ID */ |
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| 64 | #define AT91_PMC_PLL_UPDT_ID_MSK (0xf) /* PLL ID mask */ |
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| 65 | #define AT91_PMC_PLL_UPDT_STUPTIM (0xff << 16) /* Startup time */ |
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| 66 | |
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| 67 | #define AT91_CKGR_MOR 0x20 /* Main Oscillator Register [not on SAM9RL] */ |
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| 68 | #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ |
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| 69 | #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */ |
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| 70 | #define AT91_PMC_WAITMODE (1 << 2) /* Wait Mode Command */ |
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| 71 | #define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */ |
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| 72 | #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ |
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| 73 | #define AT91_PMC_KEY_MASK (0xff << 16) |
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| 74 | #define AT91_PMC_KEY (0x37 << 16) /* MOR Writing Key */ |
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| 75 | #define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */ |
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| 76 | #define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */ |
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| 77 | |
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| 78 | #define AT91_CKGR_MCFR 0x24 /* Main Clock Frequency Register */ |
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| 79 | #define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ |
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| 80 | #define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ |
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| 81 | |
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| 82 | #define AT91_CKGR_PLLAR 0x28 /* PLL A Register */ |
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| 83 | |
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| 84 | #define AT91_PMC_RATIO 0x2c /* Processor clock ratio register [SAMA7G5 only] */ |
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| 85 | #define AT91_PMC_RATIO_RATIO (0xf) /* CPU clock ratio. */ |
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| 86 | |
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| 87 | #define AT91_CKGR_PLLBR 0x2c /* PLL B Register */ |
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| 88 | #define AT91_PMC_DIV (0xff << 0) /* Divider */ |
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| 89 | #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ |
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| 90 | #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ |
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| 91 | #define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ |
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| 92 | #define AT91_PMC_MUL_GET(n) ((n) >> 16 & 0x7ff) |
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| 93 | #define AT91_PMC3_MUL (0x7f << 18) /* PLL Multiplier [SAMA5 only] */ |
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| 94 | #define AT91_PMC3_MUL_GET(n) ((n) >> 18 & 0x7f) |
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| 95 | #define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */ |
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| 96 | #define AT91_PMC_USBDIV_1 (0 << 28) |
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| 97 | #define AT91_PMC_USBDIV_2 (1 << 28) |
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| 98 | #define AT91_PMC_USBDIV_4 (2 << 28) |
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| 99 | #define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ |
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| 100 | |
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| 101 | #define AT91_PMC_CPU_CKR 0x28 /* CPU Clock Register */ |
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| 102 | |
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| 103 | #define AT91_PMC_MCKR 0x30 /* Master Clock Register */ |
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| 104 | #define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ |
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| 105 | #define AT91_PMC_CSS_SLOW (0 << 0) |
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| 106 | #define AT91_PMC_CSS_MAIN (1 << 0) |
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| 107 | #define AT91_PMC_CSS_PLLA (2 << 0) |
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| 108 | #define AT91_PMC_CSS_PLLB (3 << 0) |
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| 109 | #define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */ |
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| 110 | #define PMC_PRES_OFFSET 2 |
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| 111 | #define AT91_PMC_PRES (7 << PMC_PRES_OFFSET) /* Master Clock Prescaler */ |
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| 112 | #define AT91_PMC_PRES_1 (0 << PMC_PRES_OFFSET) |
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| 113 | #define AT91_PMC_PRES_2 (1 << PMC_PRES_OFFSET) |
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| 114 | #define AT91_PMC_PRES_4 (2 << PMC_PRES_OFFSET) |
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| 115 | #define AT91_PMC_PRES_8 (3 << PMC_PRES_OFFSET) |
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| 116 | #define AT91_PMC_PRES_16 (4 << PMC_PRES_OFFSET) |
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| 117 | #define AT91_PMC_PRES_32 (5 << PMC_PRES_OFFSET) |
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| 118 | #define AT91_PMC_PRES_64 (6 << PMC_PRES_OFFSET) |
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| 119 | #define PMC_ALT_PRES_OFFSET 4 |
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| 120 | #define AT91_PMC_ALT_PRES (7 << PMC_ALT_PRES_OFFSET) /* Master Clock Prescaler [alternate location] */ |
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| 121 | #define AT91_PMC_ALT_PRES_1 (0 << PMC_ALT_PRES_OFFSET) |
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| 122 | #define AT91_PMC_ALT_PRES_2 (1 << PMC_ALT_PRES_OFFSET) |
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| 123 | #define AT91_PMC_ALT_PRES_4 (2 << PMC_ALT_PRES_OFFSET) |
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| 124 | #define AT91_PMC_ALT_PRES_8 (3 << PMC_ALT_PRES_OFFSET) |
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| 125 | #define AT91_PMC_ALT_PRES_16 (4 << PMC_ALT_PRES_OFFSET) |
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| 126 | #define AT91_PMC_ALT_PRES_32 (5 << PMC_ALT_PRES_OFFSET) |
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| 127 | #define AT91_PMC_ALT_PRES_64 (6 << PMC_ALT_PRES_OFFSET) |
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| 128 | #define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ |
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| 129 | #define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */ |
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| 130 | #define AT91RM9200_PMC_MDIV_2 (1 << 8) |
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| 131 | #define AT91RM9200_PMC_MDIV_3 (2 << 8) |
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| 132 | #define AT91RM9200_PMC_MDIV_4 (3 << 8) |
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| 133 | #define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9 only] */ |
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| 134 | #define AT91SAM9_PMC_MDIV_2 (1 << 8) |
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| 135 | #define AT91SAM9_PMC_MDIV_4 (2 << 8) |
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| 136 | #define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */ |
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| 137 | #define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */ |
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| 138 | #define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ |
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| 139 | #define AT91_PMC_PDIV_1 (0 << 12) |
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| 140 | #define AT91_PMC_PDIV_2 (1 << 12) |
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| 141 | #define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */ |
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| 142 | #define AT91_PMC_PLLADIV2_OFF (0 << 12) |
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| 143 | #define AT91_PMC_PLLADIV2_ON (1 << 12) |
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| 144 | #define AT91_PMC_H32MXDIV BIT(24) |
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| 145 | |
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| 146 | #define AT91_PMC_MCR_V2 0x30 /* Master Clock Register [SAMA7G5 only] */ |
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| 147 | #define AT91_PMC_MCR_V2_ID_MSK (0xF) |
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| 148 | #define AT91_PMC_MCR_V2_ID(_id) ((_id) & AT91_PMC_MCR_V2_ID_MSK) |
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| 149 | #define AT91_PMC_MCR_V2_CMD (1 << 7) |
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| 150 | #define AT91_PMC_MCR_V2_DIV (7 << 8) |
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| 151 | #define AT91_PMC_MCR_V2_DIV1 (0 << 8) |
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| 152 | #define AT91_PMC_MCR_V2_DIV2 (1 << 8) |
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| 153 | #define AT91_PMC_MCR_V2_DIV4 (2 << 8) |
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| 154 | #define AT91_PMC_MCR_V2_DIV8 (3 << 8) |
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| 155 | #define AT91_PMC_MCR_V2_DIV16 (4 << 8) |
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| 156 | #define AT91_PMC_MCR_V2_DIV32 (5 << 8) |
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| 157 | #define AT91_PMC_MCR_V2_DIV64 (6 << 8) |
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| 158 | #define AT91_PMC_MCR_V2_DIV3 (7 << 8) |
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| 159 | #define AT91_PMC_MCR_V2_CSS (0x1F << 16) |
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| 160 | #define AT91_PMC_MCR_V2_CSS_MD_SLCK (0 << 16) |
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| 161 | #define AT91_PMC_MCR_V2_CSS_TD_SLCK (1 << 16) |
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| 162 | #define AT91_PMC_MCR_V2_CSS_MAINCK (2 << 16) |
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| 163 | #define AT91_PMC_MCR_V2_CSS_MCK0 (3 << 16) |
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| 164 | #define AT91_PMC_MCR_V2_CSS_SYSPLL (5 << 16) |
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| 165 | #define AT91_PMC_MCR_V2_CSS_DDRPLL (6 << 16) |
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| 166 | #define AT91_PMC_MCR_V2_CSS_IMGPLL (7 << 16) |
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| 167 | #define AT91_PMC_MCR_V2_CSS_BAUDPLL (8 << 16) |
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| 168 | #define AT91_PMC_MCR_V2_CSS_AUDIOPLL (9 << 16) |
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| 169 | #define AT91_PMC_MCR_V2_CSS_ETHPLL (10 << 16) |
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| 170 | #define AT91_PMC_MCR_V2_EN (1 << 28) |
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| 171 | |
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| 172 | #define AT91_PMC_XTALF 0x34 /* Main XTAL Frequency Register [SAMA7G5 only] */ |
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| 173 | |
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| 174 | #define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */ |
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| 175 | #define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */ |
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| 176 | #define AT91_PMC_USBS_PLLA (0 << 0) |
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| 177 | #define AT91_PMC_USBS_UPLL (1 << 0) |
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| 178 | #define AT91_PMC_USBS_PLLB (1 << 0) /* [AT91SAMN12 only] */ |
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| 179 | #define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */ |
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| 180 | #define AT91_PMC_OHCIUSBDIV_1 (0x0 << 8) |
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| 181 | #define AT91_PMC_OHCIUSBDIV_2 (0x1 << 8) |
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| 182 | |
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| 183 | #define AT91_PMC_SMD 0x3c /* Soft Modem Clock Register [some SAM9 only] */ |
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| 184 | #define AT91_PMC_SMDS (0x1 << 0) /* SMD input clock selection */ |
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| 185 | #define AT91_PMC_SMD_DIV (0x1f << 8) /* SMD input clock divider */ |
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| 186 | #define AT91_PMC_SMDDIV(n) (((n) << 8) & AT91_PMC_SMD_DIV) |
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| 187 | |
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| 188 | #define AT91_PMC_PCKR(n) (0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */ |
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| 189 | #define AT91_PMC_ALT_PCKR_CSS (0x7 << 0) /* Programmable Clock Source Selection [alternate length] */ |
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| 190 | #define AT91_PMC_CSS_MASTER (4 << 0) /* [some SAM9 only] */ |
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| 191 | #define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */ |
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| 192 | #define AT91_PMC_CSSMCK_CSS (0 << 8) |
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| 193 | #define AT91_PMC_CSSMCK_MCK (1 << 8) |
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| 194 | |
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| 195 | #define AT91_PMC_IER 0x60 /* Interrupt Enable Register */ |
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| 196 | #define AT91_PMC_IDR 0x64 /* Interrupt Disable Register */ |
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| 197 | #define AT91_PMC_SR 0x68 /* Status Register */ |
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| 198 | #define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ |
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| 199 | #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ |
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| 200 | #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ |
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| 201 | #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ |
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| 202 | #define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9] */ |
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| 203 | #define AT91_PMC_OSCSEL (1 << 7) /* Slow Oscillator Selection [some SAM9] */ |
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| 204 | #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ |
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| 205 | #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ |
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| 206 | #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ |
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| 207 | #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ |
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| 208 | #define AT91_PMC_MOSCSELS (1 << 16) /* Main Oscillator Selection [some SAM9] */ |
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| 209 | #define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */ |
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| 210 | #define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */ |
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| 211 | #define AT91_PMC_GCKRDY (1 << 24) /* Generated Clocks */ |
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| 212 | #define AT91_PMC_MCKXRDY (1 << 26) /* Master Clock x [x=1..4] Ready Status */ |
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| 213 | #define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */ |
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| 214 | |
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| 215 | #define AT91_PMC_FSMR 0x70 /* Fast Startup Mode Register */ |
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| 216 | #define AT91_PMC_FSTT(n) BIT(n) |
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| 217 | #define AT91_PMC_RTTAL BIT(16) |
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| 218 | #define AT91_PMC_RTCAL BIT(17) /* RTC Alarm Enable */ |
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| 219 | #define AT91_PMC_USBAL BIT(18) /* USB Resume Enable */ |
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| 220 | #define AT91_PMC_SDMMC_CD BIT(19) /* SDMMC Card Detect Enable */ |
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| 221 | #define AT91_PMC_LPM BIT(20) /* Low-power Mode */ |
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| 222 | #define AT91_PMC_RXLP_MCE BIT(24) /* Backup UART Receive Enable */ |
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| 223 | #define AT91_PMC_ACC_CE BIT(25) /* ACC Enable */ |
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| 224 | |
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| 225 | #define AT91_PMC_FSPR 0x74 /* Fast Startup Polarity Reg */ |
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| 226 | |
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| 227 | #define AT91_PMC_FS_INPUT_MASK 0x7ff |
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| 228 | |
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| 229 | #define AT91_PMC_PLLICPR 0x80 /* PLL Charge Pump Current Register */ |
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| 230 | |
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| 231 | #define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */ |
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| 232 | #define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */ |
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| 233 | #define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */ |
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| 234 | #define AT91_PMC_PROTKEY (0x504d43 << 8) /* Activation Code */ |
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| 235 | |
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| 236 | #define AT91_PMC_WPSR 0xe8 /* Write Protect Status Register [some SAM9] */ |
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| 237 | #define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */ |
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| 238 | #define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */ |
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| 239 | |
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| 240 | #define AT91_PMC_PLL_ISR0 0xEC /* PLL Interrupt Status Register 0 [SAM9X60 only] */ |
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| 241 | |
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| 242 | #define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 [SAMA5 only]*/ |
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| 243 | #define AT91_PMC_PCDR1 0x104 /* Peripheral Clock Enable Register 1 */ |
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| 244 | #define AT91_PMC_PCSR1 0x108 /* Peripheral Clock Enable Register 1 */ |
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| 245 | |
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| 246 | #define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9 and SAMA5] */ |
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| 247 | #define AT91_PMC_PCR_PID_MASK 0x3f |
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| 248 | #define AT91_PMC_PCR_CMD (0x1 << 12) /* Command (read=0, write=1) */ |
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| 249 | #define AT91_PMC_PCR_GCKDIV_MASK GENMASK(27, 20) |
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| 250 | #define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */ |
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| 251 | #define AT91_PMC_PCR_GCKEN (0x1 << 29) /* GCK Enable */ |
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| 252 | |
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| 253 | #define AT91_PMC_AUDIO_PLL0 0x14c |
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| 254 | #define AT91_PMC_AUDIO_PLL_PLLEN (1 << 0) |
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| 255 | #define AT91_PMC_AUDIO_PLL_PADEN (1 << 1) |
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| 256 | #define AT91_PMC_AUDIO_PLL_PMCEN (1 << 2) |
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| 257 | #define AT91_PMC_AUDIO_PLL_RESETN (1 << 3) |
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| 258 | #define AT91_PMC_AUDIO_PLL_ND_OFFSET 8 |
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| 259 | #define AT91_PMC_AUDIO_PLL_ND_MASK (0x7f << AT91_PMC_AUDIO_PLL_ND_OFFSET) |
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| 260 | #define AT91_PMC_AUDIO_PLL_ND(n) ((n) << AT91_PMC_AUDIO_PLL_ND_OFFSET) |
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| 261 | #define AT91_PMC_AUDIO_PLL_QDPMC_OFFSET 16 |
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| 262 | #define AT91_PMC_AUDIO_PLL_QDPMC_MASK (0x7f << AT91_PMC_AUDIO_PLL_QDPMC_OFFSET) |
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| 263 | #define AT91_PMC_AUDIO_PLL_QDPMC(n) ((n) << AT91_PMC_AUDIO_PLL_QDPMC_OFFSET) |
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| 264 | |
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| 265 | #define AT91_PMC_AUDIO_PLL1 0x150 |
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| 266 | #define AT91_PMC_AUDIO_PLL_FRACR_MASK 0x3fffff |
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| 267 | #define AT91_PMC_AUDIO_PLL_QDPAD_OFFSET 24 |
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| 268 | #define AT91_PMC_AUDIO_PLL_QDPAD_MASK (0x7f << AT91_PMC_AUDIO_PLL_QDPAD_OFFSET) |
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| 269 | #define AT91_PMC_AUDIO_PLL_QDPAD(n) ((n) << AT91_PMC_AUDIO_PLL_QDPAD_OFFSET) |
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| 270 | #define AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET AT91_PMC_AUDIO_PLL_QDPAD_OFFSET |
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| 271 | #define AT91_PMC_AUDIO_PLL_QDPAD_DIV_MASK (0x3 << AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET) |
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| 272 | #define AT91_PMC_AUDIO_PLL_QDPAD_DIV(n) ((n) << AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET) |
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| 273 | #define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET 26 |
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| 274 | #define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX 0x1f |
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| 275 | #define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MASK (AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX << AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET) |
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| 276 | #define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV(n) ((n) << AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET) |
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| 277 | |
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| 278 | #endif |
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| 279 | |
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