1/* SPDX-License-Identifier: GPL-2.0 */
2/* $Revision: 3.0 $$Date: 1998/11/02 14:20:59 $
3 * linux/include/linux/cyclades.h
4 *
5 * This file was initially written by
6 * Randolph Bentson <bentson@grieg.seaslug.org> and is maintained by
7 * Ivan Passos <ivan@cyclades.com>.
8 *
9 * This file contains the general definitions for the cyclades.c driver
10 *$Log: cyclades.h,v $
11 *Revision 3.1 2002/01/29 11:36:16 henrique
12 *added throttle field on struct cyclades_port to indicate whether the
13 *port is throttled or not
14 *
15 *Revision 3.1 2000/04/19 18:52:52 ivan
16 *converted address fields to unsigned long and added fields for physical
17 *addresses on cyclades_card structure;
18 *
19 *Revision 3.0 1998/11/02 14:20:59 ivan
20 *added nports field on cyclades_card structure;
21 *
22 *Revision 2.5 1998/08/03 16:57:01 ivan
23 *added cyclades_idle_stats structure;
24 *
25 *Revision 2.4 1998/06/01 12:09:53 ivan
26 *removed closing_wait2 from cyclades_port structure;
27 *
28 *Revision 2.3 1998/03/16 18:01:12 ivan
29 *changes in the cyclades_port structure to get it closer to the
30 *standard serial port structure;
31 *added constants for new ioctls;
32 *
33 *Revision 2.2 1998/02/17 16:50:00 ivan
34 *changes in the cyclades_port structure (addition of shutdown_wait and
35 *chip_rev variables);
36 *added constants for new ioctls and for CD1400 rev. numbers.
37 *
38 *Revision 2.1 1997/10/24 16:03:00 ivan
39 *added rflow (which allows enabling the CD1400 special flow control
40 *feature) and rtsdtr_inv (which allows DTR/RTS pin inversion) to
41 *cyclades_port structure;
42 *added Alpha support
43 *
44 *Revision 2.0 1997/06/30 10:30:00 ivan
45 *added some new doorbell command constants related to IOCTLW and
46 *UART error signaling
47 *
48 *Revision 1.8 1997/06/03 15:30:00 ivan
49 *added constant ZFIRM_HLT
50 *added constant CyPCI_Ze_win ( = 2 * Cy_PCI_Zwin)
51 *
52 *Revision 1.7 1997/03/26 10:30:00 daniel
53 *new entries at the end of cyclades_port struct to reallocate
54 *variables illegally allocated within card memory.
55 *
56 *Revision 1.6 1996/09/09 18:35:30 bentson
57 *fold in changes for Cyclom-Z -- including structures for
58 *communicating with board as well modest changes to original
59 *structures to support new features.
60 *
61 *Revision 1.5 1995/11/13 21:13:31 bentson
62 *changes suggested by Michael Chastain <mec@duracef.shout.net>
63 *to support use of this file in non-kernel applications
64 *
65 *
66 */
67#ifndef _LINUX_CYCLADES_H
68#define _LINUX_CYCLADES_H
69
70#include <uapi/linux/cyclades.h>
71
72
73/* Per card data structure */
74struct cyclades_card {
75 void __iomem *base_addr;
76 union {
77 void __iomem *p9050;
78 struct RUNTIME_9060 __iomem *p9060;
79 } ctl_addr;
80 struct BOARD_CTRL __iomem *board_ctrl; /* cyz specific */
81 int irq;
82 unsigned int num_chips; /* 0 if card absent, -1 if Z/PCI, else Y */
83 unsigned int first_line; /* minor number of first channel on card */
84 unsigned int nports; /* Number of ports in the card */
85 int bus_index; /* address shift - 0 for ISA, 1 for PCI */
86 int intr_enabled; /* FW Interrupt flag - 0 disabled, 1 enabled */
87 u32 hw_ver;
88 spinlock_t card_lock;
89 struct cyclades_port *ports;
90};
91
92/***************************************
93 * Memory access functions/macros *
94 * (required to support Alpha systems) *
95 ***************************************/
96
97#define cy_writeb(port,val) do { writeb((val), (port)); mb(); } while (0)
98#define cy_writew(port,val) do { writew((val), (port)); mb(); } while (0)
99#define cy_writel(port,val) do { writel((val), (port)); mb(); } while (0)
100
101/*
102 * Statistics counters
103 */
104struct cyclades_icount {
105 __u32 cts, dsr, rng, dcd, tx, rx;
106 __u32 frame, parity, overrun, brk;
107 __u32 buf_overrun;
108};
109
110/*
111 * This is our internal structure for each serial port's state.
112 *
113 * Many fields are paralleled by the structure used by the serial_struct
114 * structure.
115 *
116 * For definitions of the flags field, see tty.h
117 */
118
119struct cyclades_port {
120 int magic;
121 struct tty_port port;
122 struct cyclades_card *card;
123 union {
124 struct {
125 void __iomem *base_addr;
126 } cyy;
127 struct {
128 struct CH_CTRL __iomem *ch_ctrl;
129 struct BUF_CTRL __iomem *buf_ctrl;
130 } cyz;
131 } u;
132 int line;
133 int flags; /* defined in tty.h */
134 int type; /* UART type */
135 int read_status_mask;
136 int ignore_status_mask;
137 int timeout;
138 int xmit_fifo_size;
139 int cor1,cor2,cor3,cor4,cor5;
140 int tbpr,tco,rbpr,rco;
141 int baud;
142 int rflow;
143 int rtsdtr_inv;
144 int chip_rev;
145 int custom_divisor;
146 u8 x_char; /* to be pushed out ASAP */
147 int breakon;
148 int breakoff;
149 int xmit_head;
150 int xmit_tail;
151 int xmit_cnt;
152 int default_threshold;
153 int default_timeout;
154 unsigned long rflush_count;
155 struct cyclades_monitor mon;
156 struct cyclades_idle_stats idle_stats;
157 struct cyclades_icount icount;
158 struct completion shutdown_wait;
159 int throttle;
160#ifdef CONFIG_CYZ_INTR
161 struct timer_list rx_full_timer;
162#endif
163};
164
165#define CLOSING_WAIT_DELAY 30*HZ
166#define CY_CLOSING_WAIT_NONE ASYNC_CLOSING_WAIT_NONE
167#define CY_CLOSING_WAIT_INF ASYNC_CLOSING_WAIT_INF
168
169
170#define CyMAX_CHIPS_PER_CARD 8
171#define CyMAX_CHAR_FIFO 12
172#define CyPORTS_PER_CHIP 4
173#define CD1400_MAX_SPEED 115200
174
175#define CyISA_Ywin 0x2000
176
177#define CyPCI_Ywin 0x4000
178#define CyPCI_Yctl 0x80
179#define CyPCI_Zctl CTRL_WINDOW_SIZE
180#define CyPCI_Zwin 0x80000
181#define CyPCI_Ze_win (2 * CyPCI_Zwin)
182
183#define PCI_DEVICE_ID_MASK 0x06
184
185/**** CD1400 registers ****/
186
187#define CD1400_REV_G 0x46
188#define CD1400_REV_J 0x48
189
190#define CyRegSize 0x0400
191#define Cy_HwReset 0x1400
192#define Cy_ClrIntr 0x1800
193#define Cy_EpldRev 0x1e00
194
195/* Global Registers */
196
197#define CyGFRCR (0x40*2)
198#define CyRevE (44)
199#define CyCAR (0x68*2)
200#define CyCHAN_0 (0x00)
201#define CyCHAN_1 (0x01)
202#define CyCHAN_2 (0x02)
203#define CyCHAN_3 (0x03)
204#define CyGCR (0x4B*2)
205#define CyCH0_SERIAL (0x00)
206#define CyCH0_PARALLEL (0x80)
207#define CySVRR (0x67*2)
208#define CySRModem (0x04)
209#define CySRTransmit (0x02)
210#define CySRReceive (0x01)
211#define CyRICR (0x44*2)
212#define CyTICR (0x45*2)
213#define CyMICR (0x46*2)
214#define CyICR0 (0x00)
215#define CyICR1 (0x01)
216#define CyICR2 (0x02)
217#define CyICR3 (0x03)
218#define CyRIR (0x6B*2)
219#define CyTIR (0x6A*2)
220#define CyMIR (0x69*2)
221#define CyIRDirEq (0x80)
222#define CyIRBusy (0x40)
223#define CyIRUnfair (0x20)
224#define CyIRContext (0x1C)
225#define CyIRChannel (0x03)
226#define CyPPR (0x7E*2)
227#define CyCLOCK_20_1MS (0x27)
228#define CyCLOCK_25_1MS (0x31)
229#define CyCLOCK_25_5MS (0xf4)
230#define CyCLOCK_60_1MS (0x75)
231#define CyCLOCK_60_2MS (0xea)
232
233/* Virtual Registers */
234
235#define CyRIVR (0x43*2)
236#define CyTIVR (0x42*2)
237#define CyMIVR (0x41*2)
238#define CyIVRMask (0x07)
239#define CyIVRRxEx (0x07)
240#define CyIVRRxOK (0x03)
241#define CyIVRTxOK (0x02)
242#define CyIVRMdmOK (0x01)
243#define CyTDR (0x63*2)
244#define CyRDSR (0x62*2)
245#define CyTIMEOUT (0x80)
246#define CySPECHAR (0x70)
247#define CyBREAK (0x08)
248#define CyPARITY (0x04)
249#define CyFRAME (0x02)
250#define CyOVERRUN (0x01)
251#define CyMISR (0x4C*2)
252/* see CyMCOR_ and CyMSVR_ for bits*/
253#define CyEOSRR (0x60*2)
254
255/* Channel Registers */
256
257#define CyLIVR (0x18*2)
258#define CyMscsr (0x01)
259#define CyTdsr (0x02)
260#define CyRgdsr (0x03)
261#define CyRedsr (0x07)
262#define CyCCR (0x05*2)
263/* Format 1 */
264#define CyCHAN_RESET (0x80)
265#define CyCHIP_RESET (0x81)
266#define CyFlushTransFIFO (0x82)
267/* Format 2 */
268#define CyCOR_CHANGE (0x40)
269#define CyCOR1ch (0x02)
270#define CyCOR2ch (0x04)
271#define CyCOR3ch (0x08)
272/* Format 3 */
273#define CySEND_SPEC_1 (0x21)
274#define CySEND_SPEC_2 (0x22)
275#define CySEND_SPEC_3 (0x23)
276#define CySEND_SPEC_4 (0x24)
277/* Format 4 */
278#define CyCHAN_CTL (0x10)
279#define CyDIS_RCVR (0x01)
280#define CyENB_RCVR (0x02)
281#define CyDIS_XMTR (0x04)
282#define CyENB_XMTR (0x08)
283#define CySRER (0x06*2)
284#define CyMdmCh (0x80)
285#define CyRxData (0x10)
286#define CyTxRdy (0x04)
287#define CyTxMpty (0x02)
288#define CyNNDT (0x01)
289#define CyCOR1 (0x08*2)
290#define CyPARITY_NONE (0x00)
291#define CyPARITY_0 (0x20)
292#define CyPARITY_1 (0xA0)
293#define CyPARITY_E (0x40)
294#define CyPARITY_O (0xC0)
295#define Cy_1_STOP (0x00)
296#define Cy_1_5_STOP (0x04)
297#define Cy_2_STOP (0x08)
298#define Cy_5_BITS (0x00)
299#define Cy_6_BITS (0x01)
300#define Cy_7_BITS (0x02)
301#define Cy_8_BITS (0x03)
302#define CyCOR2 (0x09*2)
303#define CyIXM (0x80)
304#define CyTxIBE (0x40)
305#define CyETC (0x20)
306#define CyAUTO_TXFL (0x60)
307#define CyLLM (0x10)
308#define CyRLM (0x08)
309#define CyRtsAO (0x04)
310#define CyCtsAE (0x02)
311#define CyDsrAE (0x01)
312#define CyCOR3 (0x0A*2)
313#define CySPL_CH_DRANGE (0x80) /* special character detect range */
314#define CySPL_CH_DET1 (0x40) /* enable special character detection
315 on SCHR4-SCHR3 */
316#define CyFL_CTRL_TRNSP (0x20) /* Flow Control Transparency */
317#define CySPL_CH_DET2 (0x10) /* Enable special character detection
318 on SCHR2-SCHR1 */
319#define CyREC_FIFO (0x0F) /* Receive FIFO threshold */
320#define CyCOR4 (0x1E*2)
321#define CyCOR5 (0x1F*2)
322#define CyCCSR (0x0B*2)
323#define CyRxEN (0x80)
324#define CyRxFloff (0x40)
325#define CyRxFlon (0x20)
326#define CyTxEN (0x08)
327#define CyTxFloff (0x04)
328#define CyTxFlon (0x02)
329#define CyRDCR (0x0E*2)
330#define CySCHR1 (0x1A*2)
331#define CySCHR2 (0x1B*2)
332#define CySCHR3 (0x1C*2)
333#define CySCHR4 (0x1D*2)
334#define CySCRL (0x22*2)
335#define CySCRH (0x23*2)
336#define CyLNC (0x24*2)
337#define CyMCOR1 (0x15*2)
338#define CyMCOR2 (0x16*2)
339#define CyRTPR (0x21*2)
340#define CyMSVR1 (0x6C*2)
341#define CyMSVR2 (0x6D*2)
342#define CyANY_DELTA (0xF0)
343#define CyDSR (0x80)
344#define CyCTS (0x40)
345#define CyRI (0x20)
346#define CyDCD (0x10)
347#define CyDTR (0x02)
348#define CyRTS (0x01)
349#define CyPVSR (0x6F*2)
350#define CyRBPR (0x78*2)
351#define CyRCOR (0x7C*2)
352#define CyTBPR (0x72*2)
353#define CyTCOR (0x76*2)
354
355/* Custom Registers */
356
357#define CyPLX_VER (0x3400)
358#define PLX_9050 0x0b
359#define PLX_9060 0x0c
360#define PLX_9080 0x0d
361
362/***************************************************************************/
363
364#endif /* _LINUX_CYCLADES_H */
365