1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
4 */
5#ifndef LINUX_DMAENGINE_H
6#define LINUX_DMAENGINE_H
7
8#include <linux/device.h>
9#include <linux/err.h>
10#include <linux/uio.h>
11#include <linux/bug.h>
12#include <linux/scatterlist.h>
13#include <linux/bitmap.h>
14#include <linux/types.h>
15#include <asm/page.h>
16
17/**
18 * typedef dma_cookie_t - an opaque DMA cookie
19 *
20 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
21 */
22typedef s32 dma_cookie_t;
23#define DMA_MIN_COOKIE 1
24
25static inline int dma_submit_error(dma_cookie_t cookie)
26{
27 return cookie < 0 ? cookie : 0;
28}
29
30/**
31 * enum dma_status - DMA transaction status
32 * @DMA_COMPLETE: transaction completed
33 * @DMA_IN_PROGRESS: transaction not yet processed
34 * @DMA_PAUSED: transaction is paused
35 * @DMA_ERROR: transaction failed
36 */
37enum dma_status {
38 DMA_COMPLETE,
39 DMA_IN_PROGRESS,
40 DMA_PAUSED,
41 DMA_ERROR,
42 DMA_OUT_OF_ORDER,
43};
44
45/**
46 * enum dma_transaction_type - DMA transaction types/indexes
47 *
48 * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is
49 * automatically set as dma devices are registered.
50 */
51enum dma_transaction_type {
52 DMA_MEMCPY,
53 DMA_XOR,
54 DMA_PQ,
55 DMA_XOR_VAL,
56 DMA_PQ_VAL,
57 DMA_MEMSET,
58 DMA_MEMSET_SG,
59 DMA_INTERRUPT,
60 DMA_PRIVATE,
61 DMA_ASYNC_TX,
62 DMA_SLAVE,
63 DMA_CYCLIC,
64 DMA_INTERLEAVE,
65 DMA_COMPLETION_NO_ORDER,
66 DMA_REPEAT,
67 DMA_LOAD_EOT,
68/* last transaction type for creation of the capabilities mask */
69 DMA_TX_TYPE_END,
70};
71
72/**
73 * enum dma_transfer_direction - dma transfer mode and direction indicator
74 * @DMA_MEM_TO_MEM: Async/Memcpy mode
75 * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
76 * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
77 * @DMA_DEV_TO_DEV: Slave mode & From Device to Device
78 */
79enum dma_transfer_direction {
80 DMA_MEM_TO_MEM,
81 DMA_MEM_TO_DEV,
82 DMA_DEV_TO_MEM,
83 DMA_DEV_TO_DEV,
84 DMA_TRANS_NONE,
85};
86
87/**
88 * Interleaved Transfer Request
89 * ----------------------------
90 * A chunk is collection of contiguous bytes to be transferred.
91 * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
92 * ICGs may or may not change between chunks.
93 * A FRAME is the smallest series of contiguous {chunk,icg} pairs,
94 * that when repeated an integral number of times, specifies the transfer.
95 * A transfer template is specification of a Frame, the number of times
96 * it is to be repeated and other per-transfer attributes.
97 *
98 * Practically, a client driver would have ready a template for each
99 * type of transfer it is going to need during its lifetime and
100 * set only 'src_start' and 'dst_start' before submitting the requests.
101 *
102 *
103 * | Frame-1 | Frame-2 | ~ | Frame-'numf' |
104 * |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...|
105 *
106 * == Chunk size
107 * ... ICG
108 */
109
110/**
111 * struct data_chunk - Element of scatter-gather list that makes a frame.
112 * @size: Number of bytes to read from source.
113 * size_dst := fn(op, size_src), so doesn't mean much for destination.
114 * @icg: Number of bytes to jump after last src/dst address of this
115 * chunk and before first src/dst address for next chunk.
116 * Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false.
117 * Ignored for src(assumed 0), if src_inc is true and src_sgl is false.
118 * @dst_icg: Number of bytes to jump after last dst address of this
119 * chunk and before the first dst address for next chunk.
120 * Ignored if dst_inc is true and dst_sgl is false.
121 * @src_icg: Number of bytes to jump after last src address of this
122 * chunk and before the first src address for next chunk.
123 * Ignored if src_inc is true and src_sgl is false.
124 */
125struct data_chunk {
126 size_t size;
127 size_t icg;
128 size_t dst_icg;
129 size_t src_icg;
130};
131
132/**
133 * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
134 * and attributes.
135 * @src_start: Bus address of source for the first chunk.
136 * @dst_start: Bus address of destination for the first chunk.
137 * @dir: Specifies the type of Source and Destination.
138 * @src_inc: If the source address increments after reading from it.
139 * @dst_inc: If the destination address increments after writing to it.
140 * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read).
141 * Otherwise, source is read contiguously (icg ignored).
142 * Ignored if src_inc is false.
143 * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write).
144 * Otherwise, destination is filled contiguously (icg ignored).
145 * Ignored if dst_inc is false.
146 * @numf: Number of frames in this template.
147 * @frame_size: Number of chunks in a frame i.e, size of sgl[].
148 * @sgl: Array of {chunk,icg} pairs that make up a frame.
149 */
150struct dma_interleaved_template {
151 dma_addr_t src_start;
152 dma_addr_t dst_start;
153 enum dma_transfer_direction dir;
154 bool src_inc;
155 bool dst_inc;
156 bool src_sgl;
157 bool dst_sgl;
158 size_t numf;
159 size_t frame_size;
160 struct data_chunk sgl[];
161};
162
163/**
164 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
165 * control completion, and communicate status.
166 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
167 * this transaction
168 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
169 * acknowledges receipt, i.e. has a chance to establish any dependency
170 * chains
171 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
172 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
173 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
174 * sources that were the result of a previous operation, in the case of a PQ
175 * operation it continues the calculation with new sources
176 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
177 * on the result of this operation
178 * @DMA_CTRL_REUSE: client can reuse the descriptor and submit again till
179 * cleared or freed
180 * @DMA_PREP_CMD: tell the driver that the data passed to DMA API is command
181 * data and the descriptor should be in different format from normal
182 * data descriptors.
183 * @DMA_PREP_REPEAT: tell the driver that the transaction shall be automatically
184 * repeated when it ends until a transaction is issued on the same channel
185 * with the DMA_PREP_LOAD_EOT flag set. This flag is only applicable to
186 * interleaved transactions and is ignored for all other transaction types.
187 * @DMA_PREP_LOAD_EOT: tell the driver that the transaction shall replace any
188 * active repeated (as indicated by DMA_PREP_REPEAT) transaction when the
189 * repeated transaction ends. Not setting this flag when the previously queued
190 * transaction is marked with DMA_PREP_REPEAT will cause the new transaction
191 * to never be processed and stay in the issued queue forever. The flag is
192 * ignored if the previous transaction is not a repeated transaction.
193 */
194enum dma_ctrl_flags {
195 DMA_PREP_INTERRUPT = (1 << 0),
196 DMA_CTRL_ACK = (1 << 1),
197 DMA_PREP_PQ_DISABLE_P = (1 << 2),
198 DMA_PREP_PQ_DISABLE_Q = (1 << 3),
199 DMA_PREP_CONTINUE = (1 << 4),
200 DMA_PREP_FENCE = (1 << 5),
201 DMA_CTRL_REUSE = (1 << 6),
202 DMA_PREP_CMD = (1 << 7),
203 DMA_PREP_REPEAT = (1 << 8),
204 DMA_PREP_LOAD_EOT = (1 << 9),
205};
206
207/**
208 * enum sum_check_bits - bit position of pq_check_flags
209 */
210enum sum_check_bits {
211 SUM_CHECK_P = 0,
212 SUM_CHECK_Q = 1,
213};
214
215/**
216 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
217 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
218 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
219 */
220enum sum_check_flags {
221 SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P),
222 SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q),
223};
224
225
226/**
227 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
228 * See linux/cpumask.h
229 */
230typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
231
232/**
233 * enum dma_desc_metadata_mode - per descriptor metadata mode types supported
234 * @DESC_METADATA_CLIENT - the metadata buffer is allocated/provided by the
235 * client driver and it is attached (via the dmaengine_desc_attach_metadata()
236 * helper) to the descriptor.
237 *
238 * Client drivers interested to use this mode can follow:
239 * - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:
240 * 1. prepare the descriptor (dmaengine_prep_*)
241 * construct the metadata in the client's buffer
242 * 2. use dmaengine_desc_attach_metadata() to attach the buffer to the
243 * descriptor
244 * 3. submit the transfer
245 * - DMA_DEV_TO_MEM:
246 * 1. prepare the descriptor (dmaengine_prep_*)
247 * 2. use dmaengine_desc_attach_metadata() to attach the buffer to the
248 * descriptor
249 * 3. submit the transfer
250 * 4. when the transfer is completed, the metadata should be available in the
251 * attached buffer
252 *
253 * @DESC_METADATA_ENGINE - the metadata buffer is allocated/managed by the DMA
254 * driver. The client driver can ask for the pointer, maximum size and the
255 * currently used size of the metadata and can directly update or read it.
256 * dmaengine_desc_get_metadata_ptr() and dmaengine_desc_set_metadata_len() is
257 * provided as helper functions.
258 *
259 * Note: the metadata area for the descriptor is no longer valid after the
260 * transfer has been completed (valid up to the point when the completion
261 * callback returns if used).
262 *
263 * Client drivers interested to use this mode can follow:
264 * - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:
265 * 1. prepare the descriptor (dmaengine_prep_*)
266 * 2. use dmaengine_desc_get_metadata_ptr() to get the pointer to the engine's
267 * metadata area
268 * 3. update the metadata at the pointer
269 * 4. use dmaengine_desc_set_metadata_len() to tell the DMA engine the amount
270 * of data the client has placed into the metadata buffer
271 * 5. submit the transfer
272 * - DMA_DEV_TO_MEM:
273 * 1. prepare the descriptor (dmaengine_prep_*)
274 * 2. submit the transfer
275 * 3. on transfer completion, use dmaengine_desc_get_metadata_ptr() to get the
276 * pointer to the engine's metadata area
277 * 4. Read out the metadata from the pointer
278 *
279 * Note: the two mode is not compatible and clients must use one mode for a
280 * descriptor.
281 */
282enum dma_desc_metadata_mode {
283 DESC_METADATA_NONE = 0,
284 DESC_METADATA_CLIENT = BIT(0),
285 DESC_METADATA_ENGINE = BIT(1),
286};
287
288/**
289 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
290 * @memcpy_count: transaction counter
291 * @bytes_transferred: byte counter
292 */
293struct dma_chan_percpu {
294 /* stats */
295 unsigned long memcpy_count;
296 unsigned long bytes_transferred;
297};
298
299/**
300 * struct dma_router - DMA router structure
301 * @dev: pointer to the DMA router device
302 * @route_free: function to be called when the route can be disconnected
303 */
304struct dma_router {
305 struct device *dev;
306 void (*route_free)(struct device *dev, void *route_data);
307};
308
309/**
310 * struct dma_chan - devices supply DMA channels, clients use them
311 * @device: ptr to the dma device who supplies this channel, always !%NULL
312 * @slave: ptr to the device using this channel
313 * @cookie: last cookie value returned to client
314 * @completed_cookie: last completed cookie for this channel
315 * @chan_id: channel ID for sysfs
316 * @dev: class device for sysfs
317 * @name: backlink name for sysfs
318 * @dbg_client_name: slave name for debugfs in format:
319 * dev_name(requester's dev):channel name, for example: "2b00000.mcasp:tx"
320 * @device_node: used to add this to the device chan list
321 * @local: per-cpu pointer to a struct dma_chan_percpu
322 * @client_count: how many clients are using this channel
323 * @table_count: number of appearances in the mem-to-mem allocation table
324 * @router: pointer to the DMA router structure
325 * @route_data: channel specific data for the router
326 * @private: private data for certain client-channel associations
327 */
328struct dma_chan {
329 struct dma_device *device;
330 struct device *slave;
331 dma_cookie_t cookie;
332 dma_cookie_t completed_cookie;
333
334 /* sysfs */
335 int chan_id;
336 struct dma_chan_dev *dev;
337 const char *name;
338#ifdef CONFIG_DEBUG_FS
339 char *dbg_client_name;
340#endif
341
342 struct list_head device_node;
343 struct dma_chan_percpu __percpu *local;
344 int client_count;
345 int table_count;
346
347 /* DMA router */
348 struct dma_router *router;
349 void *route_data;
350
351 void *private;
352};
353
354/**
355 * struct dma_chan_dev - relate sysfs device node to backing channel device
356 * @chan: driver channel device
357 * @device: sysfs device
358 * @dev_id: parent dma_device dev_id
359 * @chan_dma_dev: The channel is using custom/different dma-mapping
360 * compared to the parent dma_device
361 */
362struct dma_chan_dev {
363 struct dma_chan *chan;
364 struct device device;
365 int dev_id;
366 bool chan_dma_dev;
367};
368
369/**
370 * enum dma_slave_buswidth - defines bus width of the DMA slave
371 * device, source or target buses
372 */
373enum dma_slave_buswidth {
374 DMA_SLAVE_BUSWIDTH_UNDEFINED = 0,
375 DMA_SLAVE_BUSWIDTH_1_BYTE = 1,
376 DMA_SLAVE_BUSWIDTH_2_BYTES = 2,
377 DMA_SLAVE_BUSWIDTH_3_BYTES = 3,
378 DMA_SLAVE_BUSWIDTH_4_BYTES = 4,
379 DMA_SLAVE_BUSWIDTH_8_BYTES = 8,
380 DMA_SLAVE_BUSWIDTH_16_BYTES = 16,
381 DMA_SLAVE_BUSWIDTH_32_BYTES = 32,
382 DMA_SLAVE_BUSWIDTH_64_BYTES = 64,
383 DMA_SLAVE_BUSWIDTH_128_BYTES = 128,
384};
385
386/**
387 * struct dma_slave_config - dma slave channel runtime config
388 * @direction: whether the data shall go in or out on this slave
389 * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are
390 * legal values. DEPRECATED, drivers should use the direction argument
391 * to the device_prep_slave_sg and device_prep_dma_cyclic functions or
392 * the dir field in the dma_interleaved_template structure.
393 * @src_addr: this is the physical address where DMA slave data
394 * should be read (RX), if the source is memory this argument is
395 * ignored.
396 * @dst_addr: this is the physical address where DMA slave data
397 * should be written (TX), if the destination is memory this argument
398 * is ignored.
399 * @src_addr_width: this is the width in bytes of the source (RX)
400 * register where DMA data shall be read. If the source
401 * is memory this may be ignored depending on architecture.
402 * Legal values: 1, 2, 3, 4, 8, 16, 32, 64, 128.
403 * @dst_addr_width: same as src_addr_width but for destination
404 * target (TX) mutatis mutandis.
405 * @src_maxburst: the maximum number of words (note: words, as in
406 * units of the src_addr_width member, not bytes) that can be sent
407 * in one burst to the device. Typically something like half the
408 * FIFO depth on I/O peripherals so you don't overflow it. This
409 * may or may not be applicable on memory sources.
410 * @dst_maxburst: same as src_maxburst but for destination target
411 * mutatis mutandis.
412 * @src_port_window_size: The length of the register area in words the data need
413 * to be accessed on the device side. It is only used for devices which is using
414 * an area instead of a single register to receive the data. Typically the DMA
415 * loops in this area in order to transfer the data.
416 * @dst_port_window_size: same as src_port_window_size but for the destination
417 * port.
418 * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill
419 * with 'true' if peripheral should be flow controller. Direction will be
420 * selected at Runtime.
421 * @peripheral_config: peripheral configuration for programming peripheral
422 * for dmaengine transfer
423 * @peripheral_size: peripheral configuration buffer size
424 *
425 * This struct is passed in as configuration data to a DMA engine
426 * in order to set up a certain channel for DMA transport at runtime.
427 * The DMA device/engine has to provide support for an additional
428 * callback in the dma_device structure, device_config and this struct
429 * will then be passed in as an argument to the function.
430 *
431 * The rationale for adding configuration information to this struct is as
432 * follows: if it is likely that more than one DMA slave controllers in
433 * the world will support the configuration option, then make it generic.
434 * If not: if it is fixed so that it be sent in static from the platform
435 * data, then prefer to do that.
436 */
437struct dma_slave_config {
438 enum dma_transfer_direction direction;
439 phys_addr_t src_addr;
440 phys_addr_t dst_addr;
441 enum dma_slave_buswidth src_addr_width;
442 enum dma_slave_buswidth dst_addr_width;
443 u32 src_maxburst;
444 u32 dst_maxburst;
445 u32 src_port_window_size;
446 u32 dst_port_window_size;
447 bool device_fc;
448 void *peripheral_config;
449 size_t peripheral_size;
450};
451
452/**
453 * enum dma_residue_granularity - Granularity of the reported transfer residue
454 * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The
455 * DMA channel is only able to tell whether a descriptor has been completed or
456 * not, which means residue reporting is not supported by this channel. The
457 * residue field of the dma_tx_state field will always be 0.
458 * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully
459 * completed segment of the transfer (For cyclic transfers this is after each
460 * period). This is typically implemented by having the hardware generate an
461 * interrupt after each transferred segment and then the drivers updates the
462 * outstanding residue by the size of the segment. Another possibility is if
463 * the hardware supports scatter-gather and the segment descriptor has a field
464 * which gets set after the segment has been completed. The driver then counts
465 * the number of segments without the flag set to compute the residue.
466 * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred
467 * burst. This is typically only supported if the hardware has a progress
468 * register of some sort (E.g. a register with the current read/write address
469 * or a register with the amount of bursts/beats/bytes that have been
470 * transferred or still need to be transferred).
471 */
472enum dma_residue_granularity {
473 DMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0,
474 DMA_RESIDUE_GRANULARITY_SEGMENT = 1,
475 DMA_RESIDUE_GRANULARITY_BURST = 2,
476};
477
478/**
479 * struct dma_slave_caps - expose capabilities of a slave channel only
480 * @src_addr_widths: bit mask of src addr widths the channel supports.
481 * Width is specified in bytes, e.g. for a channel supporting
482 * a width of 4 the mask should have BIT(4) set.
483 * @dst_addr_widths: bit mask of dst addr widths the channel supports
484 * @directions: bit mask of slave directions the channel supports.
485 * Since the enum dma_transfer_direction is not defined as bit flag for
486 * each type, the dma controller should set BIT(<TYPE>) and same
487 * should be checked by controller as well
488 * @min_burst: min burst capability per-transfer
489 * @max_burst: max burst capability per-transfer
490 * @max_sg_burst: max number of SG list entries executed in a single burst
491 * DMA tansaction with no software intervention for reinitialization.
492 * Zero value means unlimited number of entries.
493 * @cmd_pause: true, if pause is supported (i.e. for reading residue or
494 * for resume later)
495 * @cmd_resume: true, if resume is supported
496 * @cmd_terminate: true, if terminate cmd is supported
497 * @residue_granularity: granularity of the reported transfer residue
498 * @descriptor_reuse: if a descriptor can be reused by client and
499 * resubmitted multiple times
500 */
501struct dma_slave_caps {
502 u32 src_addr_widths;
503 u32 dst_addr_widths;
504 u32 directions;
505 u32 min_burst;
506 u32 max_burst;
507 u32 max_sg_burst;
508 bool cmd_pause;
509 bool cmd_resume;
510 bool cmd_terminate;
511 enum dma_residue_granularity residue_granularity;
512 bool descriptor_reuse;
513};
514
515static inline const char *dma_chan_name(struct dma_chan *chan)
516{
517 return dev_name(dev: &chan->dev->device);
518}
519
520/**
521 * typedef dma_filter_fn - callback filter for dma_request_channel
522 * @chan: channel to be reviewed
523 * @filter_param: opaque parameter passed through dma_request_channel
524 *
525 * When this optional parameter is specified in a call to dma_request_channel a
526 * suitable channel is passed to this routine for further dispositioning before
527 * being returned. Where 'suitable' indicates a non-busy channel that
528 * satisfies the given capability mask. It returns 'true' to indicate that the
529 * channel is suitable.
530 */
531typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
532
533typedef void (*dma_async_tx_callback)(void *dma_async_param);
534
535enum dmaengine_tx_result {
536 DMA_TRANS_NOERROR = 0, /* SUCCESS */
537 DMA_TRANS_READ_FAILED, /* Source DMA read failed */
538 DMA_TRANS_WRITE_FAILED, /* Destination DMA write failed */
539 DMA_TRANS_ABORTED, /* Op never submitted / aborted */
540};
541
542struct dmaengine_result {
543 enum dmaengine_tx_result result;
544 u32 residue;
545};
546
547typedef void (*dma_async_tx_callback_result)(void *dma_async_param,
548 const struct dmaengine_result *result);
549
550struct dmaengine_unmap_data {
551#if IS_ENABLED(CONFIG_DMA_ENGINE_RAID)
552 u16 map_cnt;
553#else
554 u8 map_cnt;
555#endif
556 u8 to_cnt;
557 u8 from_cnt;
558 u8 bidi_cnt;
559 struct device *dev;
560 struct kref kref;
561 size_t len;
562 dma_addr_t addr[];
563};
564
565struct dma_async_tx_descriptor;
566
567struct dma_descriptor_metadata_ops {
568 int (*attach)(struct dma_async_tx_descriptor *desc, void *data,
569 size_t len);
570
571 void *(*get_ptr)(struct dma_async_tx_descriptor *desc,
572 size_t *payload_len, size_t *max_len);
573 int (*set_len)(struct dma_async_tx_descriptor *desc,
574 size_t payload_len);
575};
576
577/**
578 * struct dma_async_tx_descriptor - async transaction descriptor
579 * ---dma generic offload fields---
580 * @cookie: tracking cookie for this transaction, set to -EBUSY if
581 * this tx is sitting on a dependency list
582 * @flags: flags to augment operation preparation, control completion, and
583 * communicate status
584 * @phys: physical address of the descriptor
585 * @chan: target channel for this operation
586 * @tx_submit: accept the descriptor, assign ordered cookie and mark the
587 * descriptor pending. To be pushed on .issue_pending() call
588 * @callback: routine to call after this operation is complete
589 * @callback_param: general parameter to pass to the callback routine
590 * @desc_metadata_mode: core managed metadata mode to protect mixed use of
591 * DESC_METADATA_CLIENT or DESC_METADATA_ENGINE. Otherwise
592 * DESC_METADATA_NONE
593 * @metadata_ops: DMA driver provided metadata mode ops, need to be set by the
594 * DMA driver if metadata mode is supported with the descriptor
595 * ---async_tx api specific fields---
596 * @next: at completion submit this descriptor
597 * @parent: pointer to the next level up in the dependency chain
598 * @lock: protect the parent and next pointers
599 */
600struct dma_async_tx_descriptor {
601 dma_cookie_t cookie;
602 enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
603 dma_addr_t phys;
604 struct dma_chan *chan;
605 dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
606 int (*desc_free)(struct dma_async_tx_descriptor *tx);
607 dma_async_tx_callback callback;
608 dma_async_tx_callback_result callback_result;
609 void *callback_param;
610 struct dmaengine_unmap_data *unmap;
611 enum dma_desc_metadata_mode desc_metadata_mode;
612 struct dma_descriptor_metadata_ops *metadata_ops;
613#ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
614 struct dma_async_tx_descriptor *next;
615 struct dma_async_tx_descriptor *parent;
616 spinlock_t lock;
617#endif
618};
619
620#ifdef CONFIG_DMA_ENGINE
621static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
622 struct dmaengine_unmap_data *unmap)
623{
624 kref_get(kref: &unmap->kref);
625 tx->unmap = unmap;
626}
627
628struct dmaengine_unmap_data *
629dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags);
630void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap);
631#else
632static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
633 struct dmaengine_unmap_data *unmap)
634{
635}
636static inline struct dmaengine_unmap_data *
637dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags)
638{
639 return NULL;
640}
641static inline void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap)
642{
643}
644#endif
645
646static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor *tx)
647{
648 if (!tx->unmap)
649 return;
650
651 dmaengine_unmap_put(unmap: tx->unmap);
652 tx->unmap = NULL;
653}
654
655#ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
656static inline void txd_lock(struct dma_async_tx_descriptor *txd)
657{
658}
659static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
660{
661}
662static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
663{
664 BUG();
665}
666static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
667{
668}
669static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
670{
671}
672static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
673{
674 return NULL;
675}
676static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
677{
678 return NULL;
679}
680
681#else
682static inline void txd_lock(struct dma_async_tx_descriptor *txd)
683{
684 spin_lock_bh(lock: &txd->lock);
685}
686static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
687{
688 spin_unlock_bh(lock: &txd->lock);
689}
690static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
691{
692 txd->next = next;
693 next->parent = txd;
694}
695static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
696{
697 txd->parent = NULL;
698}
699static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
700{
701 txd->next = NULL;
702}
703static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
704{
705 return txd->parent;
706}
707static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
708{
709 return txd->next;
710}
711#endif
712
713/**
714 * struct dma_tx_state - filled in to report the status of
715 * a transfer.
716 * @last: last completed DMA cookie
717 * @used: last issued DMA cookie (i.e. the one in progress)
718 * @residue: the remaining number of bytes left to transmit
719 * on the selected transfer for states DMA_IN_PROGRESS and
720 * DMA_PAUSED if this is implemented in the driver, else 0
721 * @in_flight_bytes: amount of data in bytes cached by the DMA.
722 */
723struct dma_tx_state {
724 dma_cookie_t last;
725 dma_cookie_t used;
726 u32 residue;
727 u32 in_flight_bytes;
728};
729
730/**
731 * enum dmaengine_alignment - defines alignment of the DMA async tx
732 * buffers
733 */
734enum dmaengine_alignment {
735 DMAENGINE_ALIGN_1_BYTE = 0,
736 DMAENGINE_ALIGN_2_BYTES = 1,
737 DMAENGINE_ALIGN_4_BYTES = 2,
738 DMAENGINE_ALIGN_8_BYTES = 3,
739 DMAENGINE_ALIGN_16_BYTES = 4,
740 DMAENGINE_ALIGN_32_BYTES = 5,
741 DMAENGINE_ALIGN_64_BYTES = 6,
742 DMAENGINE_ALIGN_128_BYTES = 7,
743 DMAENGINE_ALIGN_256_BYTES = 8,
744};
745
746/**
747 * struct dma_slave_map - associates slave device and it's slave channel with
748 * parameter to be used by a filter function
749 * @devname: name of the device
750 * @slave: slave channel name
751 * @param: opaque parameter to pass to struct dma_filter.fn
752 */
753struct dma_slave_map {
754 const char *devname;
755 const char *slave;
756 void *param;
757};
758
759/**
760 * struct dma_filter - information for slave device/channel to filter_fn/param
761 * mapping
762 * @fn: filter function callback
763 * @mapcnt: number of slave device/channel in the map
764 * @map: array of channel to filter mapping data
765 */
766struct dma_filter {
767 dma_filter_fn fn;
768 int mapcnt;
769 const struct dma_slave_map *map;
770};
771
772/**
773 * struct dma_device - info on the entity supplying DMA services
774 * @ref: reference is taken and put every time a channel is allocated or freed
775 * @chancnt: how many DMA channels are supported
776 * @privatecnt: how many DMA channels are requested by dma_request_channel
777 * @channels: the list of struct dma_chan
778 * @global_node: list_head for global dma_device_list
779 * @filter: information for device/slave to filter function/param mapping
780 * @cap_mask: one or more dma_capability flags
781 * @desc_metadata_modes: supported metadata modes by the DMA device
782 * @max_xor: maximum number of xor sources, 0 if no capability
783 * @max_pq: maximum number of PQ sources and PQ-continue capability
784 * @copy_align: alignment shift for memcpy operations
785 * @xor_align: alignment shift for xor operations
786 * @pq_align: alignment shift for pq operations
787 * @fill_align: alignment shift for memset operations
788 * @dev_id: unique device ID
789 * @dev: struct device reference for dma mapping api
790 * @owner: owner module (automatically set based on the provided dev)
791 * @chan_ida: unique channel ID
792 * @src_addr_widths: bit mask of src addr widths the device supports
793 * Width is specified in bytes, e.g. for a device supporting
794 * a width of 4 the mask should have BIT(4) set.
795 * @dst_addr_widths: bit mask of dst addr widths the device supports
796 * @directions: bit mask of slave directions the device supports.
797 * Since the enum dma_transfer_direction is not defined as bit flag for
798 * each type, the dma controller should set BIT(<TYPE>) and same
799 * should be checked by controller as well
800 * @min_burst: min burst capability per-transfer
801 * @max_burst: max burst capability per-transfer
802 * @max_sg_burst: max number of SG list entries executed in a single burst
803 * DMA tansaction with no software intervention for reinitialization.
804 * Zero value means unlimited number of entries.
805 * @descriptor_reuse: a submitted transfer can be resubmitted after completion
806 * @residue_granularity: granularity of the transfer residue reported
807 * by tx_status
808 * @device_alloc_chan_resources: allocate resources and return the
809 * number of allocated descriptors
810 * @device_router_config: optional callback for DMA router configuration
811 * @device_free_chan_resources: release DMA channel's resources
812 * @device_prep_dma_memcpy: prepares a memcpy operation
813 * @device_prep_dma_xor: prepares a xor operation
814 * @device_prep_dma_xor_val: prepares a xor validation operation
815 * @device_prep_dma_pq: prepares a pq operation
816 * @device_prep_dma_pq_val: prepares a pqzero_sum operation
817 * @device_prep_dma_memset: prepares a memset operation
818 * @device_prep_dma_memset_sg: prepares a memset operation over a scatter list
819 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
820 * @device_prep_slave_sg: prepares a slave dma operation
821 * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
822 * The function takes a buffer of size buf_len. The callback function will
823 * be called after period_len bytes have been transferred.
824 * @device_prep_interleaved_dma: Transfer expression in a generic way.
825 * @device_prep_dma_imm_data: DMA's 8 byte immediate data to the dst address
826 * @device_caps: May be used to override the generic DMA slave capabilities
827 * with per-channel specific ones
828 * @device_config: Pushes a new configuration to a channel, return 0 or an error
829 * code
830 * @device_pause: Pauses any transfer happening on a channel. Returns
831 * 0 or an error code
832 * @device_resume: Resumes any transfer on a channel previously
833 * paused. Returns 0 or an error code
834 * @device_terminate_all: Aborts all transfers on a channel. Returns 0
835 * or an error code
836 * @device_synchronize: Synchronizes the termination of a transfers to the
837 * current context.
838 * @device_tx_status: poll for transaction completion, the optional
839 * txstate parameter can be supplied with a pointer to get a
840 * struct with auxiliary transfer status information, otherwise the call
841 * will just return a simple status code
842 * @device_issue_pending: push pending transactions to hardware
843 * @device_release: called sometime atfer dma_async_device_unregister() is
844 * called and there are no further references to this structure. This
845 * must be implemented to free resources however many existing drivers
846 * do not and are therefore not safe to unbind while in use.
847 * @dbg_summary_show: optional routine to show contents in debugfs; default code
848 * will be used when this is omitted, but custom code can show extra,
849 * controller specific information.
850 * @dbg_dev_root: the root folder in debugfs for this device
851 */
852struct dma_device {
853 struct kref ref;
854 unsigned int chancnt;
855 unsigned int privatecnt;
856 struct list_head channels;
857 struct list_head global_node;
858 struct dma_filter filter;
859 dma_cap_mask_t cap_mask;
860 enum dma_desc_metadata_mode desc_metadata_modes;
861 unsigned short max_xor;
862 unsigned short max_pq;
863 enum dmaengine_alignment copy_align;
864 enum dmaengine_alignment xor_align;
865 enum dmaengine_alignment pq_align;
866 enum dmaengine_alignment fill_align;
867 #define DMA_HAS_PQ_CONTINUE (1 << 15)
868
869 int dev_id;
870 struct device *dev;
871 struct module *owner;
872 struct ida chan_ida;
873
874 u32 src_addr_widths;
875 u32 dst_addr_widths;
876 u32 directions;
877 u32 min_burst;
878 u32 max_burst;
879 u32 max_sg_burst;
880 bool descriptor_reuse;
881 enum dma_residue_granularity residue_granularity;
882
883 int (*device_alloc_chan_resources)(struct dma_chan *chan);
884 int (*device_router_config)(struct dma_chan *chan);
885 void (*device_free_chan_resources)(struct dma_chan *chan);
886
887 struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
888 struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
889 size_t len, unsigned long flags);
890 struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
891 struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src,
892 unsigned int src_cnt, size_t len, unsigned long flags);
893 struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
894 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
895 size_t len, enum sum_check_flags *result, unsigned long flags);
896 struct dma_async_tx_descriptor *(*device_prep_dma_pq)(
897 struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
898 unsigned int src_cnt, const unsigned char *scf,
899 size_t len, unsigned long flags);
900 struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)(
901 struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
902 unsigned int src_cnt, const unsigned char *scf, size_t len,
903 enum sum_check_flags *pqres, unsigned long flags);
904 struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
905 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
906 unsigned long flags);
907 struct dma_async_tx_descriptor *(*device_prep_dma_memset_sg)(
908 struct dma_chan *chan, struct scatterlist *sg,
909 unsigned int nents, int value, unsigned long flags);
910 struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
911 struct dma_chan *chan, unsigned long flags);
912
913 struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
914 struct dma_chan *chan, struct scatterlist *sgl,
915 unsigned int sg_len, enum dma_transfer_direction direction,
916 unsigned long flags, void *context);
917 struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)(
918 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
919 size_t period_len, enum dma_transfer_direction direction,
920 unsigned long flags);
921 struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
922 struct dma_chan *chan, struct dma_interleaved_template *xt,
923 unsigned long flags);
924 struct dma_async_tx_descriptor *(*device_prep_dma_imm_data)(
925 struct dma_chan *chan, dma_addr_t dst, u64 data,
926 unsigned long flags);
927
928 void (*device_caps)(struct dma_chan *chan, struct dma_slave_caps *caps);
929 int (*device_config)(struct dma_chan *chan, struct dma_slave_config *config);
930 int (*device_pause)(struct dma_chan *chan);
931 int (*device_resume)(struct dma_chan *chan);
932 int (*device_terminate_all)(struct dma_chan *chan);
933 void (*device_synchronize)(struct dma_chan *chan);
934
935 enum dma_status (*device_tx_status)(struct dma_chan *chan,
936 dma_cookie_t cookie,
937 struct dma_tx_state *txstate);
938 void (*device_issue_pending)(struct dma_chan *chan);
939 void (*device_release)(struct dma_device *dev);
940 /* debugfs support */
941 void (*dbg_summary_show)(struct seq_file *s, struct dma_device *dev);
942 struct dentry *dbg_dev_root;
943};
944
945static inline int dmaengine_slave_config(struct dma_chan *chan,
946 struct dma_slave_config *config)
947{
948 if (chan->device->device_config)
949 return chan->device->device_config(chan, config);
950
951 return -ENOSYS;
952}
953
954static inline bool is_slave_direction(enum dma_transfer_direction direction)
955{
956 return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM);
957}
958
959static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single(
960 struct dma_chan *chan, dma_addr_t buf, size_t len,
961 enum dma_transfer_direction dir, unsigned long flags)
962{
963 struct scatterlist sg;
964 sg_init_table(&sg, 1);
965 sg_dma_address(&sg) = buf;
966 sg_dma_len(&sg) = len;
967
968 if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
969 return NULL;
970
971 return chan->device->device_prep_slave_sg(chan, &sg, 1,
972 dir, flags, NULL);
973}
974
975static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg(
976 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
977 enum dma_transfer_direction dir, unsigned long flags)
978{
979 if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
980 return NULL;
981
982 return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
983 dir, flags, NULL);
984}
985
986#ifdef CONFIG_RAPIDIO_DMA_ENGINE
987struct rio_dma_ext;
988static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg(
989 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
990 enum dma_transfer_direction dir, unsigned long flags,
991 struct rio_dma_ext *rio_ext)
992{
993 if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
994 return NULL;
995
996 return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
997 dir, flags, rio_ext);
998}
999#endif
1000
1001static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic(
1002 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
1003 size_t period_len, enum dma_transfer_direction dir,
1004 unsigned long flags)
1005{
1006 if (!chan || !chan->device || !chan->device->device_prep_dma_cyclic)
1007 return NULL;
1008
1009 return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len,
1010 period_len, dir, flags);
1011}
1012
1013static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma(
1014 struct dma_chan *chan, struct dma_interleaved_template *xt,
1015 unsigned long flags)
1016{
1017 if (!chan || !chan->device || !chan->device->device_prep_interleaved_dma)
1018 return NULL;
1019 if (flags & DMA_PREP_REPEAT &&
1020 !test_bit(DMA_REPEAT, chan->device->cap_mask.bits))
1021 return NULL;
1022
1023 return chan->device->device_prep_interleaved_dma(chan, xt, flags);
1024}
1025
1026/**
1027 * dmaengine_prep_dma_memset() - Prepare a DMA memset descriptor.
1028 * @chan: The channel to be used for this descriptor
1029 * @dest: Address of buffer to be set
1030 * @value: Treated as a single byte value that fills the destination buffer
1031 * @len: The total size of dest
1032 * @flags: DMA engine flags
1033 */
1034static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memset(
1035 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
1036 unsigned long flags)
1037{
1038 if (!chan || !chan->device || !chan->device->device_prep_dma_memset)
1039 return NULL;
1040
1041 return chan->device->device_prep_dma_memset(chan, dest, value,
1042 len, flags);
1043}
1044
1045static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memcpy(
1046 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1047 size_t len, unsigned long flags)
1048{
1049 if (!chan || !chan->device || !chan->device->device_prep_dma_memcpy)
1050 return NULL;
1051
1052 return chan->device->device_prep_dma_memcpy(chan, dest, src,
1053 len, flags);
1054}
1055
1056static inline bool dmaengine_is_metadata_mode_supported(struct dma_chan *chan,
1057 enum dma_desc_metadata_mode mode)
1058{
1059 if (!chan)
1060 return false;
1061
1062 return !!(chan->device->desc_metadata_modes & mode);
1063}
1064
1065#ifdef CONFIG_DMA_ENGINE
1066int dmaengine_desc_attach_metadata(struct dma_async_tx_descriptor *desc,
1067 void *data, size_t len);
1068void *dmaengine_desc_get_metadata_ptr(struct dma_async_tx_descriptor *desc,
1069 size_t *payload_len, size_t *max_len);
1070int dmaengine_desc_set_metadata_len(struct dma_async_tx_descriptor *desc,
1071 size_t payload_len);
1072#else /* CONFIG_DMA_ENGINE */
1073static inline int dmaengine_desc_attach_metadata(
1074 struct dma_async_tx_descriptor *desc, void *data, size_t len)
1075{
1076 return -EINVAL;
1077}
1078static inline void *dmaengine_desc_get_metadata_ptr(
1079 struct dma_async_tx_descriptor *desc, size_t *payload_len,
1080 size_t *max_len)
1081{
1082 return NULL;
1083}
1084static inline int dmaengine_desc_set_metadata_len(
1085 struct dma_async_tx_descriptor *desc, size_t payload_len)
1086{
1087 return -EINVAL;
1088}
1089#endif /* CONFIG_DMA_ENGINE */
1090
1091/**
1092 * dmaengine_terminate_all() - Terminate all active DMA transfers
1093 * @chan: The channel for which to terminate the transfers
1094 *
1095 * This function is DEPRECATED use either dmaengine_terminate_sync() or
1096 * dmaengine_terminate_async() instead.
1097 */
1098static inline int dmaengine_terminate_all(struct dma_chan *chan)
1099{
1100 if (chan->device->device_terminate_all)
1101 return chan->device->device_terminate_all(chan);
1102
1103 return -ENOSYS;
1104}
1105
1106/**
1107 * dmaengine_terminate_async() - Terminate all active DMA transfers
1108 * @chan: The channel for which to terminate the transfers
1109 *
1110 * Calling this function will terminate all active and pending descriptors
1111 * that have previously been submitted to the channel. It is not guaranteed
1112 * though that the transfer for the active descriptor has stopped when the
1113 * function returns. Furthermore it is possible the complete callback of a
1114 * submitted transfer is still running when this function returns.
1115 *
1116 * dmaengine_synchronize() needs to be called before it is safe to free
1117 * any memory that is accessed by previously submitted descriptors or before
1118 * freeing any resources accessed from within the completion callback of any
1119 * previously submitted descriptors.
1120 *
1121 * This function can be called from atomic context as well as from within a
1122 * complete callback of a descriptor submitted on the same channel.
1123 *
1124 * If none of the two conditions above apply consider using
1125 * dmaengine_terminate_sync() instead.
1126 */
1127static inline int dmaengine_terminate_async(struct dma_chan *chan)
1128{
1129 if (chan->device->device_terminate_all)
1130 return chan->device->device_terminate_all(chan);
1131
1132 return -EINVAL;
1133}
1134
1135/**
1136 * dmaengine_synchronize() - Synchronize DMA channel termination
1137 * @chan: The channel to synchronize
1138 *
1139 * Synchronizes to the DMA channel termination to the current context. When this
1140 * function returns it is guaranteed that all transfers for previously issued
1141 * descriptors have stopped and it is safe to free the memory associated
1142 * with them. Furthermore it is guaranteed that all complete callback functions
1143 * for a previously submitted descriptor have finished running and it is safe to
1144 * free resources accessed from within the complete callbacks.
1145 *
1146 * The behavior of this function is undefined if dma_async_issue_pending() has
1147 * been called between dmaengine_terminate_async() and this function.
1148 *
1149 * This function must only be called from non-atomic context and must not be
1150 * called from within a complete callback of a descriptor submitted on the same
1151 * channel.
1152 */
1153static inline void dmaengine_synchronize(struct dma_chan *chan)
1154{
1155 might_sleep();
1156
1157 if (chan->device->device_synchronize)
1158 chan->device->device_synchronize(chan);
1159}
1160
1161/**
1162 * dmaengine_terminate_sync() - Terminate all active DMA transfers
1163 * @chan: The channel for which to terminate the transfers
1164 *
1165 * Calling this function will terminate all active and pending transfers
1166 * that have previously been submitted to the channel. It is similar to
1167 * dmaengine_terminate_async() but guarantees that the DMA transfer has actually
1168 * stopped and that all complete callbacks have finished running when the
1169 * function returns.
1170 *
1171 * This function must only be called from non-atomic context and must not be
1172 * called from within a complete callback of a descriptor submitted on the same
1173 * channel.
1174 */
1175static inline int dmaengine_terminate_sync(struct dma_chan *chan)
1176{
1177 int ret;
1178
1179 ret = dmaengine_terminate_async(chan);
1180 if (ret)
1181 return ret;
1182
1183 dmaengine_synchronize(chan);
1184
1185 return 0;
1186}
1187
1188static inline int dmaengine_pause(struct dma_chan *chan)
1189{
1190 if (chan->device->device_pause)
1191 return chan->device->device_pause(chan);
1192
1193 return -ENOSYS;
1194}
1195
1196static inline int dmaengine_resume(struct dma_chan *chan)
1197{
1198 if (chan->device->device_resume)
1199 return chan->device->device_resume(chan);
1200
1201 return -ENOSYS;
1202}
1203
1204static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan,
1205 dma_cookie_t cookie, struct dma_tx_state *state)
1206{
1207 return chan->device->device_tx_status(chan, cookie, state);
1208}
1209
1210static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc)
1211{
1212 return desc->tx_submit(desc);
1213}
1214
1215static inline bool dmaengine_check_align(enum dmaengine_alignment align,
1216 size_t off1, size_t off2, size_t len)
1217{
1218 return !(((1 << align) - 1) & (off1 | off2 | len));
1219}
1220
1221static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1,
1222 size_t off2, size_t len)
1223{
1224 return dmaengine_check_align(align: dev->copy_align, off1, off2, len);
1225}
1226
1227static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1,
1228 size_t off2, size_t len)
1229{
1230 return dmaengine_check_align(align: dev->xor_align, off1, off2, len);
1231}
1232
1233static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1,
1234 size_t off2, size_t len)
1235{
1236 return dmaengine_check_align(align: dev->pq_align, off1, off2, len);
1237}
1238
1239static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1,
1240 size_t off2, size_t len)
1241{
1242 return dmaengine_check_align(align: dev->fill_align, off1, off2, len);
1243}
1244
1245static inline void
1246dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)
1247{
1248 dma->max_pq = maxpq;
1249 if (has_pq_continue)
1250 dma->max_pq |= DMA_HAS_PQ_CONTINUE;
1251}
1252
1253static inline bool dmaf_continue(enum dma_ctrl_flags flags)
1254{
1255 return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE;
1256}
1257
1258static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags)
1259{
1260 enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P;
1261
1262 return (flags & mask) == mask;
1263}
1264
1265static inline bool dma_dev_has_pq_continue(struct dma_device *dma)
1266{
1267 return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;
1268}
1269
1270static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma)
1271{
1272 return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;
1273}
1274
1275/* dma_maxpq - reduce maxpq in the face of continued operations
1276 * @dma - dma device with PQ capability
1277 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
1278 *
1279 * When an engine does not support native continuation we need 3 extra
1280 * source slots to reuse P and Q with the following coefficients:
1281 * 1/ {00} * P : remove P from Q', but use it as a source for P'
1282 * 2/ {01} * Q : use Q to continue Q' calculation
1283 * 3/ {00} * Q : subtract Q from P' to cancel (2)
1284 *
1285 * In the case where P is disabled we only need 1 extra source:
1286 * 1/ {01} * Q : use Q to continue Q' calculation
1287 */
1288static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags)
1289{
1290 if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags))
1291 return dma_dev_to_maxpq(dma);
1292 if (dmaf_p_disabled_continue(flags))
1293 return dma_dev_to_maxpq(dma) - 1;
1294 if (dmaf_continue(flags))
1295 return dma_dev_to_maxpq(dma) - 3;
1296 BUG();
1297}
1298
1299static inline size_t dmaengine_get_icg(bool inc, bool sgl, size_t icg,
1300 size_t dir_icg)
1301{
1302 if (inc) {
1303 if (dir_icg)
1304 return dir_icg;
1305 if (sgl)
1306 return icg;
1307 }
1308
1309 return 0;
1310}
1311
1312static inline size_t dmaengine_get_dst_icg(struct dma_interleaved_template *xt,
1313 struct data_chunk *chunk)
1314{
1315 return dmaengine_get_icg(inc: xt->dst_inc, sgl: xt->dst_sgl,
1316 icg: chunk->icg, dir_icg: chunk->dst_icg);
1317}
1318
1319static inline size_t dmaengine_get_src_icg(struct dma_interleaved_template *xt,
1320 struct data_chunk *chunk)
1321{
1322 return dmaengine_get_icg(inc: xt->src_inc, sgl: xt->src_sgl,
1323 icg: chunk->icg, dir_icg: chunk->src_icg);
1324}
1325
1326/* --- public DMA engine API --- */
1327
1328#ifdef CONFIG_DMA_ENGINE
1329void dmaengine_get(void);
1330void dmaengine_put(void);
1331#else
1332static inline void dmaengine_get(void)
1333{
1334}
1335static inline void dmaengine_put(void)
1336{
1337}
1338#endif
1339
1340#ifdef CONFIG_ASYNC_TX_DMA
1341#define async_dmaengine_get() dmaengine_get()
1342#define async_dmaengine_put() dmaengine_put()
1343#ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
1344#define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
1345#else
1346#define async_dma_find_channel(type) dma_find_channel(type)
1347#endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
1348#else
1349static inline void async_dmaengine_get(void)
1350{
1351}
1352static inline void async_dmaengine_put(void)
1353{
1354}
1355static inline struct dma_chan *
1356async_dma_find_channel(enum dma_transaction_type type)
1357{
1358 return NULL;
1359}
1360#endif /* CONFIG_ASYNC_TX_DMA */
1361void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
1362 struct dma_chan *chan);
1363
1364static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
1365{
1366 tx->flags |= DMA_CTRL_ACK;
1367}
1368
1369static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
1370{
1371 tx->flags &= ~DMA_CTRL_ACK;
1372}
1373
1374static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
1375{
1376 return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
1377}
1378
1379#define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
1380static inline void
1381__dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
1382{
1383 set_bit(nr: tx_type, addr: dstp->bits);
1384}
1385
1386#define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
1387static inline void
1388__dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
1389{
1390 clear_bit(nr: tx_type, addr: dstp->bits);
1391}
1392
1393#define dma_cap_zero(mask) __dma_cap_zero(&(mask))
1394static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
1395{
1396 bitmap_zero(dst: dstp->bits, nbits: DMA_TX_TYPE_END);
1397}
1398
1399#define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
1400static inline int
1401__dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
1402{
1403 return test_bit(tx_type, srcp->bits);
1404}
1405
1406#define for_each_dma_cap_mask(cap, mask) \
1407 for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END)
1408
1409/**
1410 * dma_async_issue_pending - flush pending transactions to HW
1411 * @chan: target DMA channel
1412 *
1413 * This allows drivers to push copies to HW in batches,
1414 * reducing MMIO writes where possible.
1415 */
1416static inline void dma_async_issue_pending(struct dma_chan *chan)
1417{
1418 chan->device->device_issue_pending(chan);
1419}
1420
1421/**
1422 * dma_async_is_tx_complete - poll for transaction completion
1423 * @chan: DMA channel
1424 * @cookie: transaction identifier to check status of
1425 * @last: returns last completed cookie, can be NULL
1426 * @used: returns last issued cookie, can be NULL
1427 *
1428 * If @last and @used are passed in, upon return they reflect the driver
1429 * internal state and can be used with dma_async_is_complete() to check
1430 * the status of multiple cookies without re-checking hardware state.
1431 */
1432static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
1433 dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
1434{
1435 struct dma_tx_state state;
1436 enum dma_status status;
1437
1438 status = chan->device->device_tx_status(chan, cookie, &state);
1439 if (last)
1440 *last = state.last;
1441 if (used)
1442 *used = state.used;
1443 return status;
1444}
1445
1446/**
1447 * dma_async_is_complete - test a cookie against chan state
1448 * @cookie: transaction identifier to test status of
1449 * @last_complete: last know completed transaction
1450 * @last_used: last cookie value handed out
1451 *
1452 * dma_async_is_complete() is used in dma_async_is_tx_complete()
1453 * the test logic is separated for lightweight testing of multiple cookies
1454 */
1455static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
1456 dma_cookie_t last_complete, dma_cookie_t last_used)
1457{
1458 if (last_complete <= last_used) {
1459 if ((cookie <= last_complete) || (cookie > last_used))
1460 return DMA_COMPLETE;
1461 } else {
1462 if ((cookie <= last_complete) && (cookie > last_used))
1463 return DMA_COMPLETE;
1464 }
1465 return DMA_IN_PROGRESS;
1466}
1467
1468static inline void
1469dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue)
1470{
1471 if (!st)
1472 return;
1473
1474 st->last = last;
1475 st->used = used;
1476 st->residue = residue;
1477}
1478
1479#ifdef CONFIG_DMA_ENGINE
1480struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
1481enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
1482enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
1483void dma_issue_pending_all(void);
1484struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
1485 dma_filter_fn fn, void *fn_param,
1486 struct device_node *np);
1487
1488struct dma_chan *dma_request_chan(struct device *dev, const char *name);
1489struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask);
1490
1491void dma_release_channel(struct dma_chan *chan);
1492int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps);
1493#else
1494static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
1495{
1496 return NULL;
1497}
1498static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
1499{
1500 return DMA_COMPLETE;
1501}
1502static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
1503{
1504 return DMA_COMPLETE;
1505}
1506static inline void dma_issue_pending_all(void)
1507{
1508}
1509static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
1510 dma_filter_fn fn,
1511 void *fn_param,
1512 struct device_node *np)
1513{
1514 return NULL;
1515}
1516static inline struct dma_chan *dma_request_chan(struct device *dev,
1517 const char *name)
1518{
1519 return ERR_PTR(-ENODEV);
1520}
1521static inline struct dma_chan *dma_request_chan_by_mask(
1522 const dma_cap_mask_t *mask)
1523{
1524 return ERR_PTR(-ENODEV);
1525}
1526static inline void dma_release_channel(struct dma_chan *chan)
1527{
1528}
1529static inline int dma_get_slave_caps(struct dma_chan *chan,
1530 struct dma_slave_caps *caps)
1531{
1532 return -ENXIO;
1533}
1534#endif
1535
1536static inline int dmaengine_desc_set_reuse(struct dma_async_tx_descriptor *tx)
1537{
1538 struct dma_slave_caps caps;
1539 int ret;
1540
1541 ret = dma_get_slave_caps(chan: tx->chan, caps: &caps);
1542 if (ret)
1543 return ret;
1544
1545 if (!caps.descriptor_reuse)
1546 return -EPERM;
1547
1548 tx->flags |= DMA_CTRL_REUSE;
1549 return 0;
1550}
1551
1552static inline void dmaengine_desc_clear_reuse(struct dma_async_tx_descriptor *tx)
1553{
1554 tx->flags &= ~DMA_CTRL_REUSE;
1555}
1556
1557static inline bool dmaengine_desc_test_reuse(struct dma_async_tx_descriptor *tx)
1558{
1559 return (tx->flags & DMA_CTRL_REUSE) == DMA_CTRL_REUSE;
1560}
1561
1562static inline int dmaengine_desc_free(struct dma_async_tx_descriptor *desc)
1563{
1564 /* this is supported for reusable desc, so check that */
1565 if (!dmaengine_desc_test_reuse(tx: desc))
1566 return -EPERM;
1567
1568 return desc->desc_free(desc);
1569}
1570
1571/* --- DMA device --- */
1572
1573int dma_async_device_register(struct dma_device *device);
1574int dmaenginem_async_device_register(struct dma_device *device);
1575void dma_async_device_unregister(struct dma_device *device);
1576int dma_async_device_channel_register(struct dma_device *device,
1577 struct dma_chan *chan);
1578void dma_async_device_channel_unregister(struct dma_device *device,
1579 struct dma_chan *chan);
1580void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
1581#define dma_request_channel(mask, x, y) \
1582 __dma_request_channel(&(mask), x, y, NULL)
1583
1584/* Deprecated, please use dma_request_chan() directly */
1585static inline struct dma_chan * __deprecated
1586dma_request_slave_channel(struct device *dev, const char *name)
1587{
1588 struct dma_chan *ch = dma_request_chan(dev, name);
1589
1590 return IS_ERR(ptr: ch) ? NULL : ch;
1591}
1592
1593static inline struct dma_chan
1594*dma_request_slave_channel_compat(const dma_cap_mask_t mask,
1595 dma_filter_fn fn, void *fn_param,
1596 struct device *dev, const char *name)
1597{
1598 struct dma_chan *chan;
1599
1600 chan = dma_request_slave_channel(dev, name);
1601 if (chan)
1602 return chan;
1603
1604 if (!fn || !fn_param)
1605 return NULL;
1606
1607 return __dma_request_channel(mask: &mask, fn, fn_param, NULL);
1608}
1609
1610static inline char *
1611dmaengine_get_direction_text(enum dma_transfer_direction dir)
1612{
1613 switch (dir) {
1614 case DMA_DEV_TO_MEM:
1615 return "DEV_TO_MEM";
1616 case DMA_MEM_TO_DEV:
1617 return "MEM_TO_DEV";
1618 case DMA_MEM_TO_MEM:
1619 return "MEM_TO_MEM";
1620 case DMA_DEV_TO_DEV:
1621 return "DEV_TO_DEV";
1622 default:
1623 return "invalid";
1624 }
1625}
1626
1627static inline struct device *dmaengine_get_dma_device(struct dma_chan *chan)
1628{
1629 if (chan->dev->chan_dma_dev)
1630 return &chan->dev->device;
1631
1632 return chan->device->dev;
1633}
1634
1635#endif /* DMAENGINE_H */
1636

source code of linux/include/linux/dmaengine.h