1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * Xilinx Zynq MPSoC Firmware layer |
4 | * |
5 | * Copyright (C) 2014-2021 Xilinx |
6 | * |
7 | * Michal Simek <michal.simek@amd.com> |
8 | * Davorin Mista <davorin.mista@aggios.com> |
9 | * Jolly Shah <jollys@xilinx.com> |
10 | * Rajan Vaja <rajanv@xilinx.com> |
11 | */ |
12 | |
13 | #ifndef __FIRMWARE_ZYNQMP_H__ |
14 | #define __FIRMWARE_ZYNQMP_H__ |
15 | #include <linux/types.h> |
16 | |
17 | #include <linux/err.h> |
18 | |
19 | #define ZYNQMP_PM_VERSION_MAJOR 1 |
20 | #define ZYNQMP_PM_VERSION_MINOR 0 |
21 | |
22 | #define ZYNQMP_PM_VERSION ((ZYNQMP_PM_VERSION_MAJOR << 16) | \ |
23 | ZYNQMP_PM_VERSION_MINOR) |
24 | |
25 | #define ZYNQMP_TZ_VERSION_MAJOR 1 |
26 | #define ZYNQMP_TZ_VERSION_MINOR 0 |
27 | |
28 | #define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \ |
29 | ZYNQMP_TZ_VERSION_MINOR) |
30 | |
31 | /* SMC SIP service Call Function Identifier Prefix */ |
32 | #define PM_SIP_SVC 0xC2000000 |
33 | |
34 | /* PM API versions */ |
35 | #define PM_API_VERSION_2 2 |
36 | |
37 | #define PM_PINCTRL_PARAM_SET_VERSION 2 |
38 | |
39 | #define ZYNQMP_FAMILY_CODE 0x23 |
40 | #define VERSAL_FAMILY_CODE 0x26 |
41 | |
42 | /* When all subfamily of platform need to support */ |
43 | #define ALL_SUB_FAMILY_CODE 0x00 |
44 | #define VERSAL_SUB_FAMILY_CODE 0x01 |
45 | #define VERSALNET_SUB_FAMILY_CODE 0x03 |
46 | |
47 | #define FAMILY_CODE_MASK GENMASK(27, 21) |
48 | #define SUB_FAMILY_CODE_MASK GENMASK(20, 19) |
49 | |
50 | /* ATF only commands */ |
51 | #define TF_A_PM_REGISTER_SGI 0xa04 |
52 | #define PM_GET_TRUSTZONE_VERSION 0xa03 |
53 | #define PM_SET_SUSPEND_MODE 0xa02 |
54 | #define GET_CALLBACK_DATA 0xa01 |
55 | |
56 | /* Number of 32bits values in payload */ |
57 | #define PAYLOAD_ARG_CNT 4U |
58 | |
59 | /* Number of arguments for a callback */ |
60 | #define CB_ARG_CNT 4 |
61 | |
62 | /* Payload size (consists of callback API ID + arguments) */ |
63 | #define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1) |
64 | |
65 | #define ZYNQMP_PM_MAX_QOS 100U |
66 | |
67 | #define GSS_NUM_REGS (4) |
68 | |
69 | /* Node capabilities */ |
70 | #define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U |
71 | #define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U |
72 | #define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U |
73 | #define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U |
74 | |
75 | /* Loader commands */ |
76 | #define PM_LOAD_PDI 0x701 |
77 | #define PDI_SRC_DDR 0xF |
78 | |
79 | /* |
80 | * Firmware FPGA Manager flags |
81 | * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration |
82 | * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration |
83 | */ |
84 | #define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U |
85 | #define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0) |
86 | |
87 | /* FPGA Status Reg */ |
88 | #define XILINX_ZYNQMP_PM_FPGA_CONFIG_STAT_OFFSET 7U |
89 | #define XILINX_ZYNQMP_PM_FPGA_READ_CONFIG_REG 0U |
90 | |
91 | /* |
92 | * Node IDs for the Error Events. |
93 | */ |
94 | #define EVENT_ERROR_PMC_ERR1 (0x28100000U) |
95 | #define EVENT_ERROR_PMC_ERR2 (0x28104000U) |
96 | #define EVENT_ERROR_PSM_ERR1 (0x28108000U) |
97 | #define EVENT_ERROR_PSM_ERR2 (0x2810C000U) |
98 | |
99 | /* ZynqMP SD tap delay tuning */ |
100 | #define SD_ITAPDLY 0xFF180314 |
101 | #define SD_OTAPDLYSEL 0xFF180318 |
102 | |
103 | /** |
104 | * XPM_EVENT_ERROR_MASK_DDRMC_CR: Error event mask for DDRMC MC Correctable ECC Error. |
105 | */ |
106 | #define XPM_EVENT_ERROR_MASK_DDRMC_CR BIT(18) |
107 | |
108 | /** |
109 | * XPM_EVENT_ERROR_MASK_DDRMC_NCR: Error event mask for DDRMC MC Non-Correctable ECC Error. |
110 | */ |
111 | #define XPM_EVENT_ERROR_MASK_DDRMC_NCR BIT(19) |
112 | #define XPM_EVENT_ERROR_MASK_NOC_NCR BIT(13) |
113 | #define XPM_EVENT_ERROR_MASK_NOC_CR BIT(12) |
114 | |
115 | enum pm_api_cb_id { |
116 | PM_INIT_SUSPEND_CB = 30, |
117 | PM_ACKNOWLEDGE_CB = 31, |
118 | PM_NOTIFY_CB = 32, |
119 | }; |
120 | |
121 | enum pm_api_id { |
122 | PM_GET_API_VERSION = 1, |
123 | PM_REGISTER_NOTIFIER = 5, |
124 | PM_FORCE_POWERDOWN = 8, |
125 | PM_REQUEST_WAKEUP = 10, |
126 | PM_SYSTEM_SHUTDOWN = 12, |
127 | PM_REQUEST_NODE = 13, |
128 | PM_RELEASE_NODE = 14, |
129 | PM_SET_REQUIREMENT = 15, |
130 | PM_RESET_ASSERT = 17, |
131 | PM_RESET_GET_STATUS = 18, |
132 | PM_MMIO_WRITE = 19, |
133 | PM_MMIO_READ = 20, |
134 | PM_PM_INIT_FINALIZE = 21, |
135 | PM_FPGA_LOAD = 22, |
136 | PM_FPGA_GET_STATUS = 23, |
137 | PM_GET_CHIPID = 24, |
138 | PM_SECURE_SHA = 26, |
139 | PM_PINCTRL_REQUEST = 28, |
140 | PM_PINCTRL_RELEASE = 29, |
141 | PM_PINCTRL_GET_FUNCTION = 30, |
142 | PM_PINCTRL_SET_FUNCTION = 31, |
143 | PM_PINCTRL_CONFIG_PARAM_GET = 32, |
144 | PM_PINCTRL_CONFIG_PARAM_SET = 33, |
145 | PM_IOCTL = 34, |
146 | PM_QUERY_DATA = 35, |
147 | PM_CLOCK_ENABLE = 36, |
148 | PM_CLOCK_DISABLE = 37, |
149 | PM_CLOCK_GETSTATE = 38, |
150 | PM_CLOCK_SETDIVIDER = 39, |
151 | PM_CLOCK_GETDIVIDER = 40, |
152 | PM_CLOCK_SETRATE = 41, |
153 | PM_CLOCK_GETRATE = 42, |
154 | PM_CLOCK_SETPARENT = 43, |
155 | PM_CLOCK_GETPARENT = 44, |
156 | PM_FPGA_READ = 46, |
157 | PM_SECURE_AES = 47, |
158 | PM_FEATURE_CHECK = 63, |
159 | }; |
160 | |
161 | /* PMU-FW return status codes */ |
162 | enum pm_ret_status { |
163 | XST_PM_SUCCESS = 0, |
164 | XST_PM_NO_FEATURE = 19, |
165 | XST_PM_INTERNAL = 2000, |
166 | XST_PM_CONFLICT = 2001, |
167 | XST_PM_NO_ACCESS = 2002, |
168 | XST_PM_INVALID_NODE = 2003, |
169 | XST_PM_DOUBLE_REQ = 2004, |
170 | XST_PM_ABORT_SUSPEND = 2005, |
171 | XST_PM_MULT_USER = 2008, |
172 | }; |
173 | |
174 | enum pm_ioctl_id { |
175 | IOCTL_GET_RPU_OPER_MODE = 0, |
176 | IOCTL_SET_RPU_OPER_MODE = 1, |
177 | IOCTL_RPU_BOOT_ADDR_CONFIG = 2, |
178 | IOCTL_TCM_COMB_CONFIG = 3, |
179 | IOCTL_SET_TAPDELAY_BYPASS = 4, |
180 | IOCTL_SD_DLL_RESET = 6, |
181 | IOCTL_SET_SD_TAPDELAY = 7, |
182 | IOCTL_SET_PLL_FRAC_MODE = 8, |
183 | IOCTL_GET_PLL_FRAC_MODE = 9, |
184 | IOCTL_SET_PLL_FRAC_DATA = 10, |
185 | IOCTL_GET_PLL_FRAC_DATA = 11, |
186 | IOCTL_WRITE_GGS = 12, |
187 | IOCTL_READ_GGS = 13, |
188 | IOCTL_WRITE_PGGS = 14, |
189 | IOCTL_READ_PGGS = 15, |
190 | /* Set healthy bit value */ |
191 | IOCTL_SET_BOOT_HEALTH_STATUS = 17, |
192 | IOCTL_OSPI_MUX_SELECT = 21, |
193 | /* Register SGI to ATF */ |
194 | IOCTL_REGISTER_SGI = 25, |
195 | /* Runtime feature configuration */ |
196 | IOCTL_SET_FEATURE_CONFIG = 26, |
197 | IOCTL_GET_FEATURE_CONFIG = 27, |
198 | /* Dynamic SD/GEM configuration */ |
199 | IOCTL_SET_SD_CONFIG = 30, |
200 | IOCTL_SET_GEM_CONFIG = 31, |
201 | }; |
202 | |
203 | enum pm_query_id { |
204 | PM_QID_INVALID = 0, |
205 | PM_QID_CLOCK_GET_NAME = 1, |
206 | PM_QID_CLOCK_GET_TOPOLOGY = 2, |
207 | PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3, |
208 | PM_QID_CLOCK_GET_PARENTS = 4, |
209 | PM_QID_CLOCK_GET_ATTRIBUTES = 5, |
210 | PM_QID_PINCTRL_GET_NUM_PINS = 6, |
211 | PM_QID_PINCTRL_GET_NUM_FUNCTIONS = 7, |
212 | PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS = 8, |
213 | PM_QID_PINCTRL_GET_FUNCTION_NAME = 9, |
214 | PM_QID_PINCTRL_GET_FUNCTION_GROUPS = 10, |
215 | PM_QID_PINCTRL_GET_PIN_GROUPS = 11, |
216 | PM_QID_CLOCK_GET_NUM_CLOCKS = 12, |
217 | PM_QID_CLOCK_GET_MAX_DIVISOR = 13, |
218 | }; |
219 | |
220 | enum rpu_oper_mode { |
221 | PM_RPU_MODE_LOCKSTEP = 0, |
222 | PM_RPU_MODE_SPLIT = 1, |
223 | }; |
224 | |
225 | enum rpu_boot_mem { |
226 | PM_RPU_BOOTMEM_LOVEC = 0, |
227 | PM_RPU_BOOTMEM_HIVEC = 1, |
228 | }; |
229 | |
230 | enum rpu_tcm_comb { |
231 | PM_RPU_TCM_SPLIT = 0, |
232 | PM_RPU_TCM_COMB = 1, |
233 | }; |
234 | |
235 | enum zynqmp_pm_reset_action { |
236 | PM_RESET_ACTION_RELEASE = 0, |
237 | PM_RESET_ACTION_ASSERT = 1, |
238 | PM_RESET_ACTION_PULSE = 2, |
239 | }; |
240 | |
241 | enum zynqmp_pm_reset { |
242 | ZYNQMP_PM_RESET_START = 1000, |
243 | ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START, |
244 | ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001, |
245 | ZYNQMP_PM_RESET_PCIE_CTRL = 1002, |
246 | ZYNQMP_PM_RESET_DP = 1003, |
247 | ZYNQMP_PM_RESET_SWDT_CRF = 1004, |
248 | ZYNQMP_PM_RESET_AFI_FM5 = 1005, |
249 | ZYNQMP_PM_RESET_AFI_FM4 = 1006, |
250 | ZYNQMP_PM_RESET_AFI_FM3 = 1007, |
251 | ZYNQMP_PM_RESET_AFI_FM2 = 1008, |
252 | ZYNQMP_PM_RESET_AFI_FM1 = 1009, |
253 | ZYNQMP_PM_RESET_AFI_FM0 = 1010, |
254 | ZYNQMP_PM_RESET_GDMA = 1011, |
255 | ZYNQMP_PM_RESET_GPU_PP1 = 1012, |
256 | ZYNQMP_PM_RESET_GPU_PP0 = 1013, |
257 | ZYNQMP_PM_RESET_GPU = 1014, |
258 | ZYNQMP_PM_RESET_GT = 1015, |
259 | ZYNQMP_PM_RESET_SATA = 1016, |
260 | ZYNQMP_PM_RESET_ACPU3_PWRON = 1017, |
261 | ZYNQMP_PM_RESET_ACPU2_PWRON = 1018, |
262 | ZYNQMP_PM_RESET_ACPU1_PWRON = 1019, |
263 | ZYNQMP_PM_RESET_ACPU0_PWRON = 1020, |
264 | ZYNQMP_PM_RESET_APU_L2 = 1021, |
265 | ZYNQMP_PM_RESET_ACPU3 = 1022, |
266 | ZYNQMP_PM_RESET_ACPU2 = 1023, |
267 | ZYNQMP_PM_RESET_ACPU1 = 1024, |
268 | ZYNQMP_PM_RESET_ACPU0 = 1025, |
269 | ZYNQMP_PM_RESET_DDR = 1026, |
270 | ZYNQMP_PM_RESET_APM_FPD = 1027, |
271 | ZYNQMP_PM_RESET_SOFT = 1028, |
272 | ZYNQMP_PM_RESET_GEM0 = 1029, |
273 | ZYNQMP_PM_RESET_GEM1 = 1030, |
274 | ZYNQMP_PM_RESET_GEM2 = 1031, |
275 | ZYNQMP_PM_RESET_GEM3 = 1032, |
276 | ZYNQMP_PM_RESET_QSPI = 1033, |
277 | ZYNQMP_PM_RESET_UART0 = 1034, |
278 | ZYNQMP_PM_RESET_UART1 = 1035, |
279 | ZYNQMP_PM_RESET_SPI0 = 1036, |
280 | ZYNQMP_PM_RESET_SPI1 = 1037, |
281 | ZYNQMP_PM_RESET_SDIO0 = 1038, |
282 | ZYNQMP_PM_RESET_SDIO1 = 1039, |
283 | ZYNQMP_PM_RESET_CAN0 = 1040, |
284 | ZYNQMP_PM_RESET_CAN1 = 1041, |
285 | ZYNQMP_PM_RESET_I2C0 = 1042, |
286 | ZYNQMP_PM_RESET_I2C1 = 1043, |
287 | ZYNQMP_PM_RESET_TTC0 = 1044, |
288 | ZYNQMP_PM_RESET_TTC1 = 1045, |
289 | ZYNQMP_PM_RESET_TTC2 = 1046, |
290 | ZYNQMP_PM_RESET_TTC3 = 1047, |
291 | ZYNQMP_PM_RESET_SWDT_CRL = 1048, |
292 | ZYNQMP_PM_RESET_NAND = 1049, |
293 | ZYNQMP_PM_RESET_ADMA = 1050, |
294 | ZYNQMP_PM_RESET_GPIO = 1051, |
295 | ZYNQMP_PM_RESET_IOU_CC = 1052, |
296 | ZYNQMP_PM_RESET_TIMESTAMP = 1053, |
297 | ZYNQMP_PM_RESET_RPU_R50 = 1054, |
298 | ZYNQMP_PM_RESET_RPU_R51 = 1055, |
299 | ZYNQMP_PM_RESET_RPU_AMBA = 1056, |
300 | ZYNQMP_PM_RESET_OCM = 1057, |
301 | ZYNQMP_PM_RESET_RPU_PGE = 1058, |
302 | ZYNQMP_PM_RESET_USB0_CORERESET = 1059, |
303 | ZYNQMP_PM_RESET_USB1_CORERESET = 1060, |
304 | ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061, |
305 | ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062, |
306 | ZYNQMP_PM_RESET_USB0_APB = 1063, |
307 | ZYNQMP_PM_RESET_USB1_APB = 1064, |
308 | ZYNQMP_PM_RESET_IPI = 1065, |
309 | ZYNQMP_PM_RESET_APM_LPD = 1066, |
310 | ZYNQMP_PM_RESET_RTC = 1067, |
311 | ZYNQMP_PM_RESET_SYSMON = 1068, |
312 | ZYNQMP_PM_RESET_AFI_FM6 = 1069, |
313 | ZYNQMP_PM_RESET_LPD_SWDT = 1070, |
314 | ZYNQMP_PM_RESET_FPD = 1071, |
315 | ZYNQMP_PM_RESET_RPU_DBG1 = 1072, |
316 | ZYNQMP_PM_RESET_RPU_DBG0 = 1073, |
317 | ZYNQMP_PM_RESET_DBG_LPD = 1074, |
318 | ZYNQMP_PM_RESET_DBG_FPD = 1075, |
319 | ZYNQMP_PM_RESET_APLL = 1076, |
320 | ZYNQMP_PM_RESET_DPLL = 1077, |
321 | ZYNQMP_PM_RESET_VPLL = 1078, |
322 | ZYNQMP_PM_RESET_IOPLL = 1079, |
323 | ZYNQMP_PM_RESET_RPLL = 1080, |
324 | ZYNQMP_PM_RESET_GPO3_PL_0 = 1081, |
325 | ZYNQMP_PM_RESET_GPO3_PL_1 = 1082, |
326 | ZYNQMP_PM_RESET_GPO3_PL_2 = 1083, |
327 | ZYNQMP_PM_RESET_GPO3_PL_3 = 1084, |
328 | ZYNQMP_PM_RESET_GPO3_PL_4 = 1085, |
329 | ZYNQMP_PM_RESET_GPO3_PL_5 = 1086, |
330 | ZYNQMP_PM_RESET_GPO3_PL_6 = 1087, |
331 | ZYNQMP_PM_RESET_GPO3_PL_7 = 1088, |
332 | ZYNQMP_PM_RESET_GPO3_PL_8 = 1089, |
333 | ZYNQMP_PM_RESET_GPO3_PL_9 = 1090, |
334 | ZYNQMP_PM_RESET_GPO3_PL_10 = 1091, |
335 | ZYNQMP_PM_RESET_GPO3_PL_11 = 1092, |
336 | ZYNQMP_PM_RESET_GPO3_PL_12 = 1093, |
337 | ZYNQMP_PM_RESET_GPO3_PL_13 = 1094, |
338 | ZYNQMP_PM_RESET_GPO3_PL_14 = 1095, |
339 | ZYNQMP_PM_RESET_GPO3_PL_15 = 1096, |
340 | ZYNQMP_PM_RESET_GPO3_PL_16 = 1097, |
341 | ZYNQMP_PM_RESET_GPO3_PL_17 = 1098, |
342 | ZYNQMP_PM_RESET_GPO3_PL_18 = 1099, |
343 | ZYNQMP_PM_RESET_GPO3_PL_19 = 1100, |
344 | ZYNQMP_PM_RESET_GPO3_PL_20 = 1101, |
345 | ZYNQMP_PM_RESET_GPO3_PL_21 = 1102, |
346 | ZYNQMP_PM_RESET_GPO3_PL_22 = 1103, |
347 | ZYNQMP_PM_RESET_GPO3_PL_23 = 1104, |
348 | ZYNQMP_PM_RESET_GPO3_PL_24 = 1105, |
349 | ZYNQMP_PM_RESET_GPO3_PL_25 = 1106, |
350 | ZYNQMP_PM_RESET_GPO3_PL_26 = 1107, |
351 | ZYNQMP_PM_RESET_GPO3_PL_27 = 1108, |
352 | ZYNQMP_PM_RESET_GPO3_PL_28 = 1109, |
353 | ZYNQMP_PM_RESET_GPO3_PL_29 = 1110, |
354 | ZYNQMP_PM_RESET_GPO3_PL_30 = 1111, |
355 | ZYNQMP_PM_RESET_GPO3_PL_31 = 1112, |
356 | ZYNQMP_PM_RESET_RPU_LS = 1113, |
357 | ZYNQMP_PM_RESET_PS_ONLY = 1114, |
358 | ZYNQMP_PM_RESET_PL = 1115, |
359 | ZYNQMP_PM_RESET_PS_PL0 = 1116, |
360 | ZYNQMP_PM_RESET_PS_PL1 = 1117, |
361 | ZYNQMP_PM_RESET_PS_PL2 = 1118, |
362 | ZYNQMP_PM_RESET_PS_PL3 = 1119, |
363 | ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3 |
364 | }; |
365 | |
366 | enum zynqmp_pm_suspend_reason { |
367 | SUSPEND_POWER_REQUEST = 201, |
368 | SUSPEND_ALERT = 202, |
369 | SUSPEND_SYSTEM_SHUTDOWN = 203, |
370 | }; |
371 | |
372 | enum zynqmp_pm_request_ack { |
373 | ZYNQMP_PM_REQUEST_ACK_NO = 1, |
374 | ZYNQMP_PM_REQUEST_ACK_BLOCKING = 2, |
375 | ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING = 3, |
376 | }; |
377 | |
378 | enum pm_node_id { |
379 | NODE_SD_0 = 39, |
380 | NODE_SD_1 = 40, |
381 | }; |
382 | |
383 | enum tap_delay_type { |
384 | PM_TAPDELAY_INPUT = 0, |
385 | PM_TAPDELAY_OUTPUT = 1, |
386 | }; |
387 | |
388 | enum dll_reset_type { |
389 | PM_DLL_RESET_ASSERT = 0, |
390 | PM_DLL_RESET_RELEASE = 1, |
391 | PM_DLL_RESET_PULSE = 2, |
392 | }; |
393 | |
394 | enum pm_pinctrl_config_param { |
395 | PM_PINCTRL_CONFIG_SLEW_RATE = 0, |
396 | PM_PINCTRL_CONFIG_BIAS_STATUS = 1, |
397 | PM_PINCTRL_CONFIG_PULL_CTRL = 2, |
398 | PM_PINCTRL_CONFIG_SCHMITT_CMOS = 3, |
399 | PM_PINCTRL_CONFIG_DRIVE_STRENGTH = 4, |
400 | PM_PINCTRL_CONFIG_VOLTAGE_STATUS = 5, |
401 | PM_PINCTRL_CONFIG_TRI_STATE = 6, |
402 | PM_PINCTRL_CONFIG_MAX = 7, |
403 | }; |
404 | |
405 | enum pm_pinctrl_slew_rate { |
406 | PM_PINCTRL_SLEW_RATE_FAST = 0, |
407 | PM_PINCTRL_SLEW_RATE_SLOW = 1, |
408 | }; |
409 | |
410 | enum pm_pinctrl_bias_status { |
411 | PM_PINCTRL_BIAS_DISABLE = 0, |
412 | PM_PINCTRL_BIAS_ENABLE = 1, |
413 | }; |
414 | |
415 | enum pm_pinctrl_pull_ctrl { |
416 | PM_PINCTRL_BIAS_PULL_DOWN = 0, |
417 | PM_PINCTRL_BIAS_PULL_UP = 1, |
418 | }; |
419 | |
420 | enum pm_pinctrl_schmitt_cmos { |
421 | PM_PINCTRL_INPUT_TYPE_CMOS = 0, |
422 | PM_PINCTRL_INPUT_TYPE_SCHMITT = 1, |
423 | }; |
424 | |
425 | enum pm_pinctrl_drive_strength { |
426 | PM_PINCTRL_DRIVE_STRENGTH_2MA = 0, |
427 | PM_PINCTRL_DRIVE_STRENGTH_4MA = 1, |
428 | PM_PINCTRL_DRIVE_STRENGTH_8MA = 2, |
429 | PM_PINCTRL_DRIVE_STRENGTH_12MA = 3, |
430 | }; |
431 | |
432 | enum pm_pinctrl_tri_state { |
433 | PM_PINCTRL_TRI_STATE_DISABLE = 0, |
434 | PM_PINCTRL_TRI_STATE_ENABLE = 1, |
435 | }; |
436 | |
437 | enum zynqmp_pm_shutdown_type { |
438 | ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN = 0, |
439 | ZYNQMP_PM_SHUTDOWN_TYPE_RESET = 1, |
440 | ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY = 2, |
441 | }; |
442 | |
443 | enum zynqmp_pm_shutdown_subtype { |
444 | ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM = 0, |
445 | ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY = 1, |
446 | ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM = 2, |
447 | }; |
448 | |
449 | enum tap_delay_signal_type { |
450 | PM_TAPDELAY_NAND_DQS_IN = 0, |
451 | PM_TAPDELAY_NAND_DQS_OUT = 1, |
452 | PM_TAPDELAY_QSPI = 2, |
453 | PM_TAPDELAY_MAX = 3, |
454 | }; |
455 | |
456 | enum tap_delay_bypass_ctrl { |
457 | PM_TAPDELAY_BYPASS_DISABLE = 0, |
458 | PM_TAPDELAY_BYPASS_ENABLE = 1, |
459 | }; |
460 | |
461 | enum ospi_mux_select_type { |
462 | PM_OSPI_MUX_SEL_DMA = 0, |
463 | PM_OSPI_MUX_SEL_LINEAR = 1, |
464 | }; |
465 | |
466 | enum pm_feature_config_id { |
467 | PM_FEATURE_INVALID = 0, |
468 | PM_FEATURE_OVERTEMP_STATUS = 1, |
469 | PM_FEATURE_OVERTEMP_VALUE = 2, |
470 | PM_FEATURE_EXTWDT_STATUS = 3, |
471 | PM_FEATURE_EXTWDT_VALUE = 4, |
472 | }; |
473 | |
474 | /** |
475 | * enum pm_sd_config_type - PM SD configuration. |
476 | * @SD_CONFIG_EMMC_SEL: To set SD_EMMC_SEL in CTRL_REG_SD and SD_SLOTTYPE |
477 | * @SD_CONFIG_BASECLK: To set SD_BASECLK in SD_CONFIG_REG1 |
478 | * @SD_CONFIG_8BIT: To set SD_8BIT in SD_CONFIG_REG2 |
479 | * @SD_CONFIG_FIXED: To set fixed config registers |
480 | */ |
481 | enum pm_sd_config_type { |
482 | SD_CONFIG_EMMC_SEL = 1, |
483 | SD_CONFIG_BASECLK = 2, |
484 | SD_CONFIG_8BIT = 3, |
485 | SD_CONFIG_FIXED = 4, |
486 | }; |
487 | |
488 | /** |
489 | * enum pm_gem_config_type - PM GEM configuration. |
490 | * @GEM_CONFIG_SGMII_MODE: To set GEM_SGMII_MODE in GEM_CLK_CTRL register |
491 | * @GEM_CONFIG_FIXED: To set fixed config registers |
492 | */ |
493 | enum pm_gem_config_type { |
494 | GEM_CONFIG_SGMII_MODE = 1, |
495 | GEM_CONFIG_FIXED = 2, |
496 | }; |
497 | |
498 | /** |
499 | * struct zynqmp_pm_query_data - PM query data |
500 | * @qid: query ID |
501 | * @arg1: Argument 1 of query data |
502 | * @arg2: Argument 2 of query data |
503 | * @arg3: Argument 3 of query data |
504 | */ |
505 | struct zynqmp_pm_query_data { |
506 | u32 qid; |
507 | u32 arg1; |
508 | u32 arg2; |
509 | u32 arg3; |
510 | }; |
511 | |
512 | int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1, |
513 | u32 arg2, u32 arg3, u32 *ret_payload); |
514 | |
515 | #if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE) |
516 | int zynqmp_pm_get_api_version(u32 *version); |
517 | int zynqmp_pm_get_chipid(u32 *idcode, u32 *version); |
518 | int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out); |
519 | int zynqmp_pm_clock_enable(u32 clock_id); |
520 | int zynqmp_pm_clock_disable(u32 clock_id); |
521 | int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state); |
522 | int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider); |
523 | int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider); |
524 | int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate); |
525 | int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate); |
526 | int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id); |
527 | int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id); |
528 | int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode); |
529 | int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode); |
530 | int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data); |
531 | int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data); |
532 | int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value); |
533 | int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type); |
534 | int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select); |
535 | int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset, |
536 | const enum zynqmp_pm_reset_action assert_flag); |
537 | int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status); |
538 | unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode); |
539 | int zynqmp_pm_bootmode_write(u32 ps_mode); |
540 | int zynqmp_pm_init_finalize(void); |
541 | int zynqmp_pm_set_suspend_mode(u32 mode); |
542 | int zynqmp_pm_request_node(const u32 node, const u32 capabilities, |
543 | const u32 qos, const enum zynqmp_pm_request_ack ack); |
544 | int zynqmp_pm_release_node(const u32 node); |
545 | int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities, |
546 | const u32 qos, |
547 | const enum zynqmp_pm_request_ack ack); |
548 | int zynqmp_pm_aes_engine(const u64 address, u32 *out); |
549 | int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags); |
550 | int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags); |
551 | int zynqmp_pm_fpga_get_status(u32 *value); |
552 | int zynqmp_pm_fpga_get_config_status(u32 *value); |
553 | int zynqmp_pm_write_ggs(u32 index, u32 value); |
554 | int zynqmp_pm_read_ggs(u32 index, u32 *value); |
555 | int zynqmp_pm_write_pggs(u32 index, u32 value); |
556 | int zynqmp_pm_read_pggs(u32 index, u32 *value); |
557 | int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value); |
558 | int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype); |
559 | int zynqmp_pm_set_boot_health_status(u32 value); |
560 | int zynqmp_pm_pinctrl_request(const u32 pin); |
561 | int zynqmp_pm_pinctrl_release(const u32 pin); |
562 | int zynqmp_pm_pinctrl_get_function(const u32 pin, u32 *id); |
563 | int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id); |
564 | int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param, |
565 | u32 *value); |
566 | int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param, |
567 | u32 value); |
568 | int zynqmp_pm_load_pdi(const u32 src, const u64 address); |
569 | int zynqmp_pm_register_notifier(const u32 node, const u32 event, |
570 | const u32 wake, const u32 enable); |
571 | int zynqmp_pm_feature(const u32 api_id); |
572 | int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id); |
573 | int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, u32 value); |
574 | int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, u32 *payload); |
575 | int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset); |
576 | int zynqmp_pm_force_pwrdwn(const u32 target, |
577 | const enum zynqmp_pm_request_ack ack); |
578 | int zynqmp_pm_request_wake(const u32 node, |
579 | const bool set_addr, |
580 | const u64 address, |
581 | const enum zynqmp_pm_request_ack ack); |
582 | int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode); |
583 | int zynqmp_pm_set_rpu_mode(u32 node_id, enum rpu_oper_mode rpu_mode); |
584 | int zynqmp_pm_set_tcm_config(u32 node_id, enum rpu_tcm_comb tcm_mode); |
585 | int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value); |
586 | int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config, |
587 | u32 value); |
588 | #else |
589 | static inline int zynqmp_pm_get_api_version(u32 *version) |
590 | { |
591 | return -ENODEV; |
592 | } |
593 | |
594 | static inline int zynqmp_pm_get_chipid(u32 *idcode, u32 *version) |
595 | { |
596 | return -ENODEV; |
597 | } |
598 | |
599 | static inline int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, |
600 | u32 *out) |
601 | { |
602 | return -ENODEV; |
603 | } |
604 | |
605 | static inline int zynqmp_pm_clock_enable(u32 clock_id) |
606 | { |
607 | return -ENODEV; |
608 | } |
609 | |
610 | static inline int zynqmp_pm_clock_disable(u32 clock_id) |
611 | { |
612 | return -ENODEV; |
613 | } |
614 | |
615 | static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state) |
616 | { |
617 | return -ENODEV; |
618 | } |
619 | |
620 | static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider) |
621 | { |
622 | return -ENODEV; |
623 | } |
624 | |
625 | static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider) |
626 | { |
627 | return -ENODEV; |
628 | } |
629 | |
630 | static inline int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate) |
631 | { |
632 | return -ENODEV; |
633 | } |
634 | |
635 | static inline int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate) |
636 | { |
637 | return -ENODEV; |
638 | } |
639 | |
640 | static inline int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id) |
641 | { |
642 | return -ENODEV; |
643 | } |
644 | |
645 | static inline int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id) |
646 | { |
647 | return -ENODEV; |
648 | } |
649 | |
650 | static inline int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode) |
651 | { |
652 | return -ENODEV; |
653 | } |
654 | |
655 | static inline int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode) |
656 | { |
657 | return -ENODEV; |
658 | } |
659 | |
660 | static inline int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data) |
661 | { |
662 | return -ENODEV; |
663 | } |
664 | |
665 | static inline int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data) |
666 | { |
667 | return -ENODEV; |
668 | } |
669 | |
670 | static inline int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value) |
671 | { |
672 | return -ENODEV; |
673 | } |
674 | |
675 | static inline int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type) |
676 | { |
677 | return -ENODEV; |
678 | } |
679 | |
680 | static inline int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select) |
681 | { |
682 | return -ENODEV; |
683 | } |
684 | |
685 | static inline int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset, |
686 | const enum zynqmp_pm_reset_action assert_flag) |
687 | { |
688 | return -ENODEV; |
689 | } |
690 | |
691 | static inline int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, |
692 | u32 *status) |
693 | { |
694 | return -ENODEV; |
695 | } |
696 | |
697 | static inline unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode) |
698 | { |
699 | return -ENODEV; |
700 | } |
701 | |
702 | static inline int zynqmp_pm_bootmode_write(u32 ps_mode) |
703 | { |
704 | return -ENODEV; |
705 | } |
706 | |
707 | static inline int zynqmp_pm_init_finalize(void) |
708 | { |
709 | return -ENODEV; |
710 | } |
711 | |
712 | static inline int zynqmp_pm_set_suspend_mode(u32 mode) |
713 | { |
714 | return -ENODEV; |
715 | } |
716 | |
717 | static inline int zynqmp_pm_request_node(const u32 node, const u32 capabilities, |
718 | const u32 qos, |
719 | const enum zynqmp_pm_request_ack ack) |
720 | { |
721 | return -ENODEV; |
722 | } |
723 | |
724 | static inline int zynqmp_pm_release_node(const u32 node) |
725 | { |
726 | return -ENODEV; |
727 | } |
728 | |
729 | static inline int zynqmp_pm_set_requirement(const u32 node, |
730 | const u32 capabilities, |
731 | const u32 qos, |
732 | const enum zynqmp_pm_request_ack ack) |
733 | { |
734 | return -ENODEV; |
735 | } |
736 | |
737 | static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out) |
738 | { |
739 | return -ENODEV; |
740 | } |
741 | |
742 | static inline int zynqmp_pm_sha_hash(const u64 address, const u32 size, |
743 | const u32 flags) |
744 | { |
745 | return -ENODEV; |
746 | } |
747 | |
748 | static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size, |
749 | const u32 flags) |
750 | { |
751 | return -ENODEV; |
752 | } |
753 | |
754 | static inline int zynqmp_pm_fpga_get_status(u32 *value) |
755 | { |
756 | return -ENODEV; |
757 | } |
758 | |
759 | static inline int zynqmp_pm_fpga_get_config_status(u32 *value) |
760 | { |
761 | return -ENODEV; |
762 | } |
763 | |
764 | static inline int zynqmp_pm_write_ggs(u32 index, u32 value) |
765 | { |
766 | return -ENODEV; |
767 | } |
768 | |
769 | static inline int zynqmp_pm_read_ggs(u32 index, u32 *value) |
770 | { |
771 | return -ENODEV; |
772 | } |
773 | |
774 | static inline int zynqmp_pm_write_pggs(u32 index, u32 value) |
775 | { |
776 | return -ENODEV; |
777 | } |
778 | |
779 | static inline int zynqmp_pm_read_pggs(u32 index, u32 *value) |
780 | { |
781 | return -ENODEV; |
782 | } |
783 | |
784 | static inline int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value) |
785 | { |
786 | return -ENODEV; |
787 | } |
788 | |
789 | static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype) |
790 | { |
791 | return -ENODEV; |
792 | } |
793 | |
794 | static inline int zynqmp_pm_set_boot_health_status(u32 value) |
795 | { |
796 | return -ENODEV; |
797 | } |
798 | |
799 | static inline int zynqmp_pm_pinctrl_request(const u32 pin) |
800 | { |
801 | return -ENODEV; |
802 | } |
803 | |
804 | static inline int zynqmp_pm_pinctrl_release(const u32 pin) |
805 | { |
806 | return -ENODEV; |
807 | } |
808 | |
809 | static inline int zynqmp_pm_pinctrl_get_function(const u32 pin, u32 *id) |
810 | { |
811 | return -ENODEV; |
812 | } |
813 | |
814 | static inline int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id) |
815 | { |
816 | return -ENODEV; |
817 | } |
818 | |
819 | static inline int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id) |
820 | { |
821 | return -ENODEV; |
822 | } |
823 | |
824 | static inline int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param, |
825 | u32 *value) |
826 | { |
827 | return -ENODEV; |
828 | } |
829 | |
830 | static inline int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param, |
831 | u32 value) |
832 | { |
833 | return -ENODEV; |
834 | } |
835 | |
836 | static inline int zynqmp_pm_load_pdi(const u32 src, const u64 address) |
837 | { |
838 | return -ENODEV; |
839 | } |
840 | |
841 | static inline int zynqmp_pm_register_notifier(const u32 node, const u32 event, |
842 | const u32 wake, const u32 enable) |
843 | { |
844 | return -ENODEV; |
845 | } |
846 | |
847 | static inline int zynqmp_pm_feature(const u32 api_id) |
848 | { |
849 | return -ENODEV; |
850 | } |
851 | |
852 | static inline int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, |
853 | u32 value) |
854 | { |
855 | return -ENODEV; |
856 | } |
857 | |
858 | static inline int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, |
859 | u32 *payload) |
860 | { |
861 | return -ENODEV; |
862 | } |
863 | |
864 | static inline int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset) |
865 | { |
866 | return -ENODEV; |
867 | } |
868 | |
869 | static inline int zynqmp_pm_force_pwrdwn(const u32 target, |
870 | const enum zynqmp_pm_request_ack ack) |
871 | { |
872 | return -ENODEV; |
873 | } |
874 | |
875 | static inline int zynqmp_pm_request_wake(const u32 node, |
876 | const bool set_addr, |
877 | const u64 address, |
878 | const enum zynqmp_pm_request_ack ack) |
879 | { |
880 | return -ENODEV; |
881 | } |
882 | |
883 | static inline int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode) |
884 | { |
885 | return -ENODEV; |
886 | } |
887 | |
888 | static inline int zynqmp_pm_set_rpu_mode(u32 node_id, enum rpu_oper_mode rpu_mode) |
889 | { |
890 | return -ENODEV; |
891 | } |
892 | |
893 | static inline int zynqmp_pm_set_tcm_config(u32 node_id, enum rpu_tcm_comb tcm_mode) |
894 | { |
895 | return -ENODEV; |
896 | } |
897 | |
898 | static inline int zynqmp_pm_set_sd_config(u32 node, |
899 | enum pm_sd_config_type config, |
900 | u32 value) |
901 | { |
902 | return -ENODEV; |
903 | } |
904 | |
905 | static inline int zynqmp_pm_set_gem_config(u32 node, |
906 | enum pm_gem_config_type config, |
907 | u32 value) |
908 | { |
909 | return -ENODEV; |
910 | } |
911 | |
912 | #endif |
913 | |
914 | #endif /* __FIRMWARE_ZYNQMP_H__ */ |
915 | |