1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6#ifndef __LINUX_IRQCHIP_ARM_GIC_V3_H
7#define __LINUX_IRQCHIP_ARM_GIC_V3_H
8
9/*
10 * Distributor registers. We assume we're running non-secure, with ARE
11 * being set. Secure-only and non-ARE registers are not described.
12 */
13#define GICD_CTLR 0x0000
14#define GICD_TYPER 0x0004
15#define GICD_IIDR 0x0008
16#define GICD_TYPER2 0x000C
17#define GICD_STATUSR 0x0010
18#define GICD_SETSPI_NSR 0x0040
19#define GICD_CLRSPI_NSR 0x0048
20#define GICD_SETSPI_SR 0x0050
21#define GICD_CLRSPI_SR 0x0058
22#define GICD_IGROUPR 0x0080
23#define GICD_ISENABLER 0x0100
24#define GICD_ICENABLER 0x0180
25#define GICD_ISPENDR 0x0200
26#define GICD_ICPENDR 0x0280
27#define GICD_ISACTIVER 0x0300
28#define GICD_ICACTIVER 0x0380
29#define GICD_IPRIORITYR 0x0400
30#define GICD_ICFGR 0x0C00
31#define GICD_IGRPMODR 0x0D00
32#define GICD_NSACR 0x0E00
33#define GICD_IGROUPRnE 0x1000
34#define GICD_ISENABLERnE 0x1200
35#define GICD_ICENABLERnE 0x1400
36#define GICD_ISPENDRnE 0x1600
37#define GICD_ICPENDRnE 0x1800
38#define GICD_ISACTIVERnE 0x1A00
39#define GICD_ICACTIVERnE 0x1C00
40#define GICD_IPRIORITYRnE 0x2000
41#define GICD_ICFGRnE 0x3000
42#define GICD_IROUTER 0x6000
43#define GICD_IROUTERnE 0x8000
44#define GICD_IDREGS 0xFFD0
45#define GICD_PIDR2 0xFFE8
46
47#define ESPI_BASE_INTID 4096
48
49/*
50 * Those registers are actually from GICv2, but the spec demands that they
51 * are implemented as RES0 if ARE is 1 (which we do in KVM's emulated GICv3).
52 */
53#define GICD_ITARGETSR 0x0800
54#define GICD_SGIR 0x0F00
55#define GICD_CPENDSGIR 0x0F10
56#define GICD_SPENDSGIR 0x0F20
57
58#define GICD_CTLR_RWP (1U << 31)
59#define GICD_CTLR_nASSGIreq (1U << 8)
60#define GICD_CTLR_DS (1U << 6)
61#define GICD_CTLR_ARE_NS (1U << 4)
62#define GICD_CTLR_ENABLE_G1A (1U << 1)
63#define GICD_CTLR_ENABLE_G1 (1U << 0)
64
65#define GICD_IIDR_IMPLEMENTER_SHIFT 0
66#define GICD_IIDR_IMPLEMENTER_MASK (0xfff << GICD_IIDR_IMPLEMENTER_SHIFT)
67#define GICD_IIDR_REVISION_SHIFT 12
68#define GICD_IIDR_REVISION_MASK (0xf << GICD_IIDR_REVISION_SHIFT)
69#define GICD_IIDR_VARIANT_SHIFT 16
70#define GICD_IIDR_VARIANT_MASK (0xf << GICD_IIDR_VARIANT_SHIFT)
71#define GICD_IIDR_PRODUCT_ID_SHIFT 24
72#define GICD_IIDR_PRODUCT_ID_MASK (0xff << GICD_IIDR_PRODUCT_ID_SHIFT)
73
74
75/*
76 * In systems with a single security state (what we emulate in KVM)
77 * the meaning of the interrupt group enable bits is slightly different
78 */
79#define GICD_CTLR_ENABLE_SS_G1 (1U << 1)
80#define GICD_CTLR_ENABLE_SS_G0 (1U << 0)
81
82#define GICD_TYPER_RSS (1U << 26)
83#define GICD_TYPER_LPIS (1U << 17)
84#define GICD_TYPER_MBIS (1U << 16)
85#define GICD_TYPER_ESPI (1U << 8)
86
87#define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1)
88#define GICD_TYPER_NUM_LPIS(typer) ((((typer) >> 11) & 0x1f) + 1)
89#define GICD_TYPER_SPIS(typer) ((((typer) & 0x1f) + 1) * 32)
90#define GICD_TYPER_ESPIS(typer) \
91 (((typer) & GICD_TYPER_ESPI) ? GICD_TYPER_SPIS((typer) >> 27) : 0)
92
93#define GICD_TYPER2_nASSGIcap (1U << 8)
94#define GICD_TYPER2_VIL (1U << 7)
95#define GICD_TYPER2_VID GENMASK(4, 0)
96
97#define GICD_IROUTER_SPI_MODE_ONE (0U << 31)
98#define GICD_IROUTER_SPI_MODE_ANY (1U << 31)
99
100#define GIC_PIDR2_ARCH_MASK 0xf0
101#define GIC_PIDR2_ARCH_GICv3 0x30
102#define GIC_PIDR2_ARCH_GICv4 0x40
103
104#define GIC_V3_DIST_SIZE 0x10000
105
106#define GIC_PAGE_SIZE_4K 0ULL
107#define GIC_PAGE_SIZE_16K 1ULL
108#define GIC_PAGE_SIZE_64K 2ULL
109#define GIC_PAGE_SIZE_MASK 3ULL
110
111/*
112 * Re-Distributor registers, offsets from RD_base
113 */
114#define GICR_CTLR GICD_CTLR
115#define GICR_IIDR 0x0004
116#define GICR_TYPER 0x0008
117#define GICR_STATUSR GICD_STATUSR
118#define GICR_WAKER 0x0014
119#define GICR_SETLPIR 0x0040
120#define GICR_CLRLPIR 0x0048
121#define GICR_PROPBASER 0x0070
122#define GICR_PENDBASER 0x0078
123#define GICR_INVLPIR 0x00A0
124#define GICR_INVALLR 0x00B0
125#define GICR_SYNCR 0x00C0
126#define GICR_IDREGS GICD_IDREGS
127#define GICR_PIDR2 GICD_PIDR2
128
129#define GICR_CTLR_ENABLE_LPIS (1UL << 0)
130#define GICR_CTLR_CES (1UL << 1)
131#define GICR_CTLR_IR (1UL << 2)
132#define GICR_CTLR_RWP (1UL << 3)
133
134#define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff)
135
136#define EPPI_BASE_INTID 1056
137
138#define GICR_TYPER_NR_PPIS(r) \
139 ({ \
140 unsigned int __ppinum = ((r) >> 27) & 0x1f; \
141 unsigned int __nr_ppis = 16; \
142 if (__ppinum == 1 || __ppinum == 2) \
143 __nr_ppis += __ppinum * 32; \
144 \
145 __nr_ppis; \
146 })
147
148#define GICR_WAKER_ProcessorSleep (1U << 1)
149#define GICR_WAKER_ChildrenAsleep (1U << 2)
150
151#define GIC_BASER_CACHE_nCnB 0ULL
152#define GIC_BASER_CACHE_SameAsInner 0ULL
153#define GIC_BASER_CACHE_nC 1ULL
154#define GIC_BASER_CACHE_RaWt 2ULL
155#define GIC_BASER_CACHE_RaWb 3ULL
156#define GIC_BASER_CACHE_WaWt 4ULL
157#define GIC_BASER_CACHE_WaWb 5ULL
158#define GIC_BASER_CACHE_RaWaWt 6ULL
159#define GIC_BASER_CACHE_RaWaWb 7ULL
160#define GIC_BASER_CACHE_MASK 7ULL
161#define GIC_BASER_NonShareable 0ULL
162#define GIC_BASER_InnerShareable 1ULL
163#define GIC_BASER_OuterShareable 2ULL
164#define GIC_BASER_SHAREABILITY_MASK 3ULL
165
166#define GIC_BASER_CACHEABILITY(reg, inner_outer, type) \
167 (GIC_BASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT)
168
169#define GIC_BASER_SHAREABILITY(reg, type) \
170 (GIC_BASER_##type << reg##_SHAREABILITY_SHIFT)
171
172/* encode a size field of width @w containing @n - 1 units */
173#define GIC_ENCODE_SZ(n, w) (((unsigned long)(n) - 1) & GENMASK_ULL(((w) - 1), 0))
174
175#define GICR_PROPBASER_SHAREABILITY_SHIFT (10)
176#define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT (7)
177#define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT (56)
178#define GICR_PROPBASER_SHAREABILITY_MASK \
179 GIC_BASER_SHAREABILITY(GICR_PROPBASER, SHAREABILITY_MASK)
180#define GICR_PROPBASER_INNER_CACHEABILITY_MASK \
181 GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, MASK)
182#define GICR_PROPBASER_OUTER_CACHEABILITY_MASK \
183 GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, MASK)
184#define GICR_PROPBASER_CACHEABILITY_MASK GICR_PROPBASER_INNER_CACHEABILITY_MASK
185
186#define GICR_PROPBASER_InnerShareable \
187 GIC_BASER_SHAREABILITY(GICR_PROPBASER, InnerShareable)
188
189#define GICR_PROPBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nCnB)
190#define GICR_PROPBASER_nC GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nC)
191#define GICR_PROPBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWt)
192#define GICR_PROPBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWb)
193#define GICR_PROPBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWt)
194#define GICR_PROPBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWb)
195#define GICR_PROPBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWt)
196#define GICR_PROPBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWb)
197
198#define GICR_PROPBASER_IDBITS_MASK (0x1f)
199#define GICR_PROPBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 12))
200#define GICR_PENDBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 16))
201
202#define GICR_PENDBASER_SHAREABILITY_SHIFT (10)
203#define GICR_PENDBASER_INNER_CACHEABILITY_SHIFT (7)
204#define GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT (56)
205#define GICR_PENDBASER_SHAREABILITY_MASK \
206 GIC_BASER_SHAREABILITY(GICR_PENDBASER, SHAREABILITY_MASK)
207#define GICR_PENDBASER_INNER_CACHEABILITY_MASK \
208 GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, MASK)
209#define GICR_PENDBASER_OUTER_CACHEABILITY_MASK \
210 GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, MASK)
211#define GICR_PENDBASER_CACHEABILITY_MASK GICR_PENDBASER_INNER_CACHEABILITY_MASK
212
213#define GICR_PENDBASER_InnerShareable \
214 GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable)
215
216#define GICR_PENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nCnB)
217#define GICR_PENDBASER_nC GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nC)
218#define GICR_PENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWt)
219#define GICR_PENDBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb)
220#define GICR_PENDBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWt)
221#define GICR_PENDBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWb)
222#define GICR_PENDBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWt)
223#define GICR_PENDBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWb)
224
225#define GICR_PENDBASER_PTZ BIT_ULL(62)
226
227/*
228 * Re-Distributor registers, offsets from SGI_base
229 */
230#define GICR_IGROUPR0 GICD_IGROUPR
231#define GICR_ISENABLER0 GICD_ISENABLER
232#define GICR_ICENABLER0 GICD_ICENABLER
233#define GICR_ISPENDR0 GICD_ISPENDR
234#define GICR_ICPENDR0 GICD_ICPENDR
235#define GICR_ISACTIVER0 GICD_ISACTIVER
236#define GICR_ICACTIVER0 GICD_ICACTIVER
237#define GICR_IPRIORITYR0 GICD_IPRIORITYR
238#define GICR_ICFGR0 GICD_ICFGR
239#define GICR_IGRPMODR0 GICD_IGRPMODR
240#define GICR_NSACR GICD_NSACR
241
242#define GICR_TYPER_PLPIS (1U << 0)
243#define GICR_TYPER_VLPIS (1U << 1)
244#define GICR_TYPER_DIRTY (1U << 2)
245#define GICR_TYPER_DirectLPIS (1U << 3)
246#define GICR_TYPER_LAST (1U << 4)
247#define GICR_TYPER_RVPEID (1U << 7)
248#define GICR_TYPER_COMMON_LPI_AFF GENMASK_ULL(25, 24)
249#define GICR_TYPER_AFFINITY GENMASK_ULL(63, 32)
250
251#define GICR_INVLPIR_INTID GENMASK_ULL(31, 0)
252#define GICR_INVLPIR_VPEID GENMASK_ULL(47, 32)
253#define GICR_INVLPIR_V GENMASK_ULL(63, 63)
254
255#define GICR_INVALLR_VPEID GICR_INVLPIR_VPEID
256#define GICR_INVALLR_V GICR_INVLPIR_V
257
258#define GIC_V3_REDIST_SIZE 0x20000
259
260#define LPI_PROP_GROUP1 (1 << 1)
261#define LPI_PROP_ENABLED (1 << 0)
262
263/*
264 * Re-Distributor registers, offsets from VLPI_base
265 */
266#define GICR_VPROPBASER 0x0070
267
268#define GICR_VPROPBASER_IDBITS_MASK 0x1f
269
270#define GICR_VPROPBASER_SHAREABILITY_SHIFT (10)
271#define GICR_VPROPBASER_INNER_CACHEABILITY_SHIFT (7)
272#define GICR_VPROPBASER_OUTER_CACHEABILITY_SHIFT (56)
273
274#define GICR_VPROPBASER_SHAREABILITY_MASK \
275 GIC_BASER_SHAREABILITY(GICR_VPROPBASER, SHAREABILITY_MASK)
276#define GICR_VPROPBASER_INNER_CACHEABILITY_MASK \
277 GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, MASK)
278#define GICR_VPROPBASER_OUTER_CACHEABILITY_MASK \
279 GIC_BASER_CACHEABILITY(GICR_VPROPBASER, OUTER, MASK)
280#define GICR_VPROPBASER_CACHEABILITY_MASK \
281 GICR_VPROPBASER_INNER_CACHEABILITY_MASK
282
283#define GICR_VPROPBASER_InnerShareable \
284 GIC_BASER_SHAREABILITY(GICR_VPROPBASER, InnerShareable)
285
286#define GICR_VPROPBASER_nCnB GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, nCnB)
287#define GICR_VPROPBASER_nC GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, nC)
288#define GICR_VPROPBASER_RaWt GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWt)
289#define GICR_VPROPBASER_RaWb GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWb)
290#define GICR_VPROPBASER_WaWt GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, WaWt)
291#define GICR_VPROPBASER_WaWb GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, WaWb)
292#define GICR_VPROPBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWaWt)
293#define GICR_VPROPBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWaWb)
294
295/*
296 * GICv4.1 VPROPBASER reinvention. A subtle mix between the old
297 * VPROPBASER and ITS_BASER. Just not quite any of the two.
298 */
299#define GICR_VPROPBASER_4_1_VALID (1ULL << 63)
300#define GICR_VPROPBASER_4_1_ENTRY_SIZE GENMASK_ULL(61, 59)
301#define GICR_VPROPBASER_4_1_INDIRECT (1ULL << 55)
302#define GICR_VPROPBASER_4_1_PAGE_SIZE GENMASK_ULL(54, 53)
303#define GICR_VPROPBASER_4_1_Z (1ULL << 52)
304#define GICR_VPROPBASER_4_1_ADDR GENMASK_ULL(51, 12)
305#define GICR_VPROPBASER_4_1_SIZE GENMASK_ULL(6, 0)
306
307#define GICR_VPENDBASER 0x0078
308
309#define GICR_VPENDBASER_SHAREABILITY_SHIFT (10)
310#define GICR_VPENDBASER_INNER_CACHEABILITY_SHIFT (7)
311#define GICR_VPENDBASER_OUTER_CACHEABILITY_SHIFT (56)
312#define GICR_VPENDBASER_SHAREABILITY_MASK \
313 GIC_BASER_SHAREABILITY(GICR_VPENDBASER, SHAREABILITY_MASK)
314#define GICR_VPENDBASER_INNER_CACHEABILITY_MASK \
315 GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, MASK)
316#define GICR_VPENDBASER_OUTER_CACHEABILITY_MASK \
317 GIC_BASER_CACHEABILITY(GICR_VPENDBASER, OUTER, MASK)
318#define GICR_VPENDBASER_CACHEABILITY_MASK \
319 GICR_VPENDBASER_INNER_CACHEABILITY_MASK
320
321#define GICR_VPENDBASER_NonShareable \
322 GIC_BASER_SHAREABILITY(GICR_VPENDBASER, NonShareable)
323
324#define GICR_VPENDBASER_InnerShareable \
325 GIC_BASER_SHAREABILITY(GICR_VPENDBASER, InnerShareable)
326
327#define GICR_VPENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nCnB)
328#define GICR_VPENDBASER_nC GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nC)
329#define GICR_VPENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWt)
330#define GICR_VPENDBASER_RaWb GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWb)
331#define GICR_VPENDBASER_WaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, WaWt)
332#define GICR_VPENDBASER_WaWb GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, WaWb)
333#define GICR_VPENDBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWaWt)
334#define GICR_VPENDBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWaWb)
335
336#define GICR_VPENDBASER_Dirty (1ULL << 60)
337#define GICR_VPENDBASER_PendingLast (1ULL << 61)
338#define GICR_VPENDBASER_IDAI (1ULL << 62)
339#define GICR_VPENDBASER_Valid (1ULL << 63)
340
341/*
342 * GICv4.1 VPENDBASER, used for VPE residency. On top of these fields,
343 * also use the above Valid, PendingLast and Dirty.
344 */
345#define GICR_VPENDBASER_4_1_DB (1ULL << 62)
346#define GICR_VPENDBASER_4_1_VGRP0EN (1ULL << 59)
347#define GICR_VPENDBASER_4_1_VGRP1EN (1ULL << 58)
348#define GICR_VPENDBASER_4_1_VPEID GENMASK_ULL(15, 0)
349
350#define GICR_VSGIR 0x0080
351
352#define GICR_VSGIR_VPEID GENMASK(15, 0)
353
354#define GICR_VSGIPENDR 0x0088
355
356#define GICR_VSGIPENDR_BUSY (1U << 31)
357#define GICR_VSGIPENDR_PENDING GENMASK(15, 0)
358
359/*
360 * ITS registers, offsets from ITS_base
361 */
362#define GITS_CTLR 0x0000
363#define GITS_IIDR 0x0004
364#define GITS_TYPER 0x0008
365#define GITS_MPIDR 0x0018
366#define GITS_CBASER 0x0080
367#define GITS_CWRITER 0x0088
368#define GITS_CREADR 0x0090
369#define GITS_BASER 0x0100
370#define GITS_IDREGS_BASE 0xffd0
371#define GITS_PIDR0 0xffe0
372#define GITS_PIDR1 0xffe4
373#define GITS_PIDR2 GICR_PIDR2
374#define GITS_PIDR4 0xffd0
375#define GITS_CIDR0 0xfff0
376#define GITS_CIDR1 0xfff4
377#define GITS_CIDR2 0xfff8
378#define GITS_CIDR3 0xfffc
379
380#define GITS_TRANSLATER 0x10040
381
382#define GITS_SGIR 0x20020
383
384#define GITS_SGIR_VPEID GENMASK_ULL(47, 32)
385#define GITS_SGIR_VINTID GENMASK_ULL(3, 0)
386
387#define GITS_CTLR_ENABLE (1U << 0)
388#define GITS_CTLR_ImDe (1U << 1)
389#define GITS_CTLR_ITS_NUMBER_SHIFT 4
390#define GITS_CTLR_ITS_NUMBER (0xFU << GITS_CTLR_ITS_NUMBER_SHIFT)
391#define GITS_CTLR_QUIESCENT (1U << 31)
392
393#define GITS_TYPER_PLPIS (1UL << 0)
394#define GITS_TYPER_VLPIS (1UL << 1)
395#define GITS_TYPER_ITT_ENTRY_SIZE_SHIFT 4
396#define GITS_TYPER_ITT_ENTRY_SIZE GENMASK_ULL(7, 4)
397#define GITS_TYPER_IDBITS_SHIFT 8
398#define GITS_TYPER_DEVBITS_SHIFT 13
399#define GITS_TYPER_DEVBITS GENMASK_ULL(17, 13)
400#define GITS_TYPER_PTA (1UL << 19)
401#define GITS_TYPER_HCC_SHIFT 24
402#define GITS_TYPER_HCC(r) (((r) >> GITS_TYPER_HCC_SHIFT) & 0xff)
403#define GITS_TYPER_VMOVP (1ULL << 37)
404#define GITS_TYPER_VMAPP (1ULL << 40)
405#define GITS_TYPER_SVPET GENMASK_ULL(42, 41)
406
407#define GITS_IIDR_REV_SHIFT 12
408#define GITS_IIDR_REV_MASK (0xf << GITS_IIDR_REV_SHIFT)
409#define GITS_IIDR_REV(r) (((r) >> GITS_IIDR_REV_SHIFT) & 0xf)
410#define GITS_IIDR_PRODUCTID_SHIFT 24
411
412#define GITS_CBASER_VALID (1ULL << 63)
413#define GITS_CBASER_SHAREABILITY_SHIFT (10)
414#define GITS_CBASER_INNER_CACHEABILITY_SHIFT (59)
415#define GITS_CBASER_OUTER_CACHEABILITY_SHIFT (53)
416#define GITS_CBASER_SHAREABILITY_MASK \
417 GIC_BASER_SHAREABILITY(GITS_CBASER, SHAREABILITY_MASK)
418#define GITS_CBASER_INNER_CACHEABILITY_MASK \
419 GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, MASK)
420#define GITS_CBASER_OUTER_CACHEABILITY_MASK \
421 GIC_BASER_CACHEABILITY(GITS_CBASER, OUTER, MASK)
422#define GITS_CBASER_CACHEABILITY_MASK GITS_CBASER_INNER_CACHEABILITY_MASK
423
424#define GITS_CBASER_InnerShareable \
425 GIC_BASER_SHAREABILITY(GITS_CBASER, InnerShareable)
426
427#define GITS_CBASER_nCnB GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nCnB)
428#define GITS_CBASER_nC GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nC)
429#define GITS_CBASER_RaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt)
430#define GITS_CBASER_RaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWb)
431#define GITS_CBASER_WaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWt)
432#define GITS_CBASER_WaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWb)
433#define GITS_CBASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWt)
434#define GITS_CBASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWb)
435
436#define GITS_CBASER_ADDRESS(cbaser) ((cbaser) & GENMASK_ULL(51, 12))
437
438#define GITS_BASER_NR_REGS 8
439
440#define GITS_BASER_VALID (1ULL << 63)
441#define GITS_BASER_INDIRECT (1ULL << 62)
442
443#define GITS_BASER_INNER_CACHEABILITY_SHIFT (59)
444#define GITS_BASER_OUTER_CACHEABILITY_SHIFT (53)
445#define GITS_BASER_INNER_CACHEABILITY_MASK \
446 GIC_BASER_CACHEABILITY(GITS_BASER, INNER, MASK)
447#define GITS_BASER_CACHEABILITY_MASK GITS_BASER_INNER_CACHEABILITY_MASK
448#define GITS_BASER_OUTER_CACHEABILITY_MASK \
449 GIC_BASER_CACHEABILITY(GITS_BASER, OUTER, MASK)
450#define GITS_BASER_SHAREABILITY_MASK \
451 GIC_BASER_SHAREABILITY(GITS_BASER, SHAREABILITY_MASK)
452
453#define GITS_BASER_nCnB GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nCnB)
454#define GITS_BASER_nC GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nC)
455#define GITS_BASER_RaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWt)
456#define GITS_BASER_RaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWb)
457#define GITS_BASER_WaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWt)
458#define GITS_BASER_WaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWb)
459#define GITS_BASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWt)
460#define GITS_BASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWb)
461
462#define GITS_BASER_TYPE_SHIFT (56)
463#define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7)
464#define GITS_BASER_ENTRY_SIZE_SHIFT (48)
465#define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1)
466#define GITS_BASER_ENTRY_SIZE_MASK GENMASK_ULL(52, 48)
467#define GITS_BASER_PHYS_52_to_48(phys) \
468 (((phys) & GENMASK_ULL(47, 16)) | (((phys) >> 48) & 0xf) << 12)
469#define GITS_BASER_ADDR_48_to_52(baser) \
470 (((baser) & GENMASK_ULL(47, 16)) | (((baser) >> 12) & 0xf) << 48)
471
472#define GITS_BASER_SHAREABILITY_SHIFT (10)
473#define GITS_BASER_InnerShareable \
474 GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable)
475#define GITS_BASER_PAGE_SIZE_SHIFT (8)
476#define __GITS_BASER_PSZ(sz) (GIC_PAGE_SIZE_ ## sz << GITS_BASER_PAGE_SIZE_SHIFT)
477#define GITS_BASER_PAGE_SIZE_4K __GITS_BASER_PSZ(4K)
478#define GITS_BASER_PAGE_SIZE_16K __GITS_BASER_PSZ(16K)
479#define GITS_BASER_PAGE_SIZE_64K __GITS_BASER_PSZ(64K)
480#define GITS_BASER_PAGE_SIZE_MASK __GITS_BASER_PSZ(MASK)
481#define GITS_BASER_PAGES_MAX 256
482#define GITS_BASER_PAGES_SHIFT (0)
483#define GITS_BASER_NR_PAGES(r) (((r) & 0xff) + 1)
484
485#define GITS_BASER_TYPE_NONE 0
486#define GITS_BASER_TYPE_DEVICE 1
487#define GITS_BASER_TYPE_VCPU 2
488#define GITS_BASER_TYPE_RESERVED3 3
489#define GITS_BASER_TYPE_COLLECTION 4
490#define GITS_BASER_TYPE_RESERVED5 5
491#define GITS_BASER_TYPE_RESERVED6 6
492#define GITS_BASER_TYPE_RESERVED7 7
493
494#define GITS_LVL1_ENTRY_SIZE (8UL)
495
496/*
497 * ITS commands
498 */
499#define GITS_CMD_MAPD 0x08
500#define GITS_CMD_MAPC 0x09
501#define GITS_CMD_MAPTI 0x0a
502#define GITS_CMD_MAPI 0x0b
503#define GITS_CMD_MOVI 0x01
504#define GITS_CMD_DISCARD 0x0f
505#define GITS_CMD_INV 0x0c
506#define GITS_CMD_MOVALL 0x0e
507#define GITS_CMD_INVALL 0x0d
508#define GITS_CMD_INT 0x03
509#define GITS_CMD_CLEAR 0x04
510#define GITS_CMD_SYNC 0x05
511
512/*
513 * GICv4 ITS specific commands
514 */
515#define GITS_CMD_GICv4(x) ((x) | 0x20)
516#define GITS_CMD_VINVALL GITS_CMD_GICv4(GITS_CMD_INVALL)
517#define GITS_CMD_VMAPP GITS_CMD_GICv4(GITS_CMD_MAPC)
518#define GITS_CMD_VMAPTI GITS_CMD_GICv4(GITS_CMD_MAPTI)
519#define GITS_CMD_VMOVI GITS_CMD_GICv4(GITS_CMD_MOVI)
520#define GITS_CMD_VSYNC GITS_CMD_GICv4(GITS_CMD_SYNC)
521/* VMOVP, VSGI and INVDB are the odd ones, as they dont have a physical counterpart */
522#define GITS_CMD_VMOVP GITS_CMD_GICv4(2)
523#define GITS_CMD_VSGI GITS_CMD_GICv4(3)
524#define GITS_CMD_INVDB GITS_CMD_GICv4(0xe)
525
526/*
527 * ITS error numbers
528 */
529#define E_ITS_MOVI_UNMAPPED_INTERRUPT 0x010107
530#define E_ITS_MOVI_UNMAPPED_COLLECTION 0x010109
531#define E_ITS_INT_UNMAPPED_INTERRUPT 0x010307
532#define E_ITS_CLEAR_UNMAPPED_INTERRUPT 0x010507
533#define E_ITS_MAPD_DEVICE_OOR 0x010801
534#define E_ITS_MAPD_ITTSIZE_OOR 0x010802
535#define E_ITS_MAPC_PROCNUM_OOR 0x010902
536#define E_ITS_MAPC_COLLECTION_OOR 0x010903
537#define E_ITS_MAPTI_UNMAPPED_DEVICE 0x010a04
538#define E_ITS_MAPTI_ID_OOR 0x010a05
539#define E_ITS_MAPTI_PHYSICALID_OOR 0x010a06
540#define E_ITS_INV_UNMAPPED_INTERRUPT 0x010c07
541#define E_ITS_INVALL_UNMAPPED_COLLECTION 0x010d09
542#define E_ITS_MOVALL_PROCNUM_OOR 0x010e01
543#define E_ITS_DISCARD_UNMAPPED_INTERRUPT 0x010f07
544
545/*
546 * CPU interface registers
547 */
548#define ICC_CTLR_EL1_EOImode_SHIFT (1)
549#define ICC_CTLR_EL1_EOImode_drop_dir (0U << ICC_CTLR_EL1_EOImode_SHIFT)
550#define ICC_CTLR_EL1_EOImode_drop (1U << ICC_CTLR_EL1_EOImode_SHIFT)
551#define ICC_CTLR_EL1_EOImode_MASK (1 << ICC_CTLR_EL1_EOImode_SHIFT)
552#define ICC_CTLR_EL1_CBPR_SHIFT 0
553#define ICC_CTLR_EL1_CBPR_MASK (1 << ICC_CTLR_EL1_CBPR_SHIFT)
554#define ICC_CTLR_EL1_PMHE_SHIFT 6
555#define ICC_CTLR_EL1_PMHE_MASK (1 << ICC_CTLR_EL1_PMHE_SHIFT)
556#define ICC_CTLR_EL1_PRI_BITS_SHIFT 8
557#define ICC_CTLR_EL1_PRI_BITS_MASK (0x7 << ICC_CTLR_EL1_PRI_BITS_SHIFT)
558#define ICC_CTLR_EL1_ID_BITS_SHIFT 11
559#define ICC_CTLR_EL1_ID_BITS_MASK (0x7 << ICC_CTLR_EL1_ID_BITS_SHIFT)
560#define ICC_CTLR_EL1_SEIS_SHIFT 14
561#define ICC_CTLR_EL1_SEIS_MASK (0x1 << ICC_CTLR_EL1_SEIS_SHIFT)
562#define ICC_CTLR_EL1_A3V_SHIFT 15
563#define ICC_CTLR_EL1_A3V_MASK (0x1 << ICC_CTLR_EL1_A3V_SHIFT)
564#define ICC_CTLR_EL1_RSS (0x1 << 18)
565#define ICC_CTLR_EL1_ExtRange (0x1 << 19)
566#define ICC_PMR_EL1_SHIFT 0
567#define ICC_PMR_EL1_MASK (0xff << ICC_PMR_EL1_SHIFT)
568#define ICC_BPR0_EL1_SHIFT 0
569#define ICC_BPR0_EL1_MASK (0x7 << ICC_BPR0_EL1_SHIFT)
570#define ICC_BPR1_EL1_SHIFT 0
571#define ICC_BPR1_EL1_MASK (0x7 << ICC_BPR1_EL1_SHIFT)
572#define ICC_IGRPEN0_EL1_SHIFT 0
573#define ICC_IGRPEN0_EL1_MASK (1 << ICC_IGRPEN0_EL1_SHIFT)
574#define ICC_IGRPEN1_EL1_SHIFT 0
575#define ICC_IGRPEN1_EL1_MASK (1 << ICC_IGRPEN1_EL1_SHIFT)
576#define ICC_SRE_EL1_DIB (1U << 2)
577#define ICC_SRE_EL1_DFB (1U << 1)
578#define ICC_SRE_EL1_SRE (1U << 0)
579
580/* These are for GICv2 emulation only */
581#define GICH_LR_VIRTUALID (0x3ffUL << 0)
582#define GICH_LR_PHYSID_CPUID_SHIFT (10)
583#define GICH_LR_PHYSID_CPUID (7UL << GICH_LR_PHYSID_CPUID_SHIFT)
584
585#define ICC_IAR1_EL1_SPURIOUS 0x3ff
586
587#define ICC_SRE_EL2_SRE (1 << 0)
588#define ICC_SRE_EL2_ENABLE (1 << 3)
589
590#define ICC_SGI1R_TARGET_LIST_SHIFT 0
591#define ICC_SGI1R_TARGET_LIST_MASK (0xffff << ICC_SGI1R_TARGET_LIST_SHIFT)
592#define ICC_SGI1R_AFFINITY_1_SHIFT 16
593#define ICC_SGI1R_AFFINITY_1_MASK (0xff << ICC_SGI1R_AFFINITY_1_SHIFT)
594#define ICC_SGI1R_SGI_ID_SHIFT 24
595#define ICC_SGI1R_SGI_ID_MASK (0xfULL << ICC_SGI1R_SGI_ID_SHIFT)
596#define ICC_SGI1R_AFFINITY_2_SHIFT 32
597#define ICC_SGI1R_AFFINITY_2_MASK (0xffULL << ICC_SGI1R_AFFINITY_2_SHIFT)
598#define ICC_SGI1R_IRQ_ROUTING_MODE_BIT 40
599#define ICC_SGI1R_RS_SHIFT 44
600#define ICC_SGI1R_RS_MASK (0xfULL << ICC_SGI1R_RS_SHIFT)
601#define ICC_SGI1R_AFFINITY_3_SHIFT 48
602#define ICC_SGI1R_AFFINITY_3_MASK (0xffULL << ICC_SGI1R_AFFINITY_3_SHIFT)
603
604#include <asm/arch_gicv3.h>
605
606#ifndef __ASSEMBLY__
607
608/*
609 * We need a value to serve as a irq-type for LPIs. Choose one that will
610 * hopefully pique the interest of the reviewer.
611 */
612#define GIC_IRQ_TYPE_LPI 0xa110c8ed
613
614struct rdists {
615 struct {
616 raw_spinlock_t rd_lock;
617 void __iomem *rd_base;
618 struct page *pend_page;
619 phys_addr_t phys_base;
620 u64 flags;
621 cpumask_t *vpe_table_mask;
622 void *vpe_l1_base;
623 } __percpu *rdist;
624 phys_addr_t prop_table_pa;
625 void *prop_table_va;
626 u64 flags;
627 u32 gicd_typer;
628 u32 gicd_typer2;
629 int cpuhp_memreserve_state;
630 bool has_vlpis;
631 bool has_rvpeid;
632 bool has_direct_lpi;
633 bool has_vpend_valid_dirty;
634};
635
636struct irq_domain;
637struct fwnode_handle;
638int __init its_lpi_memreserve_init(void);
639int its_cpu_init(void);
640int its_init(struct fwnode_handle *handle, struct rdists *rdists,
641 struct irq_domain *domain);
642int mbi_init(struct fwnode_handle *fwnode, struct irq_domain *parent);
643
644static inline bool gic_enable_sre(void)
645{
646 u32 val;
647
648 val = gic_read_sre();
649 if (val & ICC_SRE_EL1_SRE)
650 return true;
651
652 val |= ICC_SRE_EL1_SRE;
653 gic_write_sre(val);
654 val = gic_read_sre();
655
656 return !!(val & ICC_SRE_EL1_SRE);
657}
658
659#endif
660
661#endif
662

source code of linux/include/linux/irqchip/arm-gic-v3.h