1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef NVM_H
3#define NVM_H
4
5#include <linux/blkdev.h>
6#include <linux/types.h>
7#include <uapi/linux/lightnvm.h>
8
9enum {
10 NVM_IO_OK = 0,
11 NVM_IO_REQUEUE = 1,
12 NVM_IO_DONE = 2,
13 NVM_IO_ERR = 3,
14
15 NVM_IOTYPE_NONE = 0,
16 NVM_IOTYPE_GC = 1,
17};
18
19/* common format */
20#define NVM_GEN_CH_BITS (8)
21#define NVM_GEN_LUN_BITS (8)
22#define NVM_GEN_BLK_BITS (16)
23#define NVM_GEN_RESERVED (32)
24
25/* 1.2 format */
26#define NVM_12_PG_BITS (16)
27#define NVM_12_PL_BITS (4)
28#define NVM_12_SEC_BITS (4)
29#define NVM_12_RESERVED (8)
30
31/* 2.0 format */
32#define NVM_20_SEC_BITS (24)
33#define NVM_20_RESERVED (8)
34
35enum {
36 NVM_OCSSD_SPEC_12 = 12,
37 NVM_OCSSD_SPEC_20 = 20,
38};
39
40struct ppa_addr {
41 /* Generic structure for all addresses */
42 union {
43 /* generic device format */
44 struct {
45 u64 ch : NVM_GEN_CH_BITS;
46 u64 lun : NVM_GEN_LUN_BITS;
47 u64 blk : NVM_GEN_BLK_BITS;
48 u64 reserved : NVM_GEN_RESERVED;
49 } a;
50
51 /* 1.2 device format */
52 struct {
53 u64 ch : NVM_GEN_CH_BITS;
54 u64 lun : NVM_GEN_LUN_BITS;
55 u64 blk : NVM_GEN_BLK_BITS;
56 u64 pg : NVM_12_PG_BITS;
57 u64 pl : NVM_12_PL_BITS;
58 u64 sec : NVM_12_SEC_BITS;
59 u64 reserved : NVM_12_RESERVED;
60 } g;
61
62 /* 2.0 device format */
63 struct {
64 u64 grp : NVM_GEN_CH_BITS;
65 u64 pu : NVM_GEN_LUN_BITS;
66 u64 chk : NVM_GEN_BLK_BITS;
67 u64 sec : NVM_20_SEC_BITS;
68 u64 reserved : NVM_20_RESERVED;
69 } m;
70
71 struct {
72 u64 line : 63;
73 u64 is_cached : 1;
74 } c;
75
76 u64 ppa;
77 };
78};
79
80struct nvm_rq;
81struct nvm_id;
82struct nvm_dev;
83struct nvm_tgt_dev;
84struct nvm_chk_meta;
85
86typedef int (nvm_id_fn)(struct nvm_dev *);
87typedef int (nvm_op_bb_tbl_fn)(struct nvm_dev *, struct ppa_addr, u8 *);
88typedef int (nvm_op_set_bb_fn)(struct nvm_dev *, struct ppa_addr *, int, int);
89typedef int (nvm_get_chk_meta_fn)(struct nvm_dev *, sector_t, int,
90 struct nvm_chk_meta *);
91typedef int (nvm_submit_io_fn)(struct nvm_dev *, struct nvm_rq *);
92typedef int (nvm_submit_io_sync_fn)(struct nvm_dev *, struct nvm_rq *);
93typedef void *(nvm_create_dma_pool_fn)(struct nvm_dev *, char *, int);
94typedef void (nvm_destroy_dma_pool_fn)(void *);
95typedef void *(nvm_dev_dma_alloc_fn)(struct nvm_dev *, void *, gfp_t,
96 dma_addr_t *);
97typedef void (nvm_dev_dma_free_fn)(void *, void*, dma_addr_t);
98
99struct nvm_dev_ops {
100 nvm_id_fn *identity;
101 nvm_op_bb_tbl_fn *get_bb_tbl;
102 nvm_op_set_bb_fn *set_bb_tbl;
103
104 nvm_get_chk_meta_fn *get_chk_meta;
105
106 nvm_submit_io_fn *submit_io;
107 nvm_submit_io_sync_fn *submit_io_sync;
108
109 nvm_create_dma_pool_fn *create_dma_pool;
110 nvm_destroy_dma_pool_fn *destroy_dma_pool;
111 nvm_dev_dma_alloc_fn *dev_dma_alloc;
112 nvm_dev_dma_free_fn *dev_dma_free;
113};
114
115#ifdef CONFIG_NVM
116
117#include <linux/blkdev.h>
118#include <linux/file.h>
119#include <linux/dmapool.h>
120#include <uapi/linux/lightnvm.h>
121
122enum {
123 /* HW Responsibilities */
124 NVM_RSP_L2P = 1 << 0,
125 NVM_RSP_ECC = 1 << 1,
126
127 /* Physical Adressing Mode */
128 NVM_ADDRMODE_LINEAR = 0,
129 NVM_ADDRMODE_CHANNEL = 1,
130
131 /* Plane programming mode for LUN */
132 NVM_PLANE_SINGLE = 1,
133 NVM_PLANE_DOUBLE = 2,
134 NVM_PLANE_QUAD = 4,
135
136 /* Status codes */
137 NVM_RSP_SUCCESS = 0x0,
138 NVM_RSP_NOT_CHANGEABLE = 0x1,
139 NVM_RSP_ERR_FAILWRITE = 0x40ff,
140 NVM_RSP_ERR_EMPTYPAGE = 0x42ff,
141 NVM_RSP_ERR_FAILECC = 0x4281,
142 NVM_RSP_ERR_FAILCRC = 0x4004,
143 NVM_RSP_WARN_HIGHECC = 0x4700,
144
145 /* Device opcodes */
146 NVM_OP_PWRITE = 0x91,
147 NVM_OP_PREAD = 0x92,
148 NVM_OP_ERASE = 0x90,
149
150 /* PPA Command Flags */
151 NVM_IO_SNGL_ACCESS = 0x0,
152 NVM_IO_DUAL_ACCESS = 0x1,
153 NVM_IO_QUAD_ACCESS = 0x2,
154
155 /* NAND Access Modes */
156 NVM_IO_SUSPEND = 0x80,
157 NVM_IO_SLC_MODE = 0x100,
158 NVM_IO_SCRAMBLE_ENABLE = 0x200,
159
160 /* Block Types */
161 NVM_BLK_T_FREE = 0x0,
162 NVM_BLK_T_BAD = 0x1,
163 NVM_BLK_T_GRWN_BAD = 0x2,
164 NVM_BLK_T_DEV = 0x4,
165 NVM_BLK_T_HOST = 0x8,
166
167 /* Memory capabilities */
168 NVM_ID_CAP_SLC = 0x1,
169 NVM_ID_CAP_CMD_SUSPEND = 0x2,
170 NVM_ID_CAP_SCRAMBLE = 0x4,
171 NVM_ID_CAP_ENCRYPT = 0x8,
172
173 /* Memory types */
174 NVM_ID_FMTYPE_SLC = 0,
175 NVM_ID_FMTYPE_MLC = 1,
176
177 /* Device capabilities */
178 NVM_ID_DCAP_BBLKMGMT = 0x1,
179 NVM_UD_DCAP_ECC = 0x2,
180};
181
182struct nvm_id_lp_mlc {
183 u16 num_pairs;
184 u8 pairs[886];
185};
186
187struct nvm_id_lp_tbl {
188 __u8 id[8];
189 struct nvm_id_lp_mlc mlc;
190};
191
192struct nvm_addrf_12 {
193 u8 ch_len;
194 u8 lun_len;
195 u8 blk_len;
196 u8 pg_len;
197 u8 pln_len;
198 u8 sec_len;
199
200 u8 ch_offset;
201 u8 lun_offset;
202 u8 blk_offset;
203 u8 pg_offset;
204 u8 pln_offset;
205 u8 sec_offset;
206
207 u64 ch_mask;
208 u64 lun_mask;
209 u64 blk_mask;
210 u64 pg_mask;
211 u64 pln_mask;
212 u64 sec_mask;
213};
214
215struct nvm_addrf {
216 u8 ch_len;
217 u8 lun_len;
218 u8 chk_len;
219 u8 sec_len;
220 u8 rsv_len[2];
221
222 u8 ch_offset;
223 u8 lun_offset;
224 u8 chk_offset;
225 u8 sec_offset;
226 u8 rsv_off[2];
227
228 u64 ch_mask;
229 u64 lun_mask;
230 u64 chk_mask;
231 u64 sec_mask;
232 u64 rsv_mask[2];
233};
234
235enum {
236 /* Chunk states */
237 NVM_CHK_ST_FREE = 1 << 0,
238 NVM_CHK_ST_CLOSED = 1 << 1,
239 NVM_CHK_ST_OPEN = 1 << 2,
240 NVM_CHK_ST_OFFLINE = 1 << 3,
241
242 /* Chunk types */
243 NVM_CHK_TP_W_SEQ = 1 << 0,
244 NVM_CHK_TP_W_RAN = 1 << 1,
245 NVM_CHK_TP_SZ_SPEC = 1 << 4,
246};
247
248/*
249 * Note: The structure size is linked to nvme_nvm_chk_meta such that the same
250 * buffer can be used when converting from little endian to cpu addressing.
251 */
252struct nvm_chk_meta {
253 u8 state;
254 u8 type;
255 u8 wi;
256 u8 rsvd[5];
257 u64 slba;
258 u64 cnlb;
259 u64 wp;
260};
261
262struct nvm_target {
263 struct list_head list;
264 struct nvm_tgt_dev *dev;
265 struct nvm_tgt_type *type;
266 struct gendisk *disk;
267};
268
269#define ADDR_EMPTY (~0ULL)
270
271#define NVM_TARGET_DEFAULT_OP (101)
272#define NVM_TARGET_MIN_OP (3)
273#define NVM_TARGET_MAX_OP (80)
274
275#define NVM_VERSION_MAJOR 1
276#define NVM_VERSION_MINOR 0
277#define NVM_VERSION_PATCH 0
278
279#define NVM_MAX_VLBA (64) /* max logical blocks in a vector command */
280
281struct nvm_rq;
282typedef void (nvm_end_io_fn)(struct nvm_rq *);
283
284struct nvm_rq {
285 struct nvm_tgt_dev *dev;
286
287 struct bio *bio;
288
289 union {
290 struct ppa_addr ppa_addr;
291 dma_addr_t dma_ppa_list;
292 };
293
294 struct ppa_addr *ppa_list;
295
296 void *meta_list;
297 dma_addr_t dma_meta_list;
298
299 nvm_end_io_fn *end_io;
300
301 uint8_t opcode;
302 uint16_t nr_ppas;
303 uint16_t flags;
304
305 u64 ppa_status; /* ppa media status */
306 int error;
307
308 int is_seq; /* Sequential hint flag. 1.2 only */
309
310 void *private;
311};
312
313static inline struct nvm_rq *nvm_rq_from_pdu(void *pdu)
314{
315 return pdu - sizeof(struct nvm_rq);
316}
317
318static inline void *nvm_rq_to_pdu(struct nvm_rq *rqdata)
319{
320 return rqdata + 1;
321}
322
323static inline struct ppa_addr *nvm_rq_to_ppa_list(struct nvm_rq *rqd)
324{
325 return (rqd->nr_ppas > 1) ? rqd->ppa_list : &rqd->ppa_addr;
326}
327
328enum {
329 NVM_BLK_ST_FREE = 0x1, /* Free block */
330 NVM_BLK_ST_TGT = 0x2, /* Block in use by target */
331 NVM_BLK_ST_BAD = 0x8, /* Bad block */
332};
333
334/* Instance geometry */
335struct nvm_geo {
336 /* device reported version */
337 u8 major_ver_id;
338 u8 minor_ver_id;
339
340 /* kernel short version */
341 u8 version;
342
343 /* instance specific geometry */
344 int num_ch;
345 int num_lun; /* per channel */
346
347 /* calculated values */
348 int all_luns; /* across channels */
349 int all_chunks; /* across channels */
350
351 int op; /* over-provision in instance */
352
353 sector_t total_secs; /* across channels */
354
355 /* chunk geometry */
356 u32 num_chk; /* chunks per lun */
357 u32 clba; /* sectors per chunk */
358 u16 csecs; /* sector size */
359 u16 sos; /* out-of-band area size */
360 bool ext; /* metadata in extended data buffer */
361
362 /* device write constrains */
363 u32 ws_min; /* minimum write size */
364 u32 ws_opt; /* optimal write size */
365 u32 mw_cunits; /* distance required for successful read */
366 u32 maxoc; /* maximum open chunks */
367 u32 maxocpu; /* maximum open chunks per parallel unit */
368
369 /* device capabilities */
370 u32 mccap;
371
372 /* device timings */
373 u32 trdt; /* Avg. Tread (ns) */
374 u32 trdm; /* Max Tread (ns) */
375 u32 tprt; /* Avg. Tprog (ns) */
376 u32 tprm; /* Max Tprog (ns) */
377 u32 tbet; /* Avg. Terase (ns) */
378 u32 tbem; /* Max Terase (ns) */
379
380 /* generic address format */
381 struct nvm_addrf addrf;
382
383 /* 1.2 compatibility */
384 u8 vmnt;
385 u32 cap;
386 u32 dom;
387
388 u8 mtype;
389 u8 fmtype;
390
391 u16 cpar;
392 u32 mpos;
393
394 u8 num_pln;
395 u8 pln_mode;
396 u16 num_pg;
397 u16 fpg_sz;
398};
399
400/* sub-device structure */
401struct nvm_tgt_dev {
402 /* Device information */
403 struct nvm_geo geo;
404
405 /* Base ppas for target LUNs */
406 struct ppa_addr *luns;
407
408 struct request_queue *q;
409
410 struct nvm_dev *parent;
411 void *map;
412};
413
414struct nvm_dev {
415 struct nvm_dev_ops *ops;
416
417 struct list_head devices;
418
419 /* Device information */
420 struct nvm_geo geo;
421
422 unsigned long *lun_map;
423 void *dma_pool;
424
425 /* Backend device */
426 struct request_queue *q;
427 char name[DISK_NAME_LEN];
428 void *private_data;
429
430 void *rmap;
431
432 struct mutex mlock;
433 spinlock_t lock;
434
435 /* target management */
436 struct list_head area_list;
437 struct list_head targets;
438};
439
440static inline struct ppa_addr generic_to_dev_addr(struct nvm_dev *dev,
441 struct ppa_addr r)
442{
443 struct nvm_geo *geo = &dev->geo;
444 struct ppa_addr l;
445
446 if (geo->version == NVM_OCSSD_SPEC_12) {
447 struct nvm_addrf_12 *ppaf = (struct nvm_addrf_12 *)&geo->addrf;
448
449 l.ppa = ((u64)r.g.ch) << ppaf->ch_offset;
450 l.ppa |= ((u64)r.g.lun) << ppaf->lun_offset;
451 l.ppa |= ((u64)r.g.blk) << ppaf->blk_offset;
452 l.ppa |= ((u64)r.g.pg) << ppaf->pg_offset;
453 l.ppa |= ((u64)r.g.pl) << ppaf->pln_offset;
454 l.ppa |= ((u64)r.g.sec) << ppaf->sec_offset;
455 } else {
456 struct nvm_addrf *lbaf = &geo->addrf;
457
458 l.ppa = ((u64)r.m.grp) << lbaf->ch_offset;
459 l.ppa |= ((u64)r.m.pu) << lbaf->lun_offset;
460 l.ppa |= ((u64)r.m.chk) << lbaf->chk_offset;
461 l.ppa |= ((u64)r.m.sec) << lbaf->sec_offset;
462 }
463
464 return l;
465}
466
467static inline struct ppa_addr dev_to_generic_addr(struct nvm_dev *dev,
468 struct ppa_addr r)
469{
470 struct nvm_geo *geo = &dev->geo;
471 struct ppa_addr l;
472
473 l.ppa = 0;
474
475 if (geo->version == NVM_OCSSD_SPEC_12) {
476 struct nvm_addrf_12 *ppaf = (struct nvm_addrf_12 *)&geo->addrf;
477
478 l.g.ch = (r.ppa & ppaf->ch_mask) >> ppaf->ch_offset;
479 l.g.lun = (r.ppa & ppaf->lun_mask) >> ppaf->lun_offset;
480 l.g.blk = (r.ppa & ppaf->blk_mask) >> ppaf->blk_offset;
481 l.g.pg = (r.ppa & ppaf->pg_mask) >> ppaf->pg_offset;
482 l.g.pl = (r.ppa & ppaf->pln_mask) >> ppaf->pln_offset;
483 l.g.sec = (r.ppa & ppaf->sec_mask) >> ppaf->sec_offset;
484 } else {
485 struct nvm_addrf *lbaf = &geo->addrf;
486
487 l.m.grp = (r.ppa & lbaf->ch_mask) >> lbaf->ch_offset;
488 l.m.pu = (r.ppa & lbaf->lun_mask) >> lbaf->lun_offset;
489 l.m.chk = (r.ppa & lbaf->chk_mask) >> lbaf->chk_offset;
490 l.m.sec = (r.ppa & lbaf->sec_mask) >> lbaf->sec_offset;
491 }
492
493 return l;
494}
495
496static inline u64 dev_to_chunk_addr(struct nvm_dev *dev, void *addrf,
497 struct ppa_addr p)
498{
499 struct nvm_geo *geo = &dev->geo;
500 u64 caddr;
501
502 if (geo->version == NVM_OCSSD_SPEC_12) {
503 struct nvm_addrf_12 *ppaf = (struct nvm_addrf_12 *)addrf;
504
505 caddr = (u64)p.g.pg << ppaf->pg_offset;
506 caddr |= (u64)p.g.pl << ppaf->pln_offset;
507 caddr |= (u64)p.g.sec << ppaf->sec_offset;
508 } else {
509 caddr = p.m.sec;
510 }
511
512 return caddr;
513}
514
515static inline struct ppa_addr nvm_ppa32_to_ppa64(struct nvm_dev *dev,
516 void *addrf, u32 ppa32)
517{
518 struct ppa_addr ppa64;
519
520 ppa64.ppa = 0;
521
522 if (ppa32 == -1) {
523 ppa64.ppa = ADDR_EMPTY;
524 } else if (ppa32 & (1U << 31)) {
525 ppa64.c.line = ppa32 & ((~0U) >> 1);
526 ppa64.c.is_cached = 1;
527 } else {
528 struct nvm_geo *geo = &dev->geo;
529
530 if (geo->version == NVM_OCSSD_SPEC_12) {
531 struct nvm_addrf_12 *ppaf = addrf;
532
533 ppa64.g.ch = (ppa32 & ppaf->ch_mask) >>
534 ppaf->ch_offset;
535 ppa64.g.lun = (ppa32 & ppaf->lun_mask) >>
536 ppaf->lun_offset;
537 ppa64.g.blk = (ppa32 & ppaf->blk_mask) >>
538 ppaf->blk_offset;
539 ppa64.g.pg = (ppa32 & ppaf->pg_mask) >>
540 ppaf->pg_offset;
541 ppa64.g.pl = (ppa32 & ppaf->pln_mask) >>
542 ppaf->pln_offset;
543 ppa64.g.sec = (ppa32 & ppaf->sec_mask) >>
544 ppaf->sec_offset;
545 } else {
546 struct nvm_addrf *lbaf = addrf;
547
548 ppa64.m.grp = (ppa32 & lbaf->ch_mask) >>
549 lbaf->ch_offset;
550 ppa64.m.pu = (ppa32 & lbaf->lun_mask) >>
551 lbaf->lun_offset;
552 ppa64.m.chk = (ppa32 & lbaf->chk_mask) >>
553 lbaf->chk_offset;
554 ppa64.m.sec = (ppa32 & lbaf->sec_mask) >>
555 lbaf->sec_offset;
556 }
557 }
558
559 return ppa64;
560}
561
562static inline u32 nvm_ppa64_to_ppa32(struct nvm_dev *dev,
563 void *addrf, struct ppa_addr ppa64)
564{
565 u32 ppa32 = 0;
566
567 if (ppa64.ppa == ADDR_EMPTY) {
568 ppa32 = ~0U;
569 } else if (ppa64.c.is_cached) {
570 ppa32 |= ppa64.c.line;
571 ppa32 |= 1U << 31;
572 } else {
573 struct nvm_geo *geo = &dev->geo;
574
575 if (geo->version == NVM_OCSSD_SPEC_12) {
576 struct nvm_addrf_12 *ppaf = addrf;
577
578 ppa32 |= ppa64.g.ch << ppaf->ch_offset;
579 ppa32 |= ppa64.g.lun << ppaf->lun_offset;
580 ppa32 |= ppa64.g.blk << ppaf->blk_offset;
581 ppa32 |= ppa64.g.pg << ppaf->pg_offset;
582 ppa32 |= ppa64.g.pl << ppaf->pln_offset;
583 ppa32 |= ppa64.g.sec << ppaf->sec_offset;
584 } else {
585 struct nvm_addrf *lbaf = addrf;
586
587 ppa32 |= ppa64.m.grp << lbaf->ch_offset;
588 ppa32 |= ppa64.m.pu << lbaf->lun_offset;
589 ppa32 |= ppa64.m.chk << lbaf->chk_offset;
590 ppa32 |= ppa64.m.sec << lbaf->sec_offset;
591 }
592 }
593
594 return ppa32;
595}
596
597static inline int nvm_next_ppa_in_chk(struct nvm_tgt_dev *dev,
598 struct ppa_addr *ppa)
599{
600 struct nvm_geo *geo = &dev->geo;
601 int last = 0;
602
603 if (geo->version == NVM_OCSSD_SPEC_12) {
604 int sec = ppa->g.sec;
605
606 sec++;
607 if (sec == geo->ws_min) {
608 int pg = ppa->g.pg;
609
610 sec = 0;
611 pg++;
612 if (pg == geo->num_pg) {
613 int pl = ppa->g.pl;
614
615 pg = 0;
616 pl++;
617 if (pl == geo->num_pln)
618 last = 1;
619
620 ppa->g.pl = pl;
621 }
622 ppa->g.pg = pg;
623 }
624 ppa->g.sec = sec;
625 } else {
626 ppa->m.sec++;
627 if (ppa->m.sec == geo->clba)
628 last = 1;
629 }
630
631 return last;
632}
633
634typedef blk_qc_t (nvm_tgt_make_rq_fn)(struct request_queue *, struct bio *);
635typedef sector_t (nvm_tgt_capacity_fn)(void *);
636typedef void *(nvm_tgt_init_fn)(struct nvm_tgt_dev *, struct gendisk *,
637 int flags);
638typedef void (nvm_tgt_exit_fn)(void *, bool);
639typedef int (nvm_tgt_sysfs_init_fn)(struct gendisk *);
640typedef void (nvm_tgt_sysfs_exit_fn)(struct gendisk *);
641
642enum {
643 NVM_TGT_F_DEV_L2P = 0,
644 NVM_TGT_F_HOST_L2P = 1 << 0,
645};
646
647struct nvm_tgt_type {
648 const char *name;
649 unsigned int version[3];
650 int flags;
651
652 /* target entry points */
653 nvm_tgt_make_rq_fn *make_rq;
654 nvm_tgt_capacity_fn *capacity;
655
656 /* module-specific init/teardown */
657 nvm_tgt_init_fn *init;
658 nvm_tgt_exit_fn *exit;
659
660 /* sysfs */
661 nvm_tgt_sysfs_init_fn *sysfs_init;
662 nvm_tgt_sysfs_exit_fn *sysfs_exit;
663
664 /* For internal use */
665 struct list_head list;
666 struct module *owner;
667};
668
669extern int nvm_register_tgt_type(struct nvm_tgt_type *);
670extern void nvm_unregister_tgt_type(struct nvm_tgt_type *);
671
672extern void *nvm_dev_dma_alloc(struct nvm_dev *, gfp_t, dma_addr_t *);
673extern void nvm_dev_dma_free(struct nvm_dev *, void *, dma_addr_t);
674
675extern struct nvm_dev *nvm_alloc_dev(int);
676extern int nvm_register(struct nvm_dev *);
677extern void nvm_unregister(struct nvm_dev *);
678
679extern int nvm_get_chunk_meta(struct nvm_tgt_dev *, struct ppa_addr,
680 int, struct nvm_chk_meta *);
681extern int nvm_set_chunk_meta(struct nvm_tgt_dev *, struct ppa_addr *,
682 int, int);
683extern int nvm_submit_io(struct nvm_tgt_dev *, struct nvm_rq *);
684extern int nvm_submit_io_sync(struct nvm_tgt_dev *, struct nvm_rq *);
685extern void nvm_end_io(struct nvm_rq *);
686
687#else /* CONFIG_NVM */
688struct nvm_dev_ops;
689
690static inline struct nvm_dev *nvm_alloc_dev(int node)
691{
692 return ERR_PTR(-EINVAL);
693}
694static inline int nvm_register(struct nvm_dev *dev)
695{
696 return -EINVAL;
697}
698static inline void nvm_unregister(struct nvm_dev *dev) {}
699#endif /* CONFIG_NVM */
700#endif /* LIGHTNVM.H */
701