1 | /* |
2 | * Marvell MBUS common definitions. |
3 | * |
4 | * Copyright (C) 2008 Marvell Semiconductor |
5 | * |
6 | * This file is licensed under the terms of the GNU General Public |
7 | * License version 2. This program is licensed "as is" without any |
8 | * warranty of any kind, whether express or implied. |
9 | */ |
10 | |
11 | #ifndef __LINUX_MBUS_H |
12 | #define __LINUX_MBUS_H |
13 | |
14 | #include <linux/errno.h> |
15 | |
16 | struct resource; |
17 | |
18 | struct mbus_dram_target_info |
19 | { |
20 | /* |
21 | * The 4-bit MBUS target ID of the DRAM controller. |
22 | */ |
23 | u8 mbus_dram_target_id; |
24 | |
25 | /* |
26 | * The base address, size, and MBUS attribute ID for each |
27 | * of the possible DRAM chip selects. Peripherals are |
28 | * required to support at least 4 decode windows. |
29 | */ |
30 | int num_cs; |
31 | struct mbus_dram_window { |
32 | u8 cs_index; |
33 | u8 mbus_attr; |
34 | u64 base; |
35 | u64 size; |
36 | } cs[4]; |
37 | }; |
38 | |
39 | /* Flags for PCI/PCIe address decoding regions */ |
40 | #define MVEBU_MBUS_PCI_IO 0x1 |
41 | #define MVEBU_MBUS_PCI_MEM 0x2 |
42 | #define MVEBU_MBUS_PCI_WA 0x3 |
43 | |
44 | /* |
45 | * Magic value that explicits that we don't need a remapping-capable |
46 | * address decoding window. |
47 | */ |
48 | #define MVEBU_MBUS_NO_REMAP (0xffffffff) |
49 | |
50 | /* Maximum size of a mbus window name */ |
51 | #define MVEBU_MBUS_MAX_WINNAME_SZ 32 |
52 | |
53 | /* |
54 | * The Marvell mbus is to be found only on SOCs from the Orion family |
55 | * at the moment. Provide a dummy stub for other architectures. |
56 | */ |
57 | #ifdef CONFIG_PLAT_ORION |
58 | extern const struct mbus_dram_target_info *mv_mbus_dram_info(void); |
59 | extern const struct mbus_dram_target_info *mv_mbus_dram_info_nooverlap(void); |
60 | int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 *size, u8 *target, |
61 | u8 *attr); |
62 | #else |
63 | static inline const struct mbus_dram_target_info *mv_mbus_dram_info(void) |
64 | { |
65 | return NULL; |
66 | } |
67 | static inline const struct mbus_dram_target_info *mv_mbus_dram_info_nooverlap(void) |
68 | { |
69 | return NULL; |
70 | } |
71 | static inline int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 *size, |
72 | u8 *target, u8 *attr) |
73 | { |
74 | /* |
75 | * On all ARM32 MVEBU platforms with MBus support, this stub |
76 | * function will not get called. The real function from the |
77 | * MBus driver is called instead. ARM64 MVEBU platforms like |
78 | * the Armada 3700 could use the mv_xor device driver which calls |
79 | * into this function |
80 | */ |
81 | return -EINVAL; |
82 | } |
83 | #endif |
84 | |
85 | #ifdef CONFIG_MVEBU_MBUS |
86 | int mvebu_mbus_save_cpu_target(u32 __iomem *store_addr); |
87 | void mvebu_mbus_get_pcie_mem_aperture(struct resource *res); |
88 | void mvebu_mbus_get_pcie_io_aperture(struct resource *res); |
89 | int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr); |
90 | int mvebu_mbus_add_window_remap_by_id(unsigned int target, |
91 | unsigned int attribute, |
92 | phys_addr_t base, size_t size, |
93 | phys_addr_t remap); |
94 | int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute, |
95 | phys_addr_t base, size_t size); |
96 | int mvebu_mbus_del_window(phys_addr_t base, size_t size); |
97 | int mvebu_mbus_init(const char *soc, phys_addr_t mbus_phys_base, |
98 | size_t mbus_size, phys_addr_t sdram_phys_base, |
99 | size_t sdram_size); |
100 | int mvebu_mbus_dt_init(bool is_coherent); |
101 | #else |
102 | static inline int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, |
103 | u8 *attr) |
104 | { |
105 | return -EINVAL; |
106 | } |
107 | #endif /* CONFIG_MVEBU_MBUS */ |
108 | |
109 | #endif /* __LINUX_MBUS_H */ |
110 | |